1. Record GmSAT/SSSAT and PBTI Reliability in Si-Passivated Ge nFinFETs by Improved Gate-Stack Surface Preparation
- Author
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Guillaume Boccardi, Hiroaki Arimura, Roger Loo, Samuel Suhard, Daire J. Cott, Thierry Conard, Naoto Horiguchi, L.-A. Ragnarsson, V. De Heyn, Jerome Mitard, Dan Mocuta, Liesbeth Witters, H. Dekkers, D. H. van Dorp, Nadine Collaert, and Kurt Wostyn
- Subjects
010302 applied physics ,Electron mobility ,Record value ,Materials science ,Silicon ,Nanowire ,Analytical chemistry ,chemistry.chemical_element ,Germanium ,01 natural sciences ,Electronic, Optical and Magnetic Materials ,Hafnium ,chemistry ,Gate oxide ,0103 physical sciences ,Electrical and Electronic Engineering ,Metal gate - Abstract
This article reports Si-passivated Ge nFinFETs with significantly improved GmSAT/SSSAT and positive bias temperature instability (PBTI) reliability enabled by an improved replacement metal gate (RMG) high- ${k}$ last process. SiO2 dummy gate oxide (DGO) deposition on Ge fin is shown to form (Si x )Ge1- x O y , which is, compared to a pure SiO2, more difficult to remove completely during the dry clean prior to the gate-stack formation. By extending the DGO removal clean, improved PBTI reliability, reduced ${D}_{{\text {IT}}}$ , and increased electron mobility are demonstrated. Moreover, by suppressing the Ge channel oxidation through the choice of less-oxidizing DGO or inserting an Si-cap layer prior to the DGO deposition, a greatly improved long-channel electron mobility is obtained at a scaled fin width. Finally, together with the PBTI maximum ${V}_{{\text {OV}}}$ of 0.13 V, the best GmSAT/SSSAT of 5.4 is achieved, which is today’s record value among the sub-100-nm- ${L}_{g}$ n-channel Ge Fin and gate-all-around nanowire FETs. These results clearly show the importance of the pre-gate-stack channel surface preparation on the scaled Ge FinFETs to benefit from a previously optimized Si-passivated Ge gate-stack.
- Published
- 2019
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