1. Non-TMR SEU-Hardening Techniques for SiGe HBT Shift Registers and Clock Buffers
- Author
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S.D. Phillips, B.A. Randall, Edward P. Wilcox, Devon Post, Erik S. Daniel, Paul W. Marshall, Larry Richmond, William Mathes, Jonathan A. Pellish, Barry K. Gilbert, John D. Cressler, and Martin A. Carts
- Subjects
Nuclear and High Energy Physics ,Materials science ,business.industry ,Computer science ,Heterojunction bipolar transistor ,Electrical engineering ,Electrical element ,Hardware_PERFORMANCEANDRELIABILITY ,Clock skew ,Upset ,Silicon-germanium ,chemistry.chemical_compound ,Nuclear Energy and Engineering ,chemistry ,Single event upset ,Hardening (metallurgy) ,Hardware_INTEGRATEDCIRCUITS ,Electronic engineering ,Optoelectronics ,Current-mode logic ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Electrical and Electronic Engineering ,business ,Hardware_LOGICDESIGN ,Shift register - Abstract
We report new results from both broad-beam, heavy-ion and proton experiments for circuit-level RHBD techniques in SiGe digital logic. Redundant circuit elements within the latches are used to significantly reduce single-event upset rates in shift registers and clock paths, without resorting to TMR techniques.
- Published
- 2010