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The high peak mobility of 509 cm2/ $\text {V}\cdot \text {s}$ of the chemical vapor deposition -grown GeSn pMOSFETs is obtained using 1-nm Ge cap. The Ge cap on GeSn can reduce the scattering of oxide/interface charges and surface roughness for the holes in the GeSn quantum wells. However, the thick cap induces holes in the Ge cap itself, leading lower mobility than GeSn channels. The on current is enhanced by external stress due to the effective mass reduction. The normalized noise power density of the GeSn devices decreases with increasing Ge cap thickness, indicating the carrier number fluctuation and correlated mobility fluctuation are suppressed when the holes are away from interface.

The electron mobility in junctionless (JL) Ge nanowire nFETs with the $\langle 110\rangle $ channel direction is calculated and compared with experimental data. The calculation of the electron mobility is based on the Kubo–Greenwood formula. The wave functions are obtained by solving the self-consistent Poisson–Schrodinger equation. Phonon scattering, surface roughness scattering, and Coulomb scattering (CS) by interface charges and channel charges are considered. Carrier screening on Coulomb charges is calculated using Lindhard’s screening theory. At low electron densities, the JL channels have lower electron mobility than inversion-mode (IM) channels due to CS from channel charges. At high electron densities, CS in JL channels is effectively reduced by screening, resulting in mobility comparable with the IM channels. The L4 electrons have higher mobility than $\text{L}4^\prime $ electrons. Applying uniaxial tensile strain along the channel can lower the energy of L4 valleys to enhance the channel mobility.

The performance variation caused by the stress field near a through-silicon via (TSV) is measured using 28-nm node devices across 12-in wafers. The TSV is fabricated by a via-last process. The back-end-of-line dielectrics on TSV cause the asymmetric stress field, i.e., the absolute value of radial stress ( $\vert \sigma _{r}\vert )$ does not equal to that of tangential stress ( $\vert \sigma _{\theta }\vert )$ on silicon and leads to the asymmetric keep-out zone (KOZ), different from previously reported. A modified KOZ model with the asymmetric radial and tangential stress field is proposed and verified by 3-D finite-element analysis simulation and experiment data. The physics behind the asymmetry is also described. Comparable KOZ size for nFETs and pFETs is observed.

The low channel doping concentrations of 1.2×1019 cm−3 to deplete the channel and the high S/D doping of 1.2×1020 cm−3 to reduce the S/D resistance are achieved simultaneously by selective laser annealing on the same CVD P-doped epi-Ge on SOI without ion implantation. The device with Wfin down to 7 nm, EOT = 2.2 nm, and Lch = 60 nm has Ion = 1146 μA/pm, Ion/Ioff = 2×106, and SS = 95 mV/dec. The Ion can be further boost to 1235 μA/μm with external uniaxial tensile strain of 0.16%. The self-heating effect is responsible in part for such high Ion, because the high device temperature can reduce the dominant impurity scattering in the channel. The increasing mobility with increasing temperature indicates the impurity scattering is dominant. The lower low frequency noise is observed with junctionless (JL) gate-all-around (GAA) FETs than planar inversion mode (INV) devices due to the bulk conduction nature of JL FETs.

Impact of via-last through-silicon via (TSV) on 28nm node devices is investigated. The stress field of TSV is affected by the back-end-of-line (BEOL) dielectrics. The absolute value of radial stress (|σr|) is different from that of tangential stress (|σθ|) on silicon, which leads to the asymmetric keep-out zone (KOZ). The physics behind the asymmetry is also described. A modified KOZ model considering the asymmetric stress field is proposed and verified by experiment data.

The record high peak mobility of ∼1050 cm2/V-s on (001) Ge substrate is demonstrated in NFET. High-quality Ge/GeO 2 interface is ensured by rapid thermal oxidation (RTO) and remote ozone plasma treatment. The best achieved subthreshold swing is 150mV/dec and the on/off ratio is 2×104. The low defective n+/p junction produced a record high on/off ratio of 2×105, an ideality factor of 1.05 and strong electroluminescence. For the first time, it is reported that the uniaxial tensile strain (0.08%) on channel direction gives the best mobility enhancement (12%) among the different strain configurations, consistent with theoretical calculation.

The electron mobility of n-channel metal-oxide-semiconductor field-effect transistors using Ge/GeO2/Al2O3 gate stack on (001) Ge substrates is analyzed theoretically and experimentally. Phonon scattering, Coulomb scattering, and interface roughness scattering are taken into account. The Ge peak mobility exceeding Si universal in our device by a factor of 1.3 is due to the reduction of Coulomb scattering of the interface states. As compared to Si, the faster roll-off of the Ge mobility at the effective field larger than 0.3 MV/cm is due to larger interface roughness scattering.

Well-behaved Ge n-channel metal-oxide-semiconductor field-effect transistors on (001) substrates with dispersion-free, high on/off ratio, and high peak mobility are demonstrated. The interface trap density is effectively reduced down to 5 × 1011 cm−2 eV−1 near midgap by GeO2 passivation using rapid thermal oxidation, resulting in high peak mobility of ∼1050 cm2/Vs. The fast roll-off of the mobility at high electric field is probably due to the large surface roughness scattering. By applying uniaxial 〈110〉 tensile strain (0.08%) on 〈110〉 channel direction, the best mobility enhancement (12%) can be achieved. The calculated strain responses with proper stress configurations are consistent with experimental results.