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Subwavelength grating (SWG) metamaterials have garnered a great interest for their singular capability to shape the material properties and the propagation of light, allowing the realization of devices with unprecedented performance. However, practical SWG implementations are limited by fabrication constraints, such as minimum feature size, that restrict the available design space or compromise compatibility with high-volume fabrication technologies. Indeed, most successful SWG realizations so far relied on electron-beam lithographic techniques, compromising the scalability of the approach. Here, we report the experimental demonstration of an SWG metamaterial engineered beam splitter fabricated with deep-ultraviolet immersion lithography in a 300-mm silicon-on-insulator technology. The metamaterial beam splitter exhibits high performance over a measured bandwidth exceeding 186 nm centered at 1550 nm. These results open a new route for the development of scalable silicon photonic circuits exploiting flexible metamaterial engineering.

Vertical p-i-n lasers integrated by wafer-bonding and regrowth on a heterogeneous InP-on-SOI wafer are presented. We demonstrate for the first time lasers based on regrown III-V active regions efficiently coupled to Si-photonic DBR cavities.

Vertical p-i-n AlGaInAs lasers obtained from a single Selective Area Growth (SAG) step on a thin InP layer bonded to silicon wafers are presented. A PL extension from 1490 nm to 1645 nm was demonstrated on InP-SOI wafer. Based on this result, a record of 155 nm wide spectral range was obtained for FP lasers on InP-SiO 2 /Si wafer.

We report on the CMOS-compatible hybrid III-V/Silicon platform developed in CEA-LETI. In order to follow the large-scale integration capabilities of silicon photonics, already available worldwide in 200mm or 300mm through different foundries, the development of CMOS-compatible process for the III-V integration is of major interest. The technological developments involve not only the hybridization on top of a mature silicon photonic front-end wafer through direct molecular bonding but the patterning of the III-V epitaxy layer, low access resistance contacts, as well as planar multilevel BEOL must also be investigated and optimized. Test vehicles for the process validation based on either distributed feedback (DFB) or distributed Bragg reflector (DBR) laser cavities were designed. A modular approach is proposed in order to minimize the impact on the already qualified silicon photonics devices. Next, a collective III–V die bonding and processing have been successfully developed in this platform. The collective bonding, based on a flexible template holder, allows for large scale die to wafer transfer in both 200 and 300mm. After the III-V substrate removal and III-V patterning relying on optimized dry etching processes, CMOS compatible metallization’s are used to realize ohmic contact on n-InP and P-InGaAs leading to contact resistivity in the range of 10−6 Ω·cm². While first demonstrations have been obtained through wafer bonding, the fabrication process was subsequently validated on III-V dies bonding with a fabrication yield of Fabry-Perot lasers of 97% in 200mm. A planarized two-metal-level BEOL was used to connect the devices, leading to a drastic reduction of series resistance between 5.5 and 7 Ω. Finally, the functionality of DFB and DBR lasers is demonstrated with SMSR up to 50 dB and maximum output power of 3 mW in CW. The overall technological features are expected improve the efficiency, density, and cost of silicon photonics PICs.

Hybrid integration of III-V materials onto silicon by direct bonding technique is a mature and promising approaches to develop advanced photonic integrated devices into the silicon photonics platform. In this approach, the III-V material stack is grown on an InP wafer in a unique epitaxial step prior to the direct bonding process onto the silicon-on-insulator wafer. Currently, no additional epitaxial regrowth steps are implemented after bonding. This can be seen as a huge limitation as compared to the III-V on III-V wafer mature technology where multi-regrowth steps are most often implemented. In this work, we have studied the material behavior of an InP membrane on silicon (InPoSi) under epitaxial regrowth conditions by metal-organic vapor phase epitaxy (MOVPE). MOVPE requires high-temperature elevation, typically above 600 °C. We show for the first time the appearance of voids at 400 °C in an InP seed (100 nm) directly-bonded onto a thermally oxidized Si substrate despite the use of a thick SiO2 oxide (200 nm) at the bonding interface. This phenomenon is explained by a weakening of the bonding interface while high-pressurized hydrogen is present. A kinetic study of the hydrogen lateral diffusion is carried out, enabling the assessment of its lateral diffusion length. To overcome the void formation, highly efficient outgassing trenches after bonding are demonstrated. Finally, high-quality AlGaInAs-based multi-quantum well (MQW) heterostructure surrounded by two InP layers was grown by MOVPE on InPoSi template patterned with outgassing trenches. This process is not only compatible with MOVPE regrowth conditions (650 °C under PH3) but also with conventional fabrication processes used for photonic devices.

This paper reports novel characteristic features of thermally-passivated Si nanoelectromechanical (NEM) beams fabricated via SOI-CMOS compatible processes with top-down hybrid EB/DUV lithography. Considerable difference of the resonance frequencies between the measurement results of the NEM beams with various lengths and the finite element simulation results suggests that effects of the undercut of the beam supports are serious for sub-micron beams. The resonance frequency of 332.57 MHz observed for an 800-nm-long beam is, to our knowledge, the highest ever as the fundamental resonance mode of lithographically-defined Si NEM beams. Clear change of the temperature dependence of the resonance frequencies with the varied beam lengths, observed for the first time, can be explained by considering effects of thermally-induced strain on the longer beams at higher temperatures.

In this study, fabrication of monolithic triple junction (3J) GaInP/AlGaAs/Si solar cells is reported by different wafer bonding approaches: (i) the most straightforward, direct GaAs/Si wafer bonding; (ii) an innovative 2-step approach combining epitaxy of GaAs bonding layer on Si cell followed by GaAs/GaAs direct wafer bonding; and (iii) Surface-Activated GaAs/Si wafer Bonding (SAB). Bonding interfaces properties are comparatively studied, and the performance of resulting III-V on Si triple junction devices is examined. Open-circuit voltages close to 2.9V are obtained in all cases, but large differences in fill factors between the bonding methods are observed, probably due to the presence of an oxide layer.

session poster (I43); International audience; Monolithic two-terminal III-V on Si dual-junction (2J) solar cells were fabricated by means of Surface-Activated direct wafer Bonding (SAB). Al 0.2 Ga 0.8 As single-junction cells are grown on GaAs substrate by Metal-Organic Vapor Phase Epitaxy (MOVPE) and bonded at room temperature to independently fabricated Si solar cells. The n+-GaAs//n+-Si bonding interface is characterized by Transmission Electron Microscopy (TEM) revealing a 2-3 nm thick amorphous interlayer. The performance of the 1 cm 2 tandem cells, designed for low concentration applications, was studied by External Quantum Efficiency (EQE) and J-V measurements showing a power conversion efficiency of 17% under one-sun AM1.5G spectrum. To our knowledge, this is the highest efficiency ever reported for a wafer-bonded 2J III-V on Si solar cell. Limitations to performance have been identified and therefore higher efficiencies are expected.

In this work, a comprehensive, predictive and quantitative model of a whole gas analyzer is provided in order to facilitate the design of such high performance devices. All the pre-analytical (gas separation) and analytical (detection and readout) stages have been modeled and experimentally calibrated. Heterogeneous simulations have been used to quantify the impact of the whole architecture on the output characteristic of the gas analyzer. Finally, the model of the NEMS sensor and the chromatography micro-column assembly has been experimentally validated with TEOX (toluene, ethylbenzene, octane, and xylene) gases.

Tandem GaInP/GaAs//Si(inactive) solar cells were manufactured by direct wafer bonding under vacuum. At this early stage, an inactive silicon substrate was used (i.e. n+ Si substrate instead of an active n-p Si junction). Bonded devices presented an S-shaped J-V curve with a kink close to Voc caused by a built-in potential barrier at the III-V//Si interface that reduces the fill factor and therefore the efficiency of the device by 7% compared to the stand-alone GaInP/GaAs tandem cells. Nevertheless, losses in Jsc and Voc caused by the bonding process, account for less than 10%. AlGaAs single junction cells, designed to be bonded on a silicon cell for low concentrator photovoltaics (LCPV), were also manufactured reaching an efficiency of 15.9% under one sun AM1.5G spectrum for a 2cm2 cell.

This article highlights some aspects associated with the fabrication of stacked nanowire metal oxide semiconductor field effect transistors (MOSFETs) and more precisely the active area conception. These novel architectures, with gate-all-around or independent gates (ΦFET), are promising solutions to improve electrostatic control with high on-current (Ion) and to reduce power consumption for sub-32-nm transistors. Their fabrication is highly complex regarding lithography and etching. For this study, stacked nanowires were achieved by using hybrid lithography (e-beam/deep ultraviolet) combined with anisotropic and isotropic etchings of a Si∕SiGe multilayer to form suspended silicon nanowires. Therefore, we needed high aspect ratio resist features in order to perform the anisotropic etch of the Si∕SiGe multilayer (thickness: 250nm). For this purpose, we compared two ways to pattern the sub-32-nm silicon stacked nanowires. On one hand, a resist trimming was performed on thick large critical dimension patterns...

We present a novel approach to pattern aggressive aspect ratio Si/Si1-xGex superlattices on Silicon On Insulator (SOI) wafers. This approach is based on the anisotropic etching of Si/SiGe superlattices with final dimensions down to 30nm, and the isotropic etching of the SiGe selectively to silicon. This isotropic etching was developed in a remote plasma chamber, and in-situ in an Inductive Coupled Plasma (ICP) reactor.

This work reports on the realization of the smallest Pirani gauge ever, based upon highly-doped silicon nanowires. This paper details the fabrication process and the characterization of the thermal properties of Si nanowires, such as thermal conductivity and thermal coefficient of resistivity for various working temperatures in the 300K-700K range. A dynamic transduction technique, based on the 3-omega measurement is described and the device performances (i.e. sensitivity and signal-to-noise ratio) are measured. With the tested devices a resolution below 5%/Hz1/2 is obtained in the 0.1mbar-1bar range.

A double-gate suspended silicon nanowire transistor (DGSSiNWT) is proposed for conduction-based chemical/biological sensing applications. The doping profile is uniform across the device without any junction. The suspended silicon nanowire (SiNW) provides a larger surface area that can be used to enhance the sensitivity. Two side gates, which work as the main gate and tuning gate, are separated from the SiNW by air gap and control the electrical conduction of the suspended structure. Using the tuning gate, we have optimized the operating point of device to achieve the highest sensitivity. The sensitivity, defined as the ratio of threshold voltage shift to tuning gate voltage variation, is observed to be up to 6.5. The estimated charge sensitivity of our devices is at least 20 times higher than the reported value for non-suspended SiNW transistors.

Measurements of the gauge factor of suspended, top-down silicon nanowires are presented. The nanowires are fabricated with a CMOS compatible process and with doping concentrations ranging from 2 × 10 20 down to 5 × 10 17 cm −3 . The extracted gauge factors are compared with results on identical non-suspended nanowires and with state-of-the-art results. An increase of the gauge factor after suspension is demonstrated. For the low doped nanowires a value of 235 is measured. Particular attention was paid throughout the experiments to distinguishing real resistance change due to strain modulation from resistance fluctuations due to charge trapping. Furthermore, a numerical model correlating surface charge density with the gauge factor is presented. Comparison of the simulations with experimental measurements shows the validity of this approach. These results contribute to a deeper understanding of the piezoresistive effect in Si nanowires. (Some figures in this article are in colour only in the electronic version)

For the first time, interface properties between high-k and Si or SiGe nanowires (NWs) have been experimentally investigated by adapting charge pumping technique and low-frequency noise measurement. It is found that the interface state density (D it ) of circular Si NWs is ∼3 times higher than that of rectangular ones with a deleterious impact on the low field mobility. The oxide trap density in SiGe NWs is otherwise ∼3.5 times higher than that of Si NWs which limits the mobility enhancement for this material.

Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF ( 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer from discrete width layout constraints and can benefit from specific options like independent gate operation.

Three- and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5times higher current density per layout surface is achieved compared to planar transistors with the same gate stack (HfO 2/TiN/Poly-Si). For the first time, several properties of this novel 3D architecture are explored: (i) HfO2/TiN gate stack is integrated, (ii) electrons and holes mobilities are measured on 150 beams matrices (3 levels) and compared to those of planar transistors (hi) a sub-100nm channel width is demonstrated and (iv) specific 3D integration challenges like zipping between nano-beams are discussed

We demonstrate the first implementation of a highly doped silicon nanowire electromechanical resonator that exploits the depletion charge modulation in a junctionless FET to transduce mechanical motion on-chip. The resonator, with a typical length between 1 and 2 µm, a total height of 44 nm and a total width of 65 nm, is coupled via two lateral 60 nm air-gap gate electrodes. A fundamental resonance frequency of 226 MHz is detected in the drain current. This device, showing full transistor functionality, is integrated in an SOI-CMOS platform using conventional 8″ inch wafer technology, which offers unique opportunities for ultra-low power sensing and signal processing platforms interfaced with CMOS on a single chip.

A Full 25GB/S silicon photonics platform is described in this paper, and new technological challenges that aim to improve this platform, such as multiple silicon levels, silicon nitride levels, edge coupling processing or integration of heterogeneous materials to enable tunable integrated lasers, are discussed.