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The “Quantum Dot Cellular Automata” or QCA is mainly used to design and simulate ‘3D’ structures for area-occupation, latency and total power reduction of any electronic circuit. At present, this “Nano-technology world” requires less-complex, small-size, high-frequency, fault-tolerant, low-power devices to increase the component-density in a single die. QCA designs are the well-known and optimum alternative of CMOS designs due to its above mentioned advantages. Further, reversible gates can also be formed based on QCA design. Reversible logic not only reduce the complexity of the design but also it can increase the information storage possibility by saving the power and energy. It is capable of reducing the leakage power (‘KTln2’ amount of dissipated energy for every bit can be ignored due to this logic). Cost of any device depends on the delay, power and occupied-area of the device which can be decreased by reversible multilayer (‘3D’) QCA structures. So, this proposed technique has an ability to provide the design for a cost-effective electronic device with good scalability and fault-tolerance. In the present work, we have simulated of an “Arithmetic and Logic Unit” in “QCA Designer” and “Xilinx” software. The first software is used due to the above advantages and here we apply reversible logic (reversible TSG gate with reversible AND-OR gate). This ALU is capable of performing one arithmetic (addition of two inputs) and three logical operations (AND, OR and XOR operations of two inputs) at a time. The TSG gate is used here as a full-adder with two input XOR operation and The reversible AND-OR gate is utilized for getting the AND result and OR result of two inputs. This design is also required a “4:1 MUX” which helps to select the operations properly. Schematic designs of proposed design with calculated values of delay and total power (for different room-temperature) are achieved in our work by using ‘Xilinx’ simulator. The used Verilog coding of our formed-design is also implemented in a “FPGA Board” (“Spartan 3E”) for hardware verification. Our presented circuitry can also continue its functionalities at high-temperature.

Now adays Very Large-Scale Integration (VLSI) circuits have good or great demand. Because CMOS circuit design having less power consumption. Transistors on the chip is doubled every two years, according to Moore’s law. So, it means transistor size is decreasing. This leads to increase the chip density and decrease the device size. The write and read depending on the bitline and bitline bar discharging and charging. When design the memory in below 16 nm uses Fin Field effect Transistor (FinFET) technology instead of CMOS (Complementary metal oxide semiconductor field effect transistor). Because to avoid short channel effect. Comparing leakage power, dynamic power and static power at 90 nm technology and write delay, read delay at both 90 nm and 45 nm technology in nine transistors (9 t), eight transistor (8 t) and six transistor (6 t) sram cell.

The manuscript presents the smart view of hybrid PV-wind power generation system by implementing the fuzzy logic at required stages for exploiting the maximum efficiency of the renewable system. The extracted power is processed through quadratic boost converters(QBC) and multi-level inverters for efficient maintenance of power quality and stability in the grid. The converters in the topology are provided with the fuzzy logic controllers to enhance the power extraction from the energy conversion system and performance of the overall system. The idea of this circuit topology is configured from various analysis of conventional systems by eliminating the unbalanced issues such as unbalanced voltages, power events, stability and quality issues. The proposed circuits are simulated on the Matlab software by providing the real time data such as power events in the grid. The results are contrasted with conventional topologies and discussed in the upcoming sections of the manuscript with the detailed simulation.

Conventional digital LLC Synchronous Rectifier (SR) control typically uses detection circuits to sense the drain-source voltage of SR MOSFET in low output voltage applications, or gives SR duty cycle only considering the switching frequency in the microcontroller. They are difficult to be applied to the applications of 700 V high voltage and 6.6 kW high power directly due to the high dv/dt and large SR duty cycle variations, which poses serious challenge for SRs control. A bidirectional impedance-based SR driving scheme is presented for high voltage SiC LLC converter. Based on the LLC equivalent impedance, mathematical models are built to calculate the SR on-time in the forward and reverse modes, which can be tuned timely when the switching frequency and load vary. Thus, both bidirectional LLC performance with high efficiency and high immunity to the switching noise can be achieved without adding auxiliary circuits. A prototype of 300-kHz 6.6-kW SiC bidirectional LLC charger was built. Compared to the conventional SR method, the LLC efficiencies improve 0.3% in the forward and reverse modes at full load by using the proposed SR driving scheme.

As interconnects dominate circuit performance in modern FPGAs, placement becomes a crucial stage for timing closure. Traditional FPGA placers seldom consider the timing constraints, and thus may lead to illegal routing solutions. In this paper, we present an incremental timing-driven placement flow for advanced FPGAs. First, a timing-based global placement strategy is designed to guide heterogeneous blocks to desired locations with satisfied timing constraints. Then, a timing-aware packing algorithm is developed to mitigate the design complexity while improving the timing results. Finally, we propose a critical path-based optimization method to generate optimized layout without timing violations. We evaluate our algorithm based on industrial circuits using an advanced FPGA device. The experimental results show that our placer achieves an 5.1% improvement in worst slack, and produces placements that require 16.7% less time to route when compared with the leading commercial tool Xilinx Vivado.

Multiplexing circuits in pixelated PET detectors are being studied with the goal of minimizing the degradation of detector performance. The purpose of this study was to develop a diode-based symmetric charge division (SCD) circuit with reducing the crosstalk caused by the leakage currents of adjacent channels connected in rows and columns. Four different SCD circuits (diode-based SCD with grounding path, diode-based SCD, resistor-based SCD with grounding path and resistor-based SCD) were constructed and their performance was evaluated and compared after being combined with a PET detector consisting of LYSO crystals optically coupled with SiPM. The diode-based SCD circuit with grounding path achieved a crosstalk ratio, energy resolution, coincidence timing resolution (CTR) and mean peak to valley ratio of 0.02, 14.3%, 0.5 ns and 27.9: 1, respectively; the diode-based SCD circuit achieved 0.03, 15.9%, 0.7 ns and 19.4: 1, respectively; the resistor-based SCD circuit with grounding path achieved 0.04, 14.5%, 0.9 ns and 19.4: 1, respectively; the resistorbased SCD circuit achieved 0.05, 17.8%, 1.8 ns and 17.7: 1, respectively. These results indicate that the proposed SCD has the potential to improve not only the crosstalk but also the energy linearity, energy resolution, and coincidence timing resolution characteristics in PET detectors.

Piezoelectric energy harvester (PEH) arrays are promising in many application scenarios. However, few interface circuits have been developed to manage the multiple AC inputs from PEHs. This paper proposes an extensible P-SSHI (parallel synchronized switch harvesting on inductor) array interface scheme to realize a multi-input conversion from PEH arrays. We develop a split-inductor-capacitor topology that can extract electrical energy from multiple PEHs. The proposed circuit topology effectively handles the inductor access conflict in the cases of PEHs with close, identical, and opposite vibration phases, insensitive to AC input phase changes. For demonstrating the capability of dealing with multiple AC inputs from PEHs and the enhancement effect on power output, we construct and test a self-powered three-channel array circuit with the passive peak detection function. Excited by sinusoidal vibrations, our circuit effectively avoids the energy return and efficiently achieves the power combination of the three PEHs. Compared with the classic full-bridge circuit, the proposed circuit helps increase the power output by 4.8 times. Also, to show the universality of the circuit, the circuits operation under various excitations is tested and analyzed.

This paper proposes a new modular active injection circuit (AIC) for solid-state circuit breaker (SSCB). The modular AIC is used to achieve soft-switching turn-off during DC current interruption. The proposed AIC presents following contributions: selectable resonant currents are obtained to obtain a reliable artificial zero crossing points in DC currents; current rating scalability is provided; passive components of the AIC are optimized using particle swarm optimization (PSO) algorithm and new proposed objective functions; an external wireless charger is developed to charge the injection capacitor of the AIC to provide voltage isolation, compactness, and flexibility in choosing the pre-charge voltage value on the injection capacitor; the proposed AIC needs no discharge circuits which simplifies the control and accelerates reclosing process. The proposed SSCB is simulated in a 6kV system in PSCAD/EMTDC in interrupting currents of normal and different scenarios . The designed SSCB can interrupt the DC currents up to 200A with the adaptive response time from 3.74s to 6.71s, faster response time in interrupting higher values of DC currents. The effectiveness of the proposed SSCB in practice is validated by experiments of a downsize 380V/20A prototype with only 2.8s response time and 99.91% efficiency.

The high-speed superiority of GaN power devices with silicon-based peripheral circuits is not yet fully leveraged, mainly due to the parasitic inductance of interconnections. In this work, we demonstrate a GaN-based gate driver with an over-current (OC) protection circuit and under-voltage lockout (UVLO) circuit on a p-GaN gate power HEMT platform. The gate driver features a rail-to-rail output voltage, suppressed gate ringing, and tunable driving speed, all of which are highly desired in high-efficiency and high-speed GaN power systems. To offer timely but reliable protections, over-current protection and UVLO circuit are designed with reference to the switching speed and the threshold voltage of GaN power device. The over-current protection is implemented with a separated sensing branch and blanking time controller and the response time to an over-current event is reduced to 10 ns after the blanking time. The UVLO circuit has a fixed hysteresis of 0.5 V and its threshold voltage is specially tailored for the GaN integrated circuits.

For certain field-effect transistors (FETs) in soft-switching operation, the large-signal behavior of their output capacitance ( Co ) has shown to deviate considerably from the datasheet values. This can have a significant effect on hard-switching losses if the value of output charge is also different for a given voltage. In addition, standard hard-switching tests are incapable of fully setting apart the contributions from Co , whereas existing methods tailored to characterize Co losses in soft-switching operations subject Co to a fundamentally different charge–discharge process, and hence, might not predict the correct behavior for hard switching. To address this, first, we analyze and establish the particular charge–discharge conditions that Co undergoes in hard-switching circuits by considering a half bridge at no-load conditions. We show that the channel of the switching device incurs a fixed energy loss during the turn- on process, which is separated into co-energy and stored energy components of the top (complementary) and bottom (switching) devices, respectively. Exploiting this, a new measurement technique is developed to obtain output-charge versus voltage curves of devices subjected to actual hard switching. The experimental results for commercial Si, SiC, and GaN devices indicate that the effective charge-capacity of Co for hard switching can considerably vary from the values based on datasheets or Sawyer–Tower circuit; this could greatly undermine efficiency and thermal optimizations in the design phase of power converters.

Reference point of applicability (RPA) is a predefined point in a distribution network that determines performance requirements for multi- distributed energy resource (DER) circuits compliant to international grid codes. As RPA response is often not directly controlled, it requires an aggregate response of multiple DER, which becomes a challenge in complex meshed network environment. This paper presents a multiagent-based distributed dynamic voltage support (DDVS) method for coordinated aggregate response of multiple DER units to support RPA voltage profile during and after fault-ride though in such networks. DDVS implements a multiagent based leader target tracking scheme with velocity matching and flock centering features to avoid uncoordinated current injections of cooperative DERs. The DDVS is an event-based approach based on the RPA requirements. Two-dimensional voltage support objective is handled: (i) coordinated positive sequence current injection for voltage magnitude boosting and (ii) coordinated negative sequence current injection for unbalance voltage mitigation. The results demonstrate that the proposed DDVS algorithm addresses emerging coordinated DVS requirement of DERs.

In vivo electronic monitoring systems for underwater applications are promising technologies for obtaining information about aquatic animals. State-of-the-art devices are constrained by limits on the number of integrated sensors, large dimensions and weight, and short device longevity. Here, we report the Labon-a-Fish: the world's first biotelemetry tag that combines edge computing with wireless sensing of in vivo physiology [electrocardiogram (ECG) and electromyogram (EMG)], behavior [activity level and tail beat frequency (TBF)], and ambient environment (temperature, pressure, and magnetic field). The Lab-on-a-Fish has a miniaturized form (dry weight: 2.4 g; wet weight: 0.8 g; and dimensions: 5.5 mm x 6.5 mm x 37 mm) for studying small animals. Engineering efforts spanning improvements in battery chemistry, electronic circuit efficiency, and power-saving algorithms extend the longevity of the device to as much as eight months. The designed piezoelectric transducer and its driving circuit enable underwater wireless communication of multiplexed digital sensor data over a distance up to 400 m. The Lab-on-a-Fish can also store the raw data using flash memory for use in locations that are challenging for acoustic communications or when more complex data postprocessing is needed. Long-term in vivo validation in three species-rainbow trout (Oncorhynchus mykiss), white sturgeon (Acipenser transmontanus), and walleye (Sander vitreus)-demonstrated the device's sensing potential for biological and environmental applications. DOE [DE-AC05-76RL01830] Published version This work was conducted at Pacific Northwest National Laboratory (PNNL), which is operated by Battelle for DOE under Contract DE-AC05-76RL01830. Fish care and use for the study were approved by Pacific Northwest National Laboratory's Institutional Animal Care and Use Committee (protocol No. 2019-02) following the 8th Edition Guide for the Care and Use of Laboratory Animals (NRC 2011). The authors acknowledge M. Myjak and R. Lundy for the PCB layout, A. Dao for the ECG algorithm, and R. Elsinghorst and A. Salalila for the manufacturing.

High-Voltage power Integrated Circuits (HVICs) are widely used to realize high-efficiency power conversions (e.g., AC/DC conversion), gate drivers for power devices and LED lighting, and so on. The Bipolar-CMOS-DMOS (BCD) process is proposed to fabricate devices with bipolar, CMOS, and DMOS modes, and thereby realize the single-chip integration of HVICs. The basic integrated technologies of HVICs include High-Voltage (HV) integrated device technology, HV interconnection technology, and isolation technology. The HV integrated device is the core of HVICs. The basic requirements of the HV integrated device are high breakdown voltage, low specific on-resistance, and process compatibility with low-voltage circuits. The REduced SURFace field (RESURF) technology and junction termination technology are developed to optimize the surface field of integration power devices and breakdown voltage. Furthermore, the ENhanced DIelectric layer Field (ENDIF) and REduced BULk Field (REBULF) technologies are proposed to optimize bulk fields. The double/triple RESURF technologies are further developed, and the superjunction concept is introduced to integrated power devices and to reduce the specific on-resistance. This work presents a comprehensive review of these technologies, including the innovation technologies of the authors' group, such as ENDIF and REBULF, substrate termination technology prospective integrated technologies and HVICs in wide band gap semiconductor materials are also discussed.

This paper proposes a method for generating RSFQ logic circuits utilizing special RSFQ gates in logic synthesis. It is suited for the standard technology mapping flow used in logic synthesis tools and enables generating RSFQ circuits utilizing confluence buffers (CBs) and resettable DFFs (RDFFs), to reduce the number of clocked gates by reduction of logic depth. A library of supergates, each consisting of several gates, is used to compose a resultant circuit in the technology mapping. In this paper, a library containing supergates including those special gates is generated and is utilized to design circuits with the gates. First, a generation of a supergate library is proposed to introduce CBs and RDFFs, which realize logic OR without clock pulses and a fused function of logic AND and NOT, respectively. The generated library contains supergates including the special gates and they are used to compose the resultant circuits with the special gates. A mapping approach is also proposed. It distinguishes non-clocked gates such as CBs and clocked gates. It takes the number of inserted DFFs for path balancing into account to reduce the number of clocked gates. The method was implemented into the state-of-the-art academic EDA tool, i.e., ABC, and was evaluated. Evaluation results show that the number of clocked gates is reduced by about 30% from the original ABC with path-balancing DFFs.

There is a clear trend in the aircraft industry to use more electrical systems in propulsion and electromechanical and electrohydraulic actuators to comply with environmental sustainability and to improve reliability and maintenance processes. The increase of electrical consumption requires an increase of the rated voltages to supply power to these so called More Electrical Aircraft (MEA). Unfortunately, this voltage rise, currently up to 540 Vdc, can lead to ionization processes within the electric wiring due to the lower air density at high altitudes. As a consequence, a degraded insulation can create extremely hazardous events in flight such as arcs between wires (serial) or between wires and fuselage (parallel). Serial arcs in DC bus circuits are specially dangerous for the aircraft operation, so its detection within fractions of seconds is required to ensure a reliable operation. However, during a sustained serial arc the rated current can be passing through air deceiving the protections and avoiding their tripping. In this work, it has been found that arcing introduces high frequency current pulses superimposed to the DC component that can be identified to detect the occurrence of an arc. The frequency components of these pulses depend on the line characteristics and can be detected with inductive sensors. This manuscript also designs and tests a light and inexpensive sensor for arc detection in aircraft applications.

This article demonstrates the potential of deep-subthreshold mixed-signal circuits in delivering medium-to-high performance to supply-constrained, energy-harvesting Internet of Things (IoT) sensing applications. This effort encapsulates the design and implementation of an ultra-low-voltage (ULV) 0.2-V open-loop VCO-based analog-to-digital converter (ADC). A replica VCO facilitates variation-aware VCO analog linearization. Analog phase-domain signal processing (APSP) techniques for beat-frequency extraction, phase-interpolation, and phase-folding relax constraints on both voltage-to-frequency analog circuitry and frequency-to-digital synchronous digital hardware. High-speed multi-phase frequency-to-digital converters (FDCs) and multi-rate digital back-end enable a sampling speed of 35 MS/s. The ADC prototype is implemented in 28-nm CMOS and achieves a peak SNDR of 64.4/59.9 dB, equivalent to an ENOB of 10.4/9.7 over 80-/160-kHz bandwidth (BW). The ADC core occupies an active area of 0.12 mm² and consumes 15.9 μ W, resulting in a Walden and Schreier FoM of, respectively, 73.3/61.5 fJ/c-s and 161.4/159.9 dB at the corresponding BW configurations. Measurements across multiple ICs and supply voltages consolidate the value of variation-aware deep-subthreshold open-loop ADCs.

Josephson junctions (JJs) with non-hysteretic I-V characteristic and high critical parameters are required for many applications; in particular, they are needed to create tunable THz range oscillators. We fabricated and studied shunted superconductor-insulator-superconductor (SIS) Nb-AlOx-Nb tunnel junctions with an area of about 1m2, estimated their parameters, and compared them with theoretical models. To assess the performance of shunted junctions in the terahertz range, their characteristics were studied under the influence of a high-frequency signal; the estimated value of the characteristic voltage for the shunted junction at a high frequency is about 1 mV. To improve the circuit parameters, a new type of the shunting based on application of NIS junctions was proposed, which reduces the influence of parasitic inductance, expands the frequency range of the generator, and decreases the size of the structure. The JJs with a new type of shunting have been fabricated and studied. The niobium integrated circuits intended for matching the superconducting oscillator and an SIS junction as a microwave detector were designed, fabricated, and tested. Such structures are required for studying the spectral characteristics and analyzing the operation of the oscillator. The developed circuits have demonstrated efficient operation at frequencies from 300 to 700 GHz; the experimental results are in good agreement with the simulated characteristics. The results obtained will be implemented for further development of the THz range oscillators.

Inductive power transfer (IPT) systems are appropriate for electric vehicles charging applications because of the advantages of safety and convenience. However, due to the considerable influence of pad misalignment, improving misalignment tolerance is important for IPT systems. Besides, constant current (CC) and constant voltage (CV) output characteristics are usually required for electric vehicles battery charging. Therefore, to fulfill both features, a hybrid IPT system implementing high misalignment tolerance with inherent CC-CV output is proposed for electric vehicles charging applications in this paper. Two coils connected reversely in series are applied in transmitter side while two coils respectively compensated by a capacitor and an inductor-capacitor-capacitor are applied in receiver side. Hence, without extra DC-DC converter or complicated control strategy and corresponding circuits, CC-CV output can be naturally achieved with high misalignment tolerance which obviously increase the system reliability. Besides, zero-voltage switching and zero phase angle condition can be easily achieved. A 1kW experimental prototype is built. The experimental results show that the fluctuations of the constant charging current and the constant charging voltage are less than 5% when the proposed system operates within the predetermined misalignment range.

Harnessing energy from the environment promotes the rapid development of micro-power generators and relevant power management modules of alternating current (AC) line-filtering to obtain a stabilized direct current (DC) output for storage and use. Micro-supercapacitors (MSCs) with miniaturized volume and high-frequency response are regarded as a critical component in filtering circuits for microscale power conversion. Here, we reported the fabrication of the wafer-sized planar MSCs (M-MSCs) based on 2D Ti3C2Tx MXene using a photolithography technique. The M-MSCs exhibited an areal capacitance of 153 μF cm−2 and a frequency characteristic (f0) of 5.6 kHz in aqueous electrolyte. Moreover, by employing suitable ionic liquid as electrolyte, the voltage window was expanded to 2 V and the f0 could be pushed to 6.6 kHz relying on the electrical double-layer mechanism and lower adsorption energy while maintaining quasi-rectangular cyclic voltammogram curves at 5000 V s−1. Furthermore, the integrated MSCs pack was constructed and exhibited excellent rectifying ability by filtering various high-frequency 5000 Hz AC signals with different waveforms into stable DC outputs. Such ultrahigh-rate and high-voltage M-MSCs module for kHz AC line-filtering would be potentially integrated with customizable electronics to realize on-chip rectifiers in high-density integrated circuit.

Power Supply Noise (PSN) in CPU cores or any integrated circuit (IC) chips is a problem of power line voltage degradation impelled due to the parasitic components (viz., resistance, capacitance and inductance) across the packaging. This lowers the operating frequency of the silicon chip during high volume manufacturing and thereby affects the overall performance. After numerous attempts to minimize the parasitic impacts of power delivery networks (PDN) in IC packages, researchers also started to look for circuital configurations that can curb down the coefficients of PSN (i.e., the instantaneous current i(t) and the current ramp di(t)dt during OFF to ON switching of packaged CPU/IC). Though variable frequency clock (VFC) has emerged as a potential solution, its design is found to be complex and power hungry. Hence, a novel and simple configuration of VFC embedded with leakage control transistor based clock gating (LCT-CG) is tendered in this article, where the pertaining circuits and integrated system have been designed using UMC 65nm CMOS with a supply of 1.1V. The performance of the design is tested on Master-Slave Flip-Flop (MSFF) and a few prominent benchmark circuits (viz., ISCAS’89 s27, s820, s832, s1196, s9234 and ITC’99 b02 and an IEEE 754 complaint single precision FPU) considering the PDN of existing CPU OLGA package. The system level validation of our proposed IC on A-Z80 CPU chip offers the average power and PSN to be mitigated by 30.06% and 42.63% against the conventional clocking.

Powerful electronic design automation tools have enabled the rapid development of electronic Integrated Circuits (ICs). Similar to electronic ICs, silicon photonics technology has sufficiently matured, and large-scale photonic circuits can now be implanted into a single chip. Design tools have also evolved from primary devices to complex photonic circuits. In this paper, we review the current state of photonic design automation in terms of device modeling methods and circuit simulation methodologies, and compare the photonics design flow with mature electronic design automation design flows. Key challenges and opportunities are also discussed.

A very high-light-load-efficiency, low-ripple-voltage pulse-frequency modulation (PFM) buck converter for IoT applications is presented in this paper. The PFM buck converter is widely used because of its higher light-load efficiency. However, it has a higher ripple voltage than its pulse-width modulation counterpart. Although the ripple voltage of a PFM buck converter can be reduced by increasing the output capacitance, we find that this leads to a decrease in the light-load efficiency due to increased controller loss. This problem is analyzed and verified by IC measurements in this work. The proposed PFM buck converter remarkably reduces the controller loss even at low ripple voltages by replacing the static comparator with a dynamic comparator, which provides a high voltage gain, fast evaluation speed, and low power consumption. In addition, to further reduce the controller loss, a dynamic shut-down control method, which selectively turns off control circuits, is used. The proposed PFM buck converter was fabricated with 0.35 m CMOS technology. The magnitude and variation of the output ripple voltage are 3 and 2 mV, respectively, and the light-load and peak efficiencies are 81.1% and 94.8%, respectively.

As the safety-critical applications (e.g. automotive and medical electronics) emerge, various techniques of radiation hardening by design (RHBD) are proposed to deal with soft errors. Among all RHBD techniques, Built-In Soft-Error Resilience (BISER) is the first one to apply the delayed latching to separate input signals on all flip-flops for error detection. However, the delay values induced by BISER extend the setup time of all flip-flops, and may fail to meet the timing specification of the design. For minimizing such delay impact on the setup time of each flip-flop, we propose the Automated Latching-Delay Assignment (ALDA) to transfer partial values to the CK-Q delay. Later, Time-Borrowable D-Flip-Flop (TBD-FF) as well as a modified design flow is also proposed to realize the delay assignment by ALDA and to complete the design hardening. Experiments show that ALDA together with TBD-FF effectively protects four benchmark circuits against soft errors, and optimally avoids the timing violations caused by the prior delayed-latching solutions.

To fully take the high-frequency advantage of gallium nitride (GaN) devices, this article presents a face-up integrated power module based on the printed circuit board (PCB) embedding technology to tackle the challenges caused by conventional discrete solutions. The proposed GaN module highly integrates a GaN-bare-dies-based full bridge, driving circuits, and decoupling capacitors, in which the advanced bismaleimide-triazine (BT) material is used as the packaging material and the copper-filled laser microvias are used for low-parasitic-inductance and high-thermal-conductivity interconnection. Careful electro-thermal co-design and optimization of power loop is conducted to make the trade-off between power loop inductance and thermal performance. The proposed full bridge power module achieves the lowest power loop inductance of about 0.305 nH in power modules with the same power level. The maximum thermal resistances from the embedded GaN bare dies to top and bottom surface are 3.39 /W and 0.42 /W, respectively. Benefitting from the ultra-low power loop parasitic inductances, the switching speed of GaN devices reaches to 57.5 V/ns, while the voltage overshoot is not higher than 5.35% of the DC bus voltage. The superior performance of the proposed integrated GaN module makes it a promising application prospect in high frequency high power density converters.

This paper proposes and implements a novel wireless power and drive transfer (WPDT) system using orthogonal bipolar couplers and separately excited modulation (SEM). Specifically, two bipolar coils are orthogonally integrated and naturally decoupled to form a compact magnetic coupler which will be utilized in the transmitter and receiver, respectively. The key is to employ the SEM to alternatively energize bipolar coils in the transmitter while self-driven circuits in the receiver can directly extract the drive information to control receiver-side switches. Consequently, the concurrent wireless power transfer (WPT) and wireless drive transfer (WDT) can be skillfully realized via the shared transfer channel at the single resonant frequency. Moreover, the proposed system can effortlessly achieve the wireless DC motor drive with the capability of bidirectional motion, or the wireless AC motor drive with the variable-voltage variable-frequency (VVVF) control. Besides driving the DC and AC motors, a 200-W prototype is constructed with the transmission efficiency of 89.5 % over the transfer distance of 100 mm for a resistive load of 40 . Both theoretical and experimental results are provided to validate the feasibility and flexibility of the proposed system.

In this paper, we present the investigation and design of high-performance transitions from coplanar waveguide (CPW) to the single-conductor, corrugated waveguides, namely terahertz spoof Surface Plasmon Polariton Waveguides (SSPP WGs). In contrast with the previous studies in the literature on the CPW to SSPP WG transitions, we propose a novel methodology to examine the relationship between the guided wavenumber and momentum matching, which is based on analytical calculations, together with the effects of the flaring grounds on the transition performance. This novel methodology allows us to design a low-loss transition circuit for any given CPW and SSPP dimensions, which is demonstrated for the first time in the literature. We verify the proposed methodology by the design, fabrication, and measurement of several transition circuits. The measurement results show that the insertion losses of the proposed transition circuits can be as low as -1.2, -1, and -2.4 dB at 0.25, 0.275, and 0.3 THz, respectively, which brings a significant improvement of 0.6 to 2.3 dB in 0.25-0.3 THz band, compared to the previously reported studies in the literature for the terahertz band.

In this article, we explore the design of energy-efficient intermittently powered systems (IPSs) using reconfigurable-ferroelectric transistors (R-FEFETs). Utilizing the dynamic tunability between volatile and nonvolatile modes of operation in R-FEFETs, we design nonvolatile flip-flops (NVFFs) and memory (NVM) suitable for IPS. We present two variants of R-FEFET-based NVFFs (RNVFFs): 1) with automatic backup and 2) with need-based backup. While the former offers high backup energy efficiency, the latter offers low normal operation energy. We also present an IPS-specific R-FEFET-based NVM (3T-R) with high energy efficiency compared with FEFET-based 2T NVM. Leveraging these nonvolatile circuits, we map the microcontroller unit (MCU) core registers of an IPS to RNVFFs and its on-chip memory to 3T-R. Subsequently, we analyze system-level implications of improving NVFFs and NVM individually by using R-FEFETs compared with existing FEFET-based designs. Our system-level simulations demonstrate that although we improve the register energy by 55%-67%, the total memory and system-level energy savings obtained from just improving the NVFFs (registers) in the microcontroller core are only 0.60%-5.78% and 0.31%-3.18%, respectively. However, improving the NVM by using 3T-R results in a much larger total memory and system-level energy savings in the range of 37%-40% and 20%-22%, respectively, in the context of a state-of-the-art IPS.

With the development of artificial intelligence research, the convolutional neural networks (CNN) triumphantly continue to conquer diverse visual tasks, with lots of technical and practical problems emerging. When the detection networks need to meet the high-speed processing requirement and the low power consumption constraint in edge computing, dedicated circuits and algorithm optimization are necessary. In this brief, we propose a non-maximum suppression (NMS) coprocessor that cooperated with a Vision Processor(VP) to speed up the detection. It contains a parallel process unit and dynamic memory management to accelerate NMS processing. Meanwhile, the software workflow provides a comprehensive method to convert the one-stage detection network to our processor in a post-training manner. The experimental results show that our co-design solution reaches 166 FPS to run a MobileNet-SSD, promising to deploy in edge-computing scenarios. Moreover, the detection accuracy on the Airbus dataset is 88.6%, favorable in practical applications.

This paper investigates the intelligent fault detection problem for a class of Takagi-Sugeno fuzzy Markov jump systems. The considered systems are modeled by a set of fuzzy rules and membership functions. With the help of deep learning technique, an intelligent fault detection method based on long short-term memory (LSTM) neural network with an attention mechanism is proposed. The improved LSTM model can accurately capture the fault features by making full use of previous information. Finally, the proposed approach is applied to the tunnel diode circuits and corresponding experiments are conducted to demonstrate its effectiveness, which achieves better performance in comparison with other conventional method for detection.

In this paper, a single-stage rectifier-less boost converter circuit (SSRBC) for piezoelectric energy harvesting from ambient vibration was proposed. The proposed rectifier-less circuit acted as a boost converter to extract energy from a piezoelectric device (PD). It combined the conventional boost, buck-boost methods using two split inductors and single filter capacitor. The proposed integrated circuit topology functioned in both positive and negative half cycles generated by the PD. In the proposed topology, inductors were invigorated by being enveloped with the current, which was produced by the PD through the switches. This facilitated active rectification of ultra-low AC (amplitude < 0.5 VP). Theoretical analysis, control strategies, simulation and experimental study, were presented. The proposed circuit was capable of converting a low amplitude AC voltage of 0.5 VP into 5.1 Vdc. The highest output power extracted by the proposed circuit was 281.1 µW, which outperformed existing circuits. It could potentially facilitate the advancement of vibration-based energy harvesting system for low power demand applications such as sensors, quartz watches and portable charging devices.

A high efficiency dual active bridge with coupled inductor (DABCI) for fuel cell vehicles is proposed in this paper and its operation principle is analyzed to reveal the optimal operation modes of this converter, which provides the basis for circuit parameters design. Compared with dual active bridge (DAB), the DABCI is more suitable for high voltage gain applications because its low voltage bridge works like interleaved boost circuit and it is easy to get high voltage gain by adjusting the duty cycle D. In order to reveal the best operation mode of the DABCI, an optimal current stress modulation strategy is proposed, which can realize zero voltage switching (ZVS) operation in wide load range for all switches. Furthermore, the input current ripple is suppressed by interleaving two boost circuits in low voltage bridge, which can extend the life span of fuel cell vehicles. In addition, advanced magnetic integration technology is adopted to improve the system power density. Finally, a 4kW rated prototype is made and experimental results are presented to verify the previous analysis.

A co-design dual-polarized patch antenna operating in dual compressed high-order modes and solar cells is proposed for green communication. The solar cell patch antenna is proposed for enhancing gain, wideband communication, and powering for wireless sensors. First, to enhance the gain of the antenna and the ability of optical energy harvesting, the antenna resonates at the high-order compressed modes. Secondly, the solar cell works in the direct-current loop, and the antenna works in the radio-frequency loop, separately. A differentially coupling-fed structure and two rows of vias are employed, which are beneficial to bandwidth and prevent the two loops from interfering with each other. Intrinsic isolation is achieved without any extra circuits. Next, a parametric study is exhibited as the antenna optimization guideline. By measuring the prototype experimentally performances, the design approach and the principle are validated. The measured results photoelectric experiment confirmed the ability of the solar cell antenna to convert luminous energy into electrical energy. In the desired operating band (4.8-5 GHz), the radiation performance of the proposed dual-polarized solar cell antenna is higher than 8.6 dBi for 5G communication.

In the present era of data-driven architectures like 5G, Internet of things (IoT), Artificial Intelligence (AI), etc, the requirement of fast-switchable memory storage is more than ever. Oxide resistive switches are considered to be a primary choice in the non-volatile memory design. In this work, we have engineered the conventional metal-insulator-metal (MIM) structure of an oxide memristor (Ag/ZnO/ITO) by inducing an additional oxide layer La0.7Sr0.3MnO3 (LSMO) at the interface between the active layer (ZnO) and Ag electrode. The presence of LSMO acts as a reservoir for the oxygen vacancies, easing the conducting filament formation process in ZnO, thereby enabling drastic improvement of the switching performance and offering reliable endurance over multiple switching cycles. First-principles-based calculations suggested the role of Oxygen vacancies in controlling the electronic state of ZnO and formation of vacancies in the resistive switching process, which is in agreement with the experimental observation. The current results pave ways for improving the switching performance of resistive memory circuits through simple structural engineering incorporation, which lies at the heart of oxide electronics.

Quantum-dot Cellular Automata is a nanotechnology based circuit design technology to design efficient circuits. Serial-Parallel Multiplier is an efficient hardware circuit used in different applications ranging from simple arithmetic circuits, filters to complex cryptographic systems. In this work, an architecture that can be used for realizing Serial Parallel Multiplier in QCA is discussed. Based on that architecture, an efficient four bit serial-parallel multiplier is implemented in Quantum-dot cellular automata. The proposed multiplier is also realized using efficient shift registers and adders. Parallel and serial shift registers are introduced in the circuit to store the inputs and outputs to increase the reliability of the circuit. The proposed work is first of its kind to implement serial-parallel multiplier with shift registers to store input and output in QCA. The proposed multiplier without shift registers is efficient and at least 66% faster compared to existing designs. The 4-bit multiplier with shift registers has 2271 cells covering an area of 7.74 μm2 with 25.25 clock cycle latency. To showcase, the scalability a serial adder is also realized using Universal, Scalable and Efficient Clocking scheme.

This article proposed a codesign of a power amplifier (PA) and a bandpass filter (BPF) named filtering PA using metal integrated and substrate integrated suspended line (MI-SISL). Two BPFs are designed separately as the input and output matching network to realize bandpass filtering response and good harmonic suppression at the same time. The BPF matching circuits are implemented using SISL-based dual-layer interdigital capacitors for miniaturization and SISL-based dual-layer spiral inductors for low loss. The suspended substrate of the PA is patterned according to the shape of the PA core circuit, which helps to reduce the circuit loss and improve efficiency. Moreover, the metal integrated technique is also proposed by replacing the top and bottom substrates of the conventional SISL structure with metal plates with good electrical and thermal conductivities for heat dissipation. A filtering PA on the MI-SISL platform at 0.9 GHz is fabricated and measured as a demonstration case. An ultrasmall size of 0.12 $λ_{{g}}$ x 0.07 $λ_{{g}}$ is achieved, where $λ_{{g}}$ is the guide wavelength at 0.9 GHz. To the best of our knowledge, this is the most compact filtering PA on the board level to date. In addition, a harmonic suppression level of 40 dBc in up to the fifth-harmonic frequency is achieved.

in the traditional applications such as machine field excitation where power transfer from stationary to rotary side is needed, contact sliprings are often adopted. However, this kind of sliprings are easy to wear and need frequent maintenance. In a contactless power transfer system, mechanical sliprings can be removed which will largely increase the system reliability. In this paper, a contactless power transfer device using wireless power transfer (WPT) is designed. Its performances are simulated by finite element method. To increase the system power rate and efficiency, the device is operated under high frequency. Thus, high frequency ferromagnetic materials and Litz wires are used. Moreover, compensation circuits are added to improve the coupling between the primary and secondary sides. At last, a prototype is built and tested. From the experimental results, the functions and performances of the device are well verified.

A wide-range frequency detector (FD) is presented for baud-rate clock and data recovery (CDR) circuits. It achieves a wide frequency capture range, a short lock time, and a low power. By using this FD, a referenceless quarter-rate CDR circuit with a one-tap decision feedback equalizer is fabricated in 40-nm CMOS technology. The active area of this CDR circuit is 0.0999mm2 and its power is 44mW while the data rate is 16.8Gbps. The calculated energy efficiency of this CDR circuit is 2.62pJ/b.

In this article, an interleaved high-voltage gain dc–dc converter is proposed for use with photovoltaic (PV) systems. By integrating two three-winding coupled inductors (CIs) with switched capacitor cells, the voltage gain is further extended. Through passive diode-capacitor clamp circuits, the energy stored in the leakage inductances is absorbed; additionally, the voltage stress of the power switches is clamped to a value far lower than the output voltage, which enables designers to select switches with low-voltage ratings. Due to the interleaved structure of the proposed converter, the input current has a small ripple, which leads to the increased lifespan of the PV panels. In addition, the current stress on the components is reduced. Thanks to the leakage inductances of the CIs, the zero-current switching condition is intrinsically provided for the diodes; accordingly, the adverse impact of the diodes’ reverse-recovery is alleviated. The operating principles, steady-state analyses, and design considerations of the proposed converter are presented in this article. A comparison with other similar converters is carried out to verify the merits of the proposed converter. Finally, the theoretical analyses are confirmed through the experimental results of a 400-W prototype with an output voltage of 400 V.

Polymer memristors with good flexibility are promising electronic devices for edge computing paradigms in wearable electronics. However, most reported works present nonvolatile devices, which are suitable for applications in resistive random-access memory or artificial synapse. The volatile devices, which are indispensable in artificial neuron circuits, have rarely been reported, as the resistive switching property of organic devices is usually unstable in volatile devices. Moreover, most reported works use polymers in a way that is not compatible with traditional memristor fabrication technology, which limits the further applications of polymer memristors to large-scale neuromorphic circuits. In this letter, an Ag/Nafion/Au threshold switching memristor was fabricated via electrohydrodynamic printing technology and employed as a core of a leaky integrate and fire neuron circuit. The threshold switching memristor shows excel device size, good endurance, good device-to-device and cycle-to-cycle uniformity, flexibility, and stability at high temperatures. The combination of electrohydrodynamic printing technology and polymer memristor is promising in fast memristor production and largescale edge-computation network circuits.

The single-gate (SG) and dual-gate (DG) organic thin-film transistors (OTFTs) performances have been analyzed by using high dielectric constant material. The dielectric and gate electrode material variation does the comparative study on SG (bottom-gate bottom-contact configuration) and DG-based OTFTs. Variation in thickness of the dielectric layer (step size 2) and channel length (step size 10) results in a deviation in the performance parameters like threshold voltage, mobility, ION/IOFF current ratio, subthreshold swing, trans-conductance, etc. Such variations in the performance of OTFT have been observed by using 2D numerical devices ATLAS simulator. Subsequently, it is analyzed that reduction in channel length from 50 µm to 10 µm leads to an increase in the drain current from −9.88 × 10−10 A to −5.8 × 10−9 A (in case of DG-OTFT) and from −9.84 × 10−11 A to −5.3 × 10−9 A (in case of SG-OTFT). Similarly, the reduction in dielectric layer thickness from 10 nm to 2 nm leads to an increase in the drive current/the current ratio from 3.9 × 1012 to 1.3 × 1013 (in case of SG-OTFT) and from 1.8 × 105 to 1.5 × 106 (in case of DG-OTFT). So achieving a better result, we switch to DG- OTFT compared to SG-OTFT, which would be helpful in various future applications like chemical sensors, circuits, RFIDs, etc.

This study describes a new method to compensate bias heating effects for microbolometer readout circuits using a finely adjustable CMOS resistance as a reference. The proposed self calibrated cooler-less structure dynamically modifies CMOS resistance during integration time. This compensation structure also includes a feedback loop, which forces the oscillators to work in the linear region. The proposed self calibration circuit is designed and simulated using a 65-nm process node, and achieves 40 mK NETD (Noise Equivalent Temperature Difference) value for one percent resistance non-uniformity of pixel resistance values across one row. The layout area of this circuit occupies approximately one third of the layout area used by classical readout circuits. The circuit dissipates one third of power compared with classical microbolometer readout approaches.

A new GaN Nano-Schottky diode rectifier is introduced with capacitance per unit gate width of 381 fF/mm, and series resistance is 0.45 Ω ·mm leading to transition frequency ( $f_{{T}})$ of 928 GHz. The associated forward current is 1.8 A/mm with breakdown voltage of 30 V. The new device was modeled and an on-wafer voltage doubler rectenna circuit was designed and fabricated on GaN/SiC wafers. A W-band small and large signal characterization was performed to highlight the integrated rectenna performance. An RF-dc efficiency of 61.5% was measured at 95 GHz with associated input power density of 3.61 kW/m². The latter represents a 15.7% increase in efficiency over the state-of-the-art W-band rectenna circuit. The input power handling has also increased by a factor of 1.5 and 9.5 from reported GaAs and CMOS-based rectenna circuits at 94 GHz. The result highlights key improvements in the rectenna metrics for wireless power beaming demonstrations of the future.

In this article, a novel and simple design procedure for multibit chipless radio frequency identification (RFID) tags is introduced, which is based on the characteristics of dual-mode loop resonator (DMLR) and open-loop resonator (OLR). By removing a small patch element from the symmetry axis of the DMLR, a simple geometrical transition to an OLR to obtain different frequency codes can be achieved. Since the DMLR and OLR provide dual- and single-resonant frequencies, three different frequency codes can be observed using one resonator. Thus, 3 ${N}$ codes can be performed by coupling N resonators to input/output (I/O) ports. Even-odd mode analysis over the coupling mechanism of a single resonator is provided to characterize the frequency responses of the proposed resonators. To prove the proposed approach, two multiresonator circuits having four resonators were fabricated and tested in a good agreement. In the test environment, two horn antennas and a vector network analyzer have been utilized as transmitter and reader. Next, in order to achieve size reduction, meandered resonators are utilized instead of conventional DMLR and OLR. Based on these resonators, two RFID tags, including wideband monopole antennas integrated into the seven-resonator circuits on the same board, were also fabricated and tested.

Ultra-low quiescent current ( $I_{Q}$ ) low-dropout regulator is the only solution for compact size Internet of Things (IoT) electronic devices. This paper presents an ultra-low $I_{Q}$ low dropout regulator, including low $I_{Q}$ error amplifier (EA) compensated by the adaptive current control (ACC), low leakage feedback network, low $I_{Q}$ current comparator, analog transient enhancement (ATE), and digital transient enhancement (DTE). The chip was fabricated in a standard 0.5 μm CMOS process. Measurement results show the current peak efficiency of the LDO is as high as 99.99%. Besides, owing to ATE and DTE circuits, when the load current changes from 1mA to 50mA with a 10 ns edge time, the measured undershoot and overshoot voltages are 75 mV and 50 mV, respectively, with the recovery time ( $T_{R}$ ) of 60 ns and 80 ns, respectively, where the best 0.003 ps FoM is achieved.