Search

Zhonglin Wang,1 Jian Yu,2 Shangrui Rao,2 Zhe Lin,2 Zhongliang Pan,2 Xian Shen1 1Department of General Surgery, The Second Affiliated Hospital of Wenzhou Medical University, Wenzhou, 325000, Zhejiang, People’s Republic of China; 2Department of General Surgery, Wenzhou Central Hospital, Wenzhou, 325000, Zhejiang, People’s Republic of ChinaCorrespondence: Xian ShenDepartment of General Surgery, The Second Affiliated Hospital of Wenzhou Medical University, Wenzhou, 325000, Zhejiang, People’s Republic of ChinaTel/Fax +86-577-88002609Email 13968888872@163.comBackground: Increased surgical technology has led broad acceptance endoscopic thyroidectomy and its application in the treatment of thyroid diseases, including thyroid carcinoma. Although the incidence of complications and mortality of thyroid surgery has been significantly reduced, serious complications still occur from time to time. The purpose of this retrospective study is to identify the factors that influence the complications of endoscopic thyroidectomy.Methods: This study was carried out between January 2012 and December 2019, where a total of 630 patients undergoing endoscopic thyroidectomy via the total areola approach were retrospectively evaluated to identify the key influencing factors of complications.Results: The study established that the common complications included recurrent laryngeal nerve injury (3.33%), superior laryngeal nerve injury (2.54%), hypocalcemia (8.57%), and the incidence of complications was acceptable. Both univariate and multivariate analysis showed that thyroid carcinoma (P = 0.041), operation time lasting more than 150 minutes (P = 0.034) and operation before 2017 (P = 0.001) were risk factors of recurrent laryngeal nerve injury. We established that operation after 2017 (P < 0.005) was the only protective factor of superior laryngeal nerve injury. Thyroid carcinoma (P=0.04), operation mode (P=0.001), and surgery before 2017 (P< 0.001) are risk factors for parathyroid injury. Among the clinical groups, operation before 2017 was an independent risk factor for all complications.Conclusion: For thyroid specialists, after the early learning curve, with the continuous improvement of endoscopic operation technology, high-definition equipment and more sophisticated operation equipment can be used in clinical practice, which can prevent and reduce the occurrence of complications.Keywords: thyroidectomy, endoscopy, surgical complications, influencing factors

Based on transmission line modeling, a new technology of collaborative applying the ultralow-k dielectric and the high-k dielectric materials in coupled multilayer graphene nanoribbon (MLGNR) interconnects (i.e., case 4) to reduce propagation delay and to expand 3-dB bandwidth of the conventional pristine (undoped) MLGNR interconnects is proposed in this paper. By using the decoupling technique and ABCD parameter matrix approach, the transfer function of the equivalent circuit model for coupled MLGNR interconnects is derived to obtain step response, propagation delay, transfer gain and 3-dB bandwidth under in-phase and out-of-phase crosstalk modes at global level of 7.5 nm technology node, which is based on the defined four cases. The results show that the maximum reduction of propagation delay between the proposed new technology (case 4) and the conventional MLGNR interconnects (case 1) can reach 15.911 ns at out-of-phase crosstalk mode for an interconnect length of 4000 μm. The corresponding 3-dB bandwidth for them can be expanded over 2.978 times in the same length as the former. It is demonstrated that the proposed case 4 can obviously reduce the propagation delay and enhance the transfer gain and 3-dB bandwidth compared with the conventional case 1. Moreover, it is found that the coupled MLGNR interconnect under in-phase mode outperform that under out-of-phase mode in terms of propagation delay, transfer gain and 3-dB bandwidth at the same condition. In addition, it is manifested that the victim line of two-line coupled MLGNR interconnects have lesser propagation delay, higher transfer gain and larger 3-dB bandwidth, as compared to three-line coupled MLGNR interconnects at the same case. The proposed new technology in this paper would be beneficial to improve the performance of MLGNR interconnects and to provide the guidelines for the design of next generation on-chip MLGNR interconnect system.

Purpose. The purpose of this study was to find the clinical significance and methods of using CN in endoscopic treatment for PTC. Materials and Methods. A total of 108 cases were randomly enrolled and divided into two groups, with 50 cases in the CN injection group who were injected with CN and 58 cases in the control group with no CN injection. All cases were analyzed with the size of carcinoma, the number of lymph node, and parathyroid gland injury. Results. All operations were successfully completed. The lymph node dissection number was 274 for the control group and 322 (the rate of black stained was 87%) for the CN injection group. The average number of lymph nodes in the CN injection group was 6.44 ± 2.08, which was significantly higher than that in the control group (4.72 ± 1.89). The control group had a relatively higher incidence of incidental parathyroidectomy, compared to the CN injection group (27.6% in the control group vs. 12% in the CN injection group, P = 0.045 ). However, the incidence of hypoparathyroidism failed to show the significant difference between the two groups. Conclusion. Using CN in endoscopic PTC surgery could increase the detection rate of lymph nodes and reduce the injury of parathyroid glands to a certain extent.

This paper proposes a noniterative analytical thermal model for 3-D integrated circuits (3-D-ICs) based on the solution of the governing energy equations using Green’s function, separation of variables, and superposition methods. The model is applicable to both transient and steady-state heat conduction problems. Any finite number of dies equally sized in plane can be taken into consideration in current analysis. In addition, the analytical solution presented here is very general, so that it takes into account the different interface boundary conditions between the dies. Importantly, the thermal properties (i.e., $k$ , $\rho $ , $c$ ) and thickness of different dies can be different, and the spatial and time-varying volumetric heat generation can be applied in each of the different dies. The results compared with the finite-element simulations show that the temperature fields predicted by the proposed model can offer an accurate and efficient solution to compute the temperature fields in the representative 3-D-ICs, with a maximum deviation between the two being around 2.0% in the transient heat conduction. In the steady-state case, the maximum deviation can reach even less than 1.0%.

Electrocardiography(ECG) signal suffers from noise interference during the recording and transmission, which would result in morphological structure distortion and affects proper diagnosis of diseases related to the cardiac system. For the purpose of filtering the noise to obtain the clean signal, in this paper, the recently developed complete ensemble empirical mode decomposition with adaptive noise algorithm(CEEMDAN) with morphological structure of ECG signal is proposed for ECG enhancement. The experimental results indicate that the proposed CEEMDAN based method could be capable of removing both high frequency interference and low frequency baseline wander, which provides competitive performances compared to other signal de-nosing approaches explored in this paper.

The multilayer graphene nanoribbons (MLGNR) by inserting the high-k dielectric material between adjacent graphene nanoribbons (GNR) layers to reduce propagation delay and to expand bandwidth of the conventional pristine (undoped) MLGNR interconnects is presented in this paper. An equivalent distributed circuit model of the proposed MLGNR interconnect with high-k dielectric materials is established to derive the analytical expressions of propagation delay, step response, transfer gain and 3-dB bandwidth for 7.5 nm technology node at global level. The numerical simulation results show that the maximum reduction of propagation delay between the proposed MLGNR by inserting SrTiO3 dielectric material and the pristine MLGNR can reach 12.746 ns for an interconnect length of 4000 μm. The corresponding 3-dB bandwidth for them can be expanded over 4 times for the interconnect length. It is demonstrated that the proposed MLGNR by inserting the high-k dielectric material can greatly reduce propagation delay and enhance transfer gain and 3-dB bandwidth compared with the conventional pristine MLGNR interconnects. Moreover, it is found that the results obtained by the proposed model have close agreement with Synopsys HSPICE simulation and the maximum relative error for them is less than 5%, and the average efficiency of CPU runtime is improved 95% by using the proposed model, as compared to HSPICE simulation. The proposed design method has many potential applications in improving performance of MLGNR interconnect and providing guidelines for the next generation on-chip interconnect system.

Background With the development of surgical technics, endoscopic thyroid surgery has been gradually accepted and utilized in thyroid disease treatment, including thyroid carcinoma. This study aimed to evaluate the learning curve for endoscopic hemithyroidectomy (EHT) with ipsilateral central neck dissection (CND) and investigate how many cases must be performed before a surgeon becomes competent and proficient in this approach. Methods Ninety-nine consecutive patients who underwent EHT with ipsilateral CND for papillary thyroid microcarcinoma by a single surgeon between June 2015 and October 2017 were analyzed. Multidimensional cumulative summation (CUSUM) analysis was performed to evaluate the learning curve. Results The CUSUM graph showed the learning curve ascended in the first 31 cases and declined in the following cases. The number of lymph nodes removed in phase 2 (the following 68 cases) was significantly more than that in phase 1 (the first 31 cases) (5.06 ± 1.44 vs. 4.19 ± 1.51, P = 0.001). The operation time in phase 2 was shorter than that in phase 1 (123.38 ± 12.71 min vs. 132.90 ± 13.95 min, P = 0.008) and the rate of accidental removal of parathyroid gland decreased from 35.5% in phase 1 to 16.2% in phase 2 (P = 0.040). There was a declining trend but no significant difference in the rate of postoperative complications (9.7% in phase 2 vs. 4.4% in phase 1, P = 0.309). Conclusion EHT with ipsilateral CND performed by surgeons was mastered after 31 cases, and the safety and feasibility of this endoscopic approach can also be demonstrated.

The GaAs material is a major semiconductor material, and it has high electron transfer rate and direct transition energy band structure. The devices and integrated circuits fabricated on the GaAs substrates have a lot of advantages such as high speed information processing. Small perturbations in the manufacturing of GaAs materials can lead to defects. The defects in the GaAs materials can degrade the performance of materials. A new method is presented in this paper for detecting the micro-defects in GaAs materials by using time resolved emissions. In this method, the micro-defects in GaAs materials are detected by making use of the photon emission features of micro-defects. The strength of the emitted photons from the micro-defects is increased by applying the electric current or the periodic pulse signals to GaAs materials. The single-photon detector is used to detect the photon emissions of the micro-defects. The time resolved photon emissions and single-photon detection are used to record and compare the amounts of the emitted photons that come from the given regions of the normal GaAs materials and the defective GaAs materials. A lot of experimental results show that the micro-defects in the GaAs materials can be detected by using the method proposed in this paper.

The binary decision diagrams (BDDs) can give canonical representation to Boolean functions; they have wide applications in the design and verification of digital systems. A new method based on cultural algorithms for minimizing the size of BDDs is presented in this paper. First of all, the coding of an individual representing a BDDs is given, and the fitness of an individual is defined. The population is built by a set of the individuals. Second, the implementations based on cultural algorithms for the minimization of BDDs, i.e., the designs of belief space and population space, and the designs of acceptance function and influence function, are given in detail. Third, the fault detection approaches using BDDs for digital circuits are studied. A new method for the detection of crosstalk faults by using BDDs is presented. Experimental results on a number of digital circuits show that the BDDs with small number of nodes can be obtained by the method proposed in this paper, and all test vectors of a fault in digital circuits can also be produced.

The crosstalk effect among the signal lines is produced because of the increase of density of integrated circuits; it is primarily the capacitive coupling and inductance coupling of signal lines, where a signal transition on a signal line can take effects on the adjacent signal lines. The delay faults induced by crosstalk effects is generated when the aggressor line and victim line have simultaneous or near simultaneous transitions. In this paper, a new test generation method for the delay faults induced by crosstalk effects is presented; the method can produce the test vectors by using the circuit structure and Boolean satisfiability. First of all, the conjunctive normal form (CNF) formula of a circuit is constructed. Second, the crosstalk faults that consist of the aggressor and victim lines are activated, the path that can propagate the delay to the primary outputs are selected, and the Boolean satisfiability operations are used to get the value assignments of signal lines in the circuits. The experimental results for a lot of benchmark circuits show that the test vectors of the delay faults induced by crosstalk effects can be generated effectively by using the method proposed in this paper.

The continual increase of the integrated circuit complexity results in the more signal lines close to each other; this may produce the coupling effects among the signal lines. One of main coupling effects is crosstalk effect. In this paper, a new method is presented for the test pattern generation for the multiple victim lines of crosstalk effects; the method makes use of the binary decision diagrams (BDD). First, the BDDs of the circuit under test are built to express the circuit structure and logic values related to crosstalk effects. Second, the test patterns of crosstalk faults are produced by performing the operations on these BDDs and searching for the input assignments of the decision diagrams. The experimental results show that the method proposed in this paper can produce the test patterns of crosstalk effects in shorter time.

Several types of defects in the LED chips may be caused from the manufacturing environments, these defects can result in the degradations of the parameters and performance. Hence it is very necessary to perform the defect detection of LED chips for effectively enhancing the production quality. In this paper, a new method is presented for the defect inspection of LED chips. The method makes use of both the support vector machine and the image segmentation based on level set to acquire the features of LED chip images and to carry out the inspection. First of all, the support vector machine is used to perform the clustering for the original LED images, the margin of region clustering is used as the initial contour curve. Secondly, the segmentation using level set is implemented for the LED images. The features of LED images are extracted, then the database of features is constructed. Therefore, an automatic inspection system for LED chip is built, the system can recognize the defective LED chips. The experimental results demonstrate that the presented method in this paper is able to detect the defects in the LED chips accurately.

With the continuous advancement of semiconductor technology, the interconnects crosstalk has had a great influence on the performances of VLSI circuits.To date, most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling (VMS) scheme while the current-mode signaling (CMS) scheme is rarely analyzed.First of all, an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes.The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model.Secondly, the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique andABCD parameter matrix approach at local level, intermediate level and global level, respectively.Moreover, the experimental results show that the CMS interconnects have lesser noise peak, noise width and noise amplitude than the VMS interconnects in the same cases, and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits.It is found that the results obtained by ABCD parameter matrix approach are in good accordance with the simulation results of the advanced design system.

The binary decision diagram is a graph representation of Boolean functions, it also can efficiently represent the logic functionality of digital circuits. The number of nodes in binary decision diagram depends on the variable ordering. A new method is presented in this paper for the variable ordering and the minimization of binary decision diagram, the method is based on adaptive hierarchy genetic algorithm, which uses two populations with hierarchy to evolve in parallel, and the operation parameters in the evolution procedure are adjusted dynamically as the changes of environment. The individual representation scheme corresponding to binary decision diagram, and the implementation steps of adaptive hierarchy genetic algorithm, are given in detail. Besides, the application of the method for the test generation of digital circuits is given. A lot of experimental results show that the binary decision diagrams with smaller number of nodes can be obtained by the method proposed in this paper, and the test vectors of faults in digital circuits can also be produced.

The digital circuits should be tested thoroughly in order to find the faults due to manufacturing defects or errors. The generation of test vectors is one of main task of circuit test, the test vectors can be obtained by finding appropriate logic assignments to the circuit primary inputs such that the given faults can be detected. The power consumption during test process may be higher than that power consumption during normal operations of circuits. Therefore it is necessary to design the test vectors with low power. In this paper, a new method is proposed for the generation of test vectors with low power. The method makes use of the co-evolution algorithms, first of all, the coding of an individual corresponding to the circuit primary inputs is given, secondly, the populations consisting of a lot of individuals are built, the better individuals corresponding to the test vectors with low power are obtained by applying the evolutionary operations to the populations. A lot of experimental results show that the test generation method in this paper is able to produce the test vectors with lower power, and can obtain higher fault coverage.

The network-on-chip(NoC) is one of important aspects in digital circuit design, it attracted more and more attentions in electronic engineering. The NoC has been proposed as a promising solution to act as communication architecture because the number of cores in the systems-on-chip(SoC) is increased greatly. A lot of work needs to be carried out in the design of NoC, such as the determinations of the NoC communication backbone and communication protocols, the allocation of cores to various available nodes in NoC topology, that is the core mapping. The task of core mapping is to determine the topological placement of cores onto the nodes in NoC topology structure, and choose a path for each pair of IP cores. In this paper, the NoC structure with mesh topology is considered, a new approach is presented for the core mapping of network-on-chip by using Tabu search algorithm. The evolution operations in genetic algorithms are added to the Tabu search process to enhance the computation efficiency. The experimental results show that the time being needed to obtain the core mapping scheme by the approach proposed in this paper is lower than conventional genetic algorithm.

The scaling of circuit design technology to ultra deep submicron has increased the sensitivity of circuit technology to various noise mechanisms such as power supply noise and leakage current noise, etc. The propagation of noise can happen through various modes like the power supply and the substrate to a sensitive receptor. The power supply noise can reduce the actual voltage level reaching a device, results in the loss of signal integrity. The type of noise may also cause the degradation of switching speed, timing faults, or logic functional failures. In this paper, a new approach is presented for the test generation of power supply noise in digital circuits, the approach is based on the binary decision diagrams. The test vectors of power supply noise are generated by building and operating several binary decision diagrams, such as the binary decision diagrams respectively corresponding to the normal circuits and the circuits whose signal lines have been assigned special logic values. A lot of experimental results show that if there are test vectors for the power supply noise in a circuit, then the test vectors can be generated by the approach proposed in this paper.

In the design procedure of system on chip (SoC), it is needed to make use of hardware-software co-design technique owing to the great complexity of SoC. One of main steps in hardware-software co-design is how to carry out the partitioning of a system into hardware and software components. The efficient approaches for hardware-software partitioning can achieve good system performance, which is superior to the techniques that use software only or use hardware only. In this paper, a method based on neural networks is presented for the hardware-software partitioning of system on chip. The discrete Hopfield neural networks corresponding to the problem of hardware-software partitioning is built, the states of neural neurons are able to represent whether the required components or functionalities are to be implemented in hardware or software. An algorithm based on the principle of simulated annealing is designed, which can be used to compute the minimal energy states of neural networks, therefore the optimal partitioning schemes are obtained. The experimental results show that the hardware-software partitioning method proposed in this paper can obtain the near optimal partitioning for a lot of example circuits.

The network-on-chip (NoC) is a scalable and flexible infrastructure for the design of system on chip (SoC). The performance of data communication in a network-on-chip depends heavily on the topology structure and routing algorithm. The communication bandwidth requirements of a network-on-chip can be reduced when the irregular topology structures are designed for specific application systems. In this paper, a new method is presented for designing the structure of network-on-chip, the method is based on the evolutionary strategies. First of all, the initial topology structures are produced by the random approach. Secondly, the topology structures are coded as individuals, and the topology structure corresponding to an individual is strongly connected, that is there is a path between every pair of nodes. The feasible topology structures can be obtained by applying the operations in the evolutionary strategies to the population being consisting of individuals. The experimental results demonstrate that the method proposed in this paper can obtain the feasible topology structure of network-on-chip.

In the current circuit design technology, due to increasing device density and operation speed, crosstalk effects are induced between circuit elements. A new method for the detection of crosstalk faults in digital circuits is presented in this paper, the method is based on both the energy function model of digital circuits and the chaotic ant colony algorithms. First of all, the energy function models of basic gate circuits are constructed, then the energy function corresponding to a digital circuit is built. The energy function of a circuit is the summation of all energy functions of the gates in the circuit. The test vectors of crosstalk delay faults in the circuit are produced by computing the minimal energy states of energy functions. Secondly, a chaotic ant colony algorithm is designed to compute the minimal energy states. Experimental results show the method proposed in this paper is able to produce the test vectors of crosstalk delay faults if there are the test vectors for the faults, therefore the high fault coverage can be obtained by the proposed method.

The integrated circuit (IC) design technology has made the chip density continue to increase. The high performance chips have a high sensitivity to the slightest defects in manufacturing procedure, therefore the defect detection is needed in order to ensure the performances of chip and semiconductor device. For the defects on a wafer, a detection method using image segmentation is presented in this paper. The method performs the segmentation of wafer image by selecting the threshold values. The optimal thresholds are computed by the technique based on cultural algorithm. The designs of population space, the belief space, and communication protocol in the cultural algorithm, are given in detail. An integration of genetic algorithm and simulated annealing is used to produce the new individuals in the population space. The experimental results show that the defect detection method proposed in this paper can obtain the features of defects effectively, the better image about the defect on a wafer can be obtained if the differential chart of the original image and the intact image of wafer is computed in advance.

Binary decision diagram can be used to give canonical representation to logic functions and manipulate functions by simple and efficient graph algorithms. In this paper, the generation of test pattern based on binary decision diagrams is studied for stuck-at faults and crosstalk faults in digital circuits. The binary decision diagrams corresponding to the normal circuit and faulty circuit are built, respectively. A binary decision diagram is built by the XOR operation of the two binary decision diagrams, each input assignment that leads to the leaf node labeled 1 is a test vector of the faults. Besides, the binary decision diagram is very sensitive to the variable ordering, the variable ordering used can have a significant impact on the number of nodes. A chaotic genetic algorithms is presented in this paper, which is used to find a variable ordering that minimizes the size of a binary decision diagram to get the test vectors of the faults in digital circuits in the shortest possible test time. Experimental results obtained with a lot of digital circuits show that all the test vectors of a fault can be obtained using the method presented in this paper.

Test scheduling is an important task for the test of a system on chip, and it determines the assignment of cores to the test access mechanism such that the overall test time is minimized. A new test scheduling approach based on cultural algorithms for system on chip is presented in this paper. First of all, the optimization model of test scheduling is given, the model uses the information such as the bits width of the test access mechanism and the scale of test sets of cores, the crosstalk fault test sets of core interconnect lines is also discussed. Secondly, a method based on cultural algorithms is proposed to solve the optimization model of test scheduling. The ant colony algorithm is used in the population space, and the conventional genetic algorithm is used in the belief space. The feasible solutions of test scheduling are represented by individuals, a lot of individuals form the populations. The optimal test scheduling scheme is obtained by the evolution of the populations. Experimental results on a lot of benchmark circuits show that the proposed approach in this paper can solve the problem of test scheduling effectively.

The increase in signal switching speed and density of digital circuits leads to the crosstalk faults of interconnection lines, which may cause undesirable effects and even logic errors in the circuit. A new test method based on the neural network models of digital circuits is proposed in this paper for the crosstalk faults in digital circuits. The neural network corresponding to digital circuit is built, and the test vectors of the crosstalk faults are generated by computing the minimum energy states of neural network. A chaotic evolutionary strategies algorithm is designed to compute the minimum energy states. The algorithm combines the features of chaotic systems and evolutionary strategies, and takes full advantages of the stochastic properties and global search ability of the two techniques. Experimental results on a lot of benchmark circuits show that the approach proposed in this paper can be used to get the test vectors of the crosstalk faults if the crosstalk faults are testable.

By using the first-principles methods based on density function theory (DFT), the effects of boron(B)/phosphorus(P) pair co-doping on the electrical properties of zigzag single-walled carbon nanotubes (SWNTs) have been investigated. We calculated the formation energies and band structures of (6, 0) metallic and (8, 0) semiconducting SWNTs with different B/P co-doping sites and concentrations. The obtained formation energies suggest that the B/P co-doping configurations are energetically stable structures and the B and P tend to form a B–P bond. It shows that an energy gap is opened by B/P co-doping in (6, 0) metallic SWNTs and the metallic carbon nanotubes are converted into semiconductors. For the (8, 0) semiconducting SWNTs, B/P co-doping influences the band structure, but it does not change the attributes essentially and the SWNTs are still semiconducting. It was also found that the band structures depend on the doping concentration as well as the doping site of B/P pair.