Generation of Test Vectors with Low Power by Co-evolution Algorithm for Digital Circuits

The digital circuits should be tested thoroughly in order to find the faults due to manufacturing defects or errors. The generation of test vectors is one of main task of circuit test, the test vectors can be obtained by finding appropriate logic assignments to the circuit primary inputs such that the given faults can be detected. The power consumption during test process may be higher than that power consumption during normal operations of circuits. Therefore it is necessary to design the test vectors with low power. In this paper, a new method is proposed for the generation of test vectors with low power. The method makes use of the co-evolution algorithms, first of all, the coding of an individual corresponding to the circuit primary inputs is given, secondly, the populations consisting of a lot of individuals are built, the better individuals corresponding to the test vectors with low power are obtained by applying the evolutionary operations to the populations. A lot of experimental results show that the test generation method in this paper is able to produce the test vectors with lower power, and can obtain higher fault coverage.