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IEEE 802.11ax is the standard for the new generation WiFi networks. In this paper, we formulate the problem of joint access point (AP) placement and power-channel-resource unit assignment for 802.11ax-based dense WiFi. The objective is to minimize the number of APs. Two quality-of-service (QoS) requirements are to be fulfilled: (1) a two-tier throughput requirement which ensures that the throughput of each station is good enough, and (2) a fault tolerance requirement which ensures that the stations could still use WiFi even when some APs fail. We prove that this problem is NP-hard. To tackle this problem, we first develop an analytic model to derive the throughput of each station under the OFDMA mechanism and a widely used interference model. We then design a heuristic algorithm to find high-quality solutions with polynomial time complexity. Simulation results under both fixed-user and mobile-user cases show that: (1) when the area is small (50 x 50 m2), our algorithm gives the optimal solutions; when the area is larger (80 x 60 m2), our algorithm can reduce the number of APs by 34.9-87.7% as compared to the Random and Greedy algorithms. (2) Our algorithm can always get feasible solutions that fulfill the QoS requirements.

Mobile Cloud Computing enables the migration of services to the edge of the Internet. Therefore, high-performance computing clusters are widely deployed to improve computational capabilities of such environments. However, they are prone to failures and need analytical models to predict their behaviour in order to deliver desired quality-of-service and quality-of-experience to mobile users. This paper proposes a 3D analytical model and a problem-solving approach for sustainability evaluation of high-performance computing clusters. The proposed solution uses an iterative approach to obtain performance measurements to overcome the state space explosion problem. The availability modelling and evaluation of master and computing nodes are performed using a multi-repairman approach. The optimum number of repairmen is also obtained to get realistic results and reduce the overall cost. The proposed model is validated using discrete event simulation. The analytical approach is much faster and in good agreement with the simulations. The analysis focuses on mean queue length, throughput, and mean response time outputs. The maximum differences between analytical and simulation results in the considered scenarios of up to a billion states are less than1.149%,3.82%, and3.76%respectively. These differences are well within the5%of confidence interval of the simulation and the proposed model.

Today's blockchains suffer from low throughput and high latency, which impedes their widespread adoption of more complex applications like smart contracts. In this paper, we propose a novel paradigm for smart contract execution. It distinguishes between consensus nodes and execution nodes: different groups of execution nodes can execute transactions in parallel; meanwhile, consensus nodes can asynchronously order transactions and process execution results. Moreover, it requires no coordination among execution nodes and can effectively prevent livelocks. We show two ways of applying this paradigm to blockchains. First, we show how we can make Ethereum support parallel and asynchronous contract execution \emph{without hard-forks}. Then, we propose a new public, permissionless blockchain. Our benchmark shows that, with a fast consensus layer, it can provide a high throughput even for complex transactions like Cryptokitties gene mixing. It can also protect simple transactions from being starved by complex transactions.

Due to the huge success and rapid development of convolutional neural networks (CNNs), there is a growing demand for hardware accelerators that accommodate a variety of CNNs to improve their inference latency and energy efficiency, in order to enable their deployment in real-time applications. Among popular platforms, field-programmable gate arrays (FPGAs) have been widely adopted for CNN acceleration because of their capability to provide superior energy efficiency and low-latency processing, while supporting high reconfigurability, making them favorable for accelerating rapidly evolving CNN algorithms. This article introduces a highly customized streaming hardware architecture that focuses on improving the compute efficiency for streaming applications by providing full-stack acceleration of CNNs on FPGAs. The proposed accelerator maps most computational functions, that is, convolutional and deconvolutional layers into a singular unified module, and implements the residual and concatenative connections between the functions with high efficiency, to support the inference of mainstream CNNs with different topologies. This architecture is further optimized through exploiting different levels of parallelism, layer fusion, and fully leveraging digital signal processing blocks (DSPs). The proposed accelerator has been implemented on Intel's Arria 10 GX1150 hardware and evaluated with a wide range of benchmark models. The results demonstrate a high performance of over 1.3 TOP/s of throughput, up to 97% of compute [multiply-accumulate (MAC)] efficiency, which outperforms the state-of-the-art FPGA accelerators.

Background: High throughput screening systems are automated labs for the analysis of many biochemical substances in the drug discovery and virus detection process. This paper was motivated by the problem of automating testing for viruses and new drugs using high throughput screening systems. The emergence of severe acute respiratory syndrome coronavirus 2 (SARSCoV- 2) at the turn of 2019-2020 presented extraordinary challenges to public health. Existing approaches to test viruses and new drugs do not use optimal schedules and are not efficient. Objective: The scheduling of activities performed by various resources in a high throughput screening system affects its efficiency, throughput, operations cost, and quality of screening. This study aims to minimize the total screening (flow) time and ensure the consistency and quality of screening. Methods: This paper develops innovative mixed-integer models that efficiently compute optimal schedules for screening many microplates to identify new drugs and determine whether samples contain viruses. The methods integrate job-shop and cyclic scheduling. Experiments are conducted for a drug discovery process of screening an enzymatic assay and a general process of detecting SARS-CoV-2. Results: The method developed in this article can reduce screening time by as much as 91.67%. Conclusion: The optimal schedules for high throughput screening systems greatly reduce the total flow time and can be computed efficiently to help discover new drugs and detect viruses.

Due to recent explosion of data volume and velocity, a new array of lightweight key-value stores have emerged to serve as alternatives to traditional databases. The majority of these storage engines, however, sacrifice their read performance in order to cope with write throughput by avoiding random disk access when writing a record in favor of fast sequential accesses. But, the boundary between sequential vs. random access is becoming blurred with the advent of solid-state drives (SSDs). In this work, we propose our new key-value store, LogStore, optimized for hybrid storage architectures. Additionally, introduce a novel cost-based data staging model based on log-structured storage, in which recent changes are first stored on SSDs, and pushed to HDD as it ages, while minimizing the read/write amplification for merging data from SSDs and HDDs. Furthermore, we take a holistic approach in improving both the read and write performance by dynamically optimizing the data layout, such as deferring and reversing the compaction process, and developing an access strategy to leverage the strengths of each available medium in our storage hierarchy. Lastly, in our extensive evaluation, we demonstrate that LogStore achieves up to 6x improvement in throughput/latency over LevelDB, a state-of-the-art key-value store

A spectrum of emerging applications including edge artificial intelligence advocate the precompute-and-search scheme with embedded small-size content addressable memory (CAM) for its hardware efficiency instead of repetitive arithmetic operations. However, integration of the CAM macros that are conventionally implemented with full custom analog circuits renders design-space exploration and optimization to be difficult at system level. As an alternative, a complete design flow for compiling ternary CAM on chip using foundry-supplied digital standard cells is introduced in this paper. Based on novel CAM architecture and logic design, we leverage guided placement and routing with mainstream EDA tools for exploiting the inherent structure regularity of CAM-cell arrays in layout. An analytical model is also presented which allows us for a systematic investigation on the energy reduction by adapting our design to various pre-search structures. Validated on a post-layout 32W64 ternary CAM in 28nm, our parallel-matching scheme performs at 2.6GHz with 0.42fJ/bit/search, and the (8-bit) pre-search scheme achieves 0.19fJ/bit/search at 1.1GHz, both under the 0.9V supply voltage. In addition to flexibility for tradeoffs between the search throughput and energy, our all-digital CAM design enables voltage scaling aggressively down to 0.45V with a minimum energy consumption of 0.06fJ/bit/search at 50MHz.

This paper proposes an efficient structure-aware storage system, called GraphSO. It can be integrated into existing out-of-core graph processing systems to promote the execution efficiency of concurrent jobs with lower I/O overhead. Specifically, it logically divides the partitions of existing graph processing systems into a series of small same-sized chunks. At runtime, these small chunks with active vertices are judiciously loaded by GraphSO to construct new logical partitions for existing graph processing systems to handle, where the most-frequently-used chunks are preferentially loaded to construct the logical partitions and the other ones are delayed to wait to be required by more jobs. In this way, it can effectively spare the cost of loading the graph data associated with the inactive vertices with low repartitioning overhead and can also enable the loaded graph data to be fully shared by concurrent jobs. Moreover, GraphSO also designs a buffering strategy to efficiently cache the most-frequently-used chunks in the main memory to further minimize the I/O traffic by avoiding repeated load of them. Experimental results show that GraphSO improves the throughput of GridGraph, GraphChi, X-Stream, DynamicShards, LUMOS, Graphene, and Wonderland by 1.4-3.5, 2.1-4.3, 1.9-4.1, 1.9-2.9, 1.5-3.1, 1.3-1.5, and 1.3-2.7 times after integrating with them, respectively.

Leveraging cloud computing services to improve the flexibility and scalability of the IT services delivered to end-users is becoming increasingly important. However, organizations using cloud computing services face many challenges: decreased visibility into the performance of services being delivered to their end-users. Organizations using cloud computing services need to have visibility not only into the performance of applications that have moved to the cloud, but also into the different computing resources on which these applications depend. The monitoring system monitors the running state of virtual machines, response time and throughput. By analysing this data, you can identify the causes of service delays. During the operation of the monitoring system, virtual machines are suspended, a service delay occurs in order to avoid this delay. Therefore in this paper, a cloud computing model is proposed that takes into account the time spent for monitoring, calculations and probabilities of delay and waiting time are made, blocking probabilities are also put to account and results are shown in diagrams and the effects are discussed.

Nowadays, the improvement of the data acquisition capability of the IIoT (Industrial Internet-of-Things) systems has brought about higher data throughput. Users can deploy industrial big data analysis applications on cloud platforms in a pay-as-you-go way to deal with the unstable data generation and data analysis workloads in the IIoT scenario. To procure stable and flexible computing resources, as a traditional pay-as-you-go cloud instance procurement option, on-demand instances are widely used, but their expensive prices also significantly increase users’ cost burden. To reduce the data analysis cost, in this paper, we establish a per-job cost-effective framework adopting spot instances, on-demand instances, and cloud storage for industrial big data analysis applications. In our framework, we take advantage of spot instances, which are computing instances provided at low prices under a pay-as-you-go model, to achieve cost savings. However, using spot instances carries the risk of being interrupted. Therefore, we propose to use a checkpointing mechanism to back up intermediate results to cloud storage to reduce the potential loss caused by spot instance interruptions. Considering the time-sensitivity of industrial big data analysis applications, we use on-demand instances as alternative computing resources after spot instance interruptions to ensure that users’ jobs can be completed without high time latencies. Evaluation results show that our framework can achieve cost savings as well as minimize time latencies for users’ jobs.

Phase Change Memory (PCM) can directly connect persistent memory to main memory bus, while it achieves high read throughput and low standby power, the critical concerns are its poor write performance and limited durability. A naturally in-spired design is the hybrid memory architecture that fuses DRAM and PCM, so as to exploit the positive aspects of both types of memory. Unfortunately, existing solutions are seriously challenged by the limited main memory size, which is the primary bottleneck of in-memory computing. In this paper, we introduce a novel Content Aware Hybrid DRAM-PCM memory system framework—CAHRAM, which exploits deduplication to improve line sharing with high memory efficiency. It reduces write traffic to hybrid memory by removing unnecessary duplicate line writes, thereby further enhancing the write endurance of PCM. And it also substantially extends available free memory space by coalescing redundant lines in hybrid memory. We also design a reference-based page migration technique to minimize the access overheads caused by the performance gap between DRAM and PCM. Compared with the state-of-the-art in a hybrid memory simulator, our experiment results show that CAHRAM can achieve the highest I/O performance and the longest PCM lifetime with the competitive efficiencies in space and energy.

Real-time in situ image analytics impose stringent latency requirements on intelligent neural network inference operations. While conventional software-based implementations on the graphic processing unit (GPU)-accelerated platforms are flexible and have achieved very high inference throughput, they are not suitable for latency-sensitive applications where real-time feedback is needed. Here, we demonstrate that high-performance reconfigurable computing platforms based on field-programmable gate array (FPGA) processing can successfully bridge the gap between low-level hardware processing and high-level intelligent image analytics algorithm deployment within a unified system. The proposed design performs inference operations on a stream of individual images as they are produced and has a deeply pipelined hardware design that allows all layers of a quantized convolutional neural network (QCNN) to compute concurrently with partial image inputs. Using the case of label-free classification of human peripheral blood mononuclear cell (PBMC) subtypes as a proof-of-concept illustration, our system achieves an ultralow classification latency of 34.2 [Formula: see text] with over 95% end-to-end accuracy by using a QCNN, while the cells are imaged at throughput exceeding 29 200 cells/s. Our QCNN design is modular and is readily adaptable to other QCNNs with different latency and resource requirements.

We consider a multichannel random access system in which each user accesses a single channel at each time slot to communicate with an access point (AP). Users arrive to the system at random and be activated for a certain period of time slots and then disappear from the system. Under such dynamic network environment, we propose a distributed multichannel access protocol based on multi-agent reinforcement learning (RL) to improve both throughput and fairness between active users. Unlike the previous approaches adjusting channel access probabilities at each time slot, the proposed RL algorithm deterministically selects a set of channel access policies for several consecutive time slots. To effectively reduce the complexity of the proposed RL algorithm, we adopt a branching dueling Q-network architecture and propose an efficient training methodology for producing proper Q-values over time-varying user sets. We perform extensive simulations on realistic traffic environments and demonstrate that the proposed online learning improves both throughput and fairness compared to the conventional RL approaches and centralized scheduling policies., 20 pages, 12 figures

This paper considers a WP-MEC system consisting of multiple base stations (BSs) and mobile devices (MDs), where the MDs offload tasks to the BSs for computational resources and the BSs charge the MDs using wireless power transfer (WPT). In practice, each BS and MD are equipped with a task buffer with limited size and a battery with limited capacity. First, we develop a WP-MEC system with task and energy queuing dynamics to study long-term system performance under time-varying fading channels and stochastic task and energy arrivals. Second, we propose a dynamic throughput maximum (DTM) algorithm based on perturbed Lyapunov optimization to maximize the system throughput under task and energy queue stability constraints, by optimizing the allocation of communication, computation, and energy resources. For DTM, we characterize a throughput-backlog trade-off of [O}(1/V), O(V)] to indicate that the system throughput goes up as the queue backlog increases. However, as V goes large, the system throughput can be pushed arbitrarily close to the optimum at the cost of linearly increasing queue backlog. To reduce the cost, we further develop an improved dynamic throughput maximum (IDTM) algorithm, and verify that the IDTM algorithm can achieve a trade-off of ${[O(1/V), O((\log(V))^2)]}$ between the system throughput and the queue backlog.

This paper investigates intelligent reflecting surface (IRS) assisted wireless powered Internet of Things (IoT) networks. Specifically, multiple IoT devices first collect energy radiated from a power station (PS), then each device uses its harvested energy to support data transmission to an access point (AP) via frequency division multiple access (FDMA). In addition, an IRS aims to improve wireless energy transfer (WET) and wireless information transfer (WIT) capabilities using passive reflection beamformers. The system sum throughput, as a performance metric, is maximized evaluate the overall performance of the considered model, which is subject to the constraints of IRS phase shifts, transmission time scheduling, and bandwidth allocation. This problem is not convex with respect to multiple coupled variables, and cannot be directly solved. To circumvent this non-convexity, the transmission time scheduling and the bandwidth allocation are optimally designed in closed-form by the Lagrange dual method and the Karush-Kuhn-Tucker (KKT) conditions. Moreover, an alternating optimization (AO) algorithm is used to optimally design the IRS’s phase shifts during the WET and WIT phases in an alternating fashion. Specifically, we propose element-wise block coordinate decent (EBCD) and complex circle manifold (CCM) algorithms to iteratively derive the optimal phase shifts in closed-form. We also characterize the convergence behaviour of the proposed algorithms. Finally, numerical results are presented to validate the performance of the proposed scheme, where the benefits of the IRS are highlighted in terms of sum throughput, transmission time scheduling, and energy harvesting, compared with the benchmark schemes.

Future CPU-manycore heterogeneous systems can provide high peak throughput by integrating thousands of simple, independent, energy-efficient cores in a single die. However, there are two key challenges to translating this high peak throughput into improved end-to-end workload performance: (1) manycore co-processors rely on simple hardware putting significant demands on the software programmer; and (2) manycore co-processors use in-order cores that struggle to tolerate long memory latencies. To address the manycore programmability challenge, this paper presents a dense and sparse tensor processing framework based on PyTorch that enables domain experts to easily accelerate off-the-shelf workloads on CPUmanycore heterogeneous systems. To address the manycore memory latency challenge, we use our extended PyTorch framework to explore the potential for decoupled access/execute (DAE) software and hardware mechanisms. More specifically, we propose two software-only techniques, naive-software DAE and systolic-software DAE, along with a lightweight hardware access accelerator to further improve area-normalized throughput. We evaluate our techniques using a combination of PyTorch operator microbenchmarking and real-world PyTorch workloads running on a detailed register-transfer-level model of a 128-core manycore architecture. Our evaluation on three real-world dense and sparse tensor workloads suggest these workloads can achieve approximately 2-6× performance improvement when scaled to a future 2,000-core CPU-manycore heterogeneous system compared to an 18-core out-of-order CPU baseline, while potentially achieving higher area-normalized throughput and improved energyefficiency compared to general-purpose graphics processing units.

Drug metabolite identification is a bottleneck of drug metabolism studies due to the need for time-consuming chromatographic separation and structural confirmation. Ion mobility-mass spectrometry (IM-MS), on the other hand, separates analytes on a rapid (millisecond) time scale and enables the measurement of collision cross section (CCS), a unique physical property related to an ion's gas-phase size and shape, which can be used as an additional parameter for identification of unknowns. A current limitation to the application of IM-MS to the identification of drug metabolites is the lack of reference CCS values. In this work, we assembled a large-scale database of drug and drug metabolite CCS values using high-throughput in vitro drug metabolite generation and a rapid IM-MS analysis with automated data processing. Subsequently, we used this database to train a machine learning-based CCS prediction model, employing a combination of conventional 2D molecular descriptors and novel 3D descriptors, achieving high prediction accuracies (0.8-2.2% median relative error on test set data). The inclusion of 3D information in the prediction model enables the prediction of different CCS values for different protomers, conformers, and positional isomers, which is not possible using conventional 2D descriptors. The prediction models, dmCCS, are available at https://CCSbase.net/dmccs_predictions.

Fluorescence laser-scanning microscopy (LSM) is experiencing a revolution thanks to the introduction of new asynchronous read-out single-photon (SP) array detectors. These detectors give access to an entirely new set of single-photon information typically lost in conventional fluorescence LSM, thus triggering a new imaging/spectroscopy paradigm – the so-called singlephoton LSM (SP-LSM). The revolution’s outcomes are, from one side, the blooming of new SP-LSM techniques and tailored SP array detectors; from the other side, the need for data acquisition (DAQ) systems effectively supporting such innovations. In particular, there is a growing need for DAQ systems capable of handling the high throughput and high temporal resolution information generated by the single-photon detectors. To fill this gap, we developed an open-source multi-channel time tagging module (TTM) based on a field-programmable-gate array (FPGA), that can temporally tag single-photon events – with 30 ps precision – and synchronisation events – with 4 ns precision. Furthermore, being an open-access project, the TTM can be upgraded, modified, and customized by the microscopy-makers. We connected the TTM to a fluorescence LSM equipped with a single-photon avalanche diode (SPAD) bidimensional array detector, and we implemented fluorescence lifetime image scanning microscopy (FLISM) and, for the first time, fluorescence lifetime fluctuation spectroscopy (FLFS). We expect that our BrigthEyes-TTM will support the microscopy community to spread SP-LSM in many life science labs.

Diffraction-unlimited single-molecule techniques like STORM and (F)PALM enable three-dimensional (3D) fluorescence imaging at tens of nanometer resolution and are invaluable to investigate sub-cellular organization. The multitude of camera frames required to reconstruct a super-resolved image limits the typical throughput of these techniques to tens of cells per day, rendering these methods incompatible with large-scale cell biological or clinical application. STORM acquisition rates can be increased by over an order of magnitude, however the data volumes of about 40 TB a day and concomitant analysis burdens exceed the capacity of existing workflows. Here we present an integrated platform which transforms SMLM from a trick-pony technique into a work horse for cell biology. We leverage our developments in microscopy-specific data compression, distributed storage, and distributed analysis to automatically perform real-time localization analysis, which enable SMLM at throughputs of 10,000 cells a day. We implemented these advances in a fully-integrated environment that supports a highly-flexible architecture for distributed analysis, enabling quickly- and graphically-reconfigurable analyses to be automatically initiated from the microscope during acquisition, remotely executed, and even feedback and queue new acquisition tasks on the microscope. We demonstrate the utility of this framework by imaging hundreds of cells per well in multi-well sample formats. Our platform, the PYthon-Microscopy Environment (PYME), is easily configurable for hardware control on custom microscopes, and includes a plugin framework so users can readily extend all components of their imaging, visualization, and analysis pipeline. PYME is cross-platform, open source, and efficiently puts high-caliber visualization and analysis tools into the hands of both microscope developers and users.

This paper considers an Ultra-Dense Heterogeneous Network (UDHN) consisting of cache-enabled Unmanned Aerial Vehicles (UAVs) and Internet of things Mobile Devices (IMDs) receiving their requested contents via the Power Domain Non-Orthogonal Multiple Access (PD-NOMA) protocol. Employing the Fast Global K-Means (FGKM) algorithm, IMDs are partitioned into several clusters connecting to either other IMDs or UAV belonging to the same cluster in the presence of untrusted users, known as non-legitimate eavesdroppers. It is assumed that users located in the cluster edge area communicate with multiple UAVs to obtain their requested contents. The main goal for such a network is to jointly optimize the number of UAVs, their 3D placements, and the cache placement probability of contents stored in UAVs and IMDs by maximizing the secure cache throughput. Toward this goal, we prove that the objective function is non-concave. Therefore, we decompose the optimization problem into multiple subproblems. We first employ the FGKM algorithm to optimally determine the number of employed UAVs and their horizontal placements. Then, the UAVs’ altitudes are optimized by employing the Interior-Point Method (IPM), while the convex approximation for the objective function and its constraints are substituted. Then, we optimize the secure cache throughput of IMDs by proposing a caching placement strategy for contents stored in UAVs and IMDs via Device to Device (D2D) and UAV to Device (U2D) links, given illegal eavesdroppers’ presence. Then, we propose an iterative algorithm to achieve the near-optimal solution for the cache throughput of IMDs. Different from existing works, the closed-form expressions for the achievable secrecy rate and the successful probability of D2D communications and U2D transmissions, as well as the secure cache throughput are derived. Finally, simulation results are presented to validate the proposed caching placement strategy. It is shown that the proposed scheme outperforms the conventional Most Popular caching (MPC) strategy substantially.

As deep learning applications often encounter accuracy degradation due to the distorted inputs from a variety of environmental conditions, training with personal data has become essential for the edge devices. Hence, training on edge by supporting a trainable deep learning accelerator has been actively studied. Nevertheless, previous research does not consider the fundamental datapath for training and the importance of retaining the high performance for inference tasks. In this work, we propose NeuroFlix, a deep neural network training accelerator supporting heterogeneous data-type of floating- and fixed-point for input operands. From two perspectives: 1)separate precision decision for each input data, 2)maintenance of high performance on inference, we configure the data with low-bit fixed-point of activation/weight and floating-point based error gradient securing up to half-precision. A novel MAC architecture is designed to compute low/high-precision modes for the different input combinations. By substituting a high-cost floating-point based addition to brick-level separate accumulations, we realize both area-efficient architecture and high throughput for low-precision computation. Consequently, NeuroFlix outperforms the previous architectures of state-of-the-art configurations proving its high efficiency in both training and inference. By also comparing with the off-the-shelf bfloat16-based accelerator, it achieves 1.2/2.0 of speedup/energy-efficiency at training and further enhancement of 3.6/4.5 at inference.

The disruptive blockchain technology is expected to have broad applications in many areas due to its advantages of transparency, fault tolerance, and decentralization, but the open nature of blockchain also introduces severe privacy issues. Since anyone can deduce private information about relevant accounts, different privacy-preserving techniques have been proposed for cryptocurrencies under the UTXO model, e.g., Zerocash and Monero. However, it is more challenging to protect privacy for account-model blockchains (e.g., Ethereum) since it is much easier to link accounts in the account-model blockchain. In this paper, we propose BlockMaze, an efficient privacy-preserving account-model blockchain based on zk-SNARKs. Along with dual-balance model, BlockMaze achieves strong privacy guaran- tees by hiding account balances, transaction amounts, and linkage between senders and recipients. Moreover, we provide formal security definitions and prove the security of BlockMaze. Finally, we implement a prototype of BlockMaze based on Libsnark and Go-Ethereum, and conduct extensive experiments to evaluate its performance. Our 300-node experiment results show that BlockMaze has high efficiency in computation and transaction throughput: one transaction verification takes about 14.2 ms, one transaction generation takes 6.1-18.6 seconds, and its throughput is around 20 TPS.

Convolutional neural networks (CNNs) play a key role in deep learning applications. However, the large storage overheads and the substantial computation cost of CNNs are problematic in hardware accelerators. Computing-in-memory (CIM) architecture has demonstrated great potential to effectively compute large-scale matrix-vector multiplication. However, the intensive multiply and accumulation (MAC) operations executed at the crossbar array and the limited capacity of CIM macros remain bottlenecks for further improvement of energy efficiency and throughput. To reduce computation costs, network pruning and quantization are two widely studied compression methods to shrink the model size. However, most of the model compression algorithms can only be implemented in digital-based CNN accelerators. For implementation in a static random access memory (SRAM) CIM-based accelerator, the model compression algorithm must consider the hardware limitations of CIM macros, such as the number of word lines and bit lines that can be turned on at the same time, as well as how to map the weight to the SRAM CIM macro. In this study, a software and hardware co-design approach is proposed to design an SRAM CIM-based CNN accelerator and an SRAM CIM-aware model compression algorithm. To lessen the high-precision MAC required by batch normalization (BN), a quantization algorithm that can fuse BN into the weights is proposed. Furthermore, to reduce the number of network parameters, a sparsity algorithm that considers a CIM architecture is proposed. Last, MARS, a CIM-based CNN accelerator that can utilize multiple SRAM CIM macros as processing units and support a sparsity neural network, is proposed., IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2021

Resistive random-access memory (ReRAM)-based architectures can be used to accelerate Convolutional Neural Network (CNN) training. However, existing architectures either do not support normalization at all or they support only a limited version of it. Moreover, it is common practice for CNNs to add normalization layers after every convolution layer. In this work, we show that while normalization layers are necessary to train deep CNNs, only a few such layers are sufficient for effective training. A large number of normalization layers do not improve prediction accuracy; it necessitates additional hardware and gives rise to performance bottlenecks. To address this problem, we propose DeepTrain, a heterogeneous architecture enabled by a Bayesian optimization (BO) methodology; together, they provide adequate hardware and software support for normalization operations. The proposed BO methodology determines the minimum number of normalization operations necessary for a given CNN. Experimental evaluation indicates that the BO-enabled DeepTrain architecture achieves up to 15X speed-up compared to a conventional GPU for training CNNs with no accuracy loss while utilizing only a few normalization layers.

Convolution Neural Network (CNN) accelerators are commonly used to boost the CNN application's performance. The energy efficiency of the CNN accelerators is of paramount importance for battery-operated devices like smartphones. A substantial fraction of their energy consumption is due to off-chip memory accesses. These accelerators connect to the off-chip memory by a wide bus to improve the throughput. However, accessing the data from an unaligned address or size that is not a multiple of bus width leads to low bus width utilization and wastage of energy. Memory accesses can be reduced considerably by partitioning the data in a way that increases the number of aligned accesses and optimally utilizes bus width. We propose an approach that factors in the architectural parameters to evaluate memory access. Our tool determines optimal partitioning and data reuse scheme for convolution and fully connected layers to minimize the off-chip memory accesses for these accelerators. Compared to state-of-the-art, our approach reduces off-chip memory accesses of AlexNet, VGG16, and ResNet:50 by 9%, 16%, and 28% on 64 bits data bus and by 16%, 29%, and 46% on 128 bits data bus, respectively.

The increasing throughput of experiments in biomaterials research makes automatic techniques more and more necessary. Among all the characterization methods, microscopy makes fundamental contributions to biomaterials science where precisely focused images are the basis of related research. Although automatic focusing has been widely applied in all kinds of microscopes, defocused images can still be acquired now and then due to factors including background noises of materials and mechanical errors. Herein, we present a deep-learning-based method for the automatic sorting and reconstruction of defocused cell images. First, the defocusing problem is illustrated on a high-throughput cell microarray. Then, a comprehensive dataset of phase-contrast images captured from varied conditions containing multiple cell types, magnifications, and substrate materials is prepared to establish and test our method. We obtain high accuracy of over 0.993 on the dataset using a simple network architecture that requires less than half of the training time compared with the classical ResNetV2 architecture. Moreover, the subcellular-level reconstruction of heavily defocused cell images is achieved with another architecture. The applicability of the established workflow in practice is finally demonstrated on the high-throughput cell microarray. The intelligent workflow does not require a priori knowledge of focusing algorithms, possessing widespread application value in cell experiments concerning high-throughput or time-lapse imaging., Graphical abstract Image 1, Highlights • An automatic workflow for the sorting and reconstruction of defocused images. • Representative data containing varied cells, substrate materials, and magnifications. • Effectiveness of the workflow in high-throughput experiments. • Publicly accessible image datasets and codes.

Coarse-grained reconfigurable architectures (CGRAs) provide high energy efficiency with word-level programmability rather than bit-level ones such as FPGAs. The coarser reconfigurability brings about higher energy efficiency and reduces the complexity of compiler tasks compared to the FPGAs. However, application mapping process for CGRAs is still time-consuming. When the compiler tries to map a large and complicated application data-flow-graph(DFG) onto the reconfigurable fabric, it tends to result in inefficient resource use or to fail in mapping. In case of failure, the compiler must divide it into several sub-DFGs and goes back to the same flow. In this work, we propose a novel partitioning method based on a genetic algorithm to eliminate the unmappable DFGs and improve the mapping quality. In order not to generate unmappable sub-DFGs, we also propose an estimation model which predicts the mappability and resource requirements using a DGCNN (Deep Graph Convolutional Neural Network). The genetic algorithm with this model can seek the most resource-efficient mapping without the back-end mapping process. Our model can predict the mappability with more than 98% accuracy and resource usage with a negligible error for two studied CGRAs. Besides, the proposed partitioning method demonstrates 53-75% of memory saving, 1.28-1.39x higher throughput, and better mapping quality over three comparative approaches.

Unmanned aerial vehicles (UAVs) serve as aerial base stations to provide controlled wireless connections for ground users. Due to their constraints on both mobility and energy consumption, a key problem is how to deploy UAVs adaptively in a geographic area with changing traffic demand of mobile users, while meeting the aforementioned constraints. In this paper, we propose a QoE-driven and energy-efficient adaptive deployment strategy for multi-UAV networks based on hybrid deep reinforcement learning to solve the problem of incomplete information game, where the UAVs can adjust their moving directions and distance to serve users who move randomly in the target area. Through the hybrid deep reinforcement learning with centralized training and distributed testing, UAVs can be trained offline to obtain the global state information and learn a completely distributed control strategy, with which each UAV only needs to take actions based on its observed state in the real deployment to be fully adaptive. Moreover, in order to improve the speed and effect of learning, we improve hybrid reinforcement learning, by adding genetic algorithms and TD-error-based resampling optimization mechanism. Simulation results show that the hybrid deep reinforcement learning algorithm has better efficiency and robustness in multi-UAV control, and has better performance in terms of QoE, energy consumption and average throughput, by which average throughput can be increased by 20% to 60%.

Unmanned Aerial Vehicle (UAV)-assisted communications has attracted increasing attention recently. This paper investgates air-ground coordinated communications system, in which trajectories of air UAV base stations (UAV-BSs) and access control of ground users (GUs) are jointly optimized. We formulated this optimization problem as a mixed cooperative-competitive game, where each GU competes for the limited resources of UAV-BSs to maximize its own throughput by accessing a suitable UAV-BS, and UAV-BSs cooperate with each other and design their trajectories to maximize the defined fair throughput to improve the total throughput and keep the GU fairness. Moreover, the action space of GUs is discrete, while that of UAV-BS is continuous. To tackle this hybrid action space issue, we transform the discrete actions into continuous action probabilities and propose a multi-agent deep reinforcement learning (MADRL) approach, named AG-PMADDPG (air-ground probabilistic multi-agent deep deterministic policy gradient). With well-designed rewards, AG-PMADDPG can coordinate two types of agents, UAV-BSs and GUs, to achieve their own objectives based on local observations. Simulation results demonstrate that AG-PMADDPG can outperform the benchmark algorithms in terms of throughput and fairness.

Radio Frequency Identification (RFID) has been one of the critical technologies of the Internet of Things (IoT). With the rapid development of the IoT, the RFID systems are required to be more efficient and with high throughput capacity. In the widespread IoT application scenes, the collision problem of the RFID tags has become the increasingly remarkable problem in RFID systems. Traditionally, the anti-collision algorithms of RFID systems are always based on time division multiple access (TDMA). Although the TDMA based anti-collision algorithms are simple and easy to implement, it often misses tags and costs high time. Afterwards, the anti-collision algorithms based on blind source separation (BSS) have been introduced. These BSS based anti-collision algorithms are more efficient and stable, but they are mostly suitable for the determined or overdetermined case, i.e., the number of tags is less than that of the readers in RFID systems. Only a few anti-collision algorithms are taken into account of the underdetermined collision model. Because this underdetermined RFID collision model will give rise to more difficult solution but with very meaningfully practical IoT applications. Therefore, to investigate high quality underdetermined anti-collision algorithm for RFID system plays an important role in improving the efficiency of RFID system, and enable RFID implement more wide applications in future IoT systems. As a motivation, this paper proposes a new anti-collision algorithm for underdetermined RFID mixed system for performance improvement. In this work, the nonnegative matrix factorization (NMF) with minimum correlation and minimum volume constrains, i.e., the new MCV_NMF algorithm is proposed for anti-collision application in underdetermined RFID systems. This algorithm combines the independent principle of the tag signals with the NMF mechanism to achieve performance enhancement. The experimental results and analysis corroborate that this new algorithm can implement the underdetermined collision problem well and enhance the throughput capacity of RFID system.

The capability to obtain detailed motility information of model organisms is fundamental to reveal their functional and social behavior characteristics. Zebrafish is a powerful vertebrate model organism. Despite recent success in the automatic quantification of adult zebrafish movement, it remains a laborious task for group zebrafish larval tracking due to their similar appearance, frequent occlusions, and highly discontinuous kinematics. This article presents DanioSense (DS), an automatic tracker for group larval zebrafish, to overcome these tracking challenges. The integration of a light convolutional neural network and a centerline extraction algorithm enables the tracker to localize individuals even in occlusion cases where objects' identities are prone to switch. With reliable detections, an adaptive Kalman filter is designed to optimally estimate locomotive parameters, which is also used for object reidentification accomplished by a two-stage data association protocol. Experimental results demonstrated a tracking accuracy of over 97%, median errors of 102 μm, and 8.8° for the position and orientation measurement, and a processing speed of over 30 frames/s with a normal computer configuration. DS provides detailed quantitative data for a large-scale larvae group in nearly real time, highly boosting the efficiency of characterizing individual phenotypes and analyzing social interactions.

Data-parallel computing platforms, such as Hadoop and Spark, are deployed in computing clusters for big data analytics. There is a general tendency that multiple users share the same computing cluster. The schedule of multiple jobs becomes a serious challenge. Over a long period in the past, the Shortest-Job-First (SJF) method has been considered as the optimal solution to minimize the average job completion time. However, the SJF method leads to a low system throughput in the case where a small number of short jobs consume a large amount of resources. This factor prolongs the average job completion time. We propose an improved heuristic job scheduling method, called the Densest-Job-Set-First (DJSF) method. The DJSF method schedules jobs by maximizing the number of completed jobs per unit time, aiming to decrease the average Job Completion Time (JCT) and improve the system throughput. We perform extensive simulations based on Google cluster data. Compared with the SJF method, the DJSF method decreases the average JCT by 23.19% and enhances the system throughput by 42.19%. Compared with Tetris, the job packing method improves the job completion efficiency by 55.4%, so that the computing platforms complete more jobs in a short time span.

This paper considers NOMA-ALOHA, ALOHA implemented over NOMA (non-orthogonal multiple access), that can decode simultaneously transmitted multiple signals via successive interference cancellation (SIC). We analyze the throughput of NOMA-ALOHA from the perspective of MAC layer when the maximum two signals can be simultaneously decoded and there are no more than NSIC users, where NSIC is the smallest number K such that two-level SIC cannot work if more than K users simultaneously transmit a packet. We mathematically prove that the maximum throughput of NOMA-ALOHA is always higher than 0. 593 and lower than 0.724 when total number of users is no bigger than NSIC and that NOMA-ALOHA enhances the throughput of traditional slotted ALOHA at least by 57.8 percent if NSIC is no more than 50. We suggest practical transmission probabilities that yield a throughput close to the maximum throughput.

To meet the tremendous demand of Internet of Things (IoT) applications, the 3rd Generation Partnership Project (3GPP) has specified the Narrowband IoT (NB-IoT) standard. However, collisions in the random access (RA) channel of NB-IoT can be severe due to mismatch between frequent random access attempts by a huge number of devices and the limited radio resources. In this paper, a new random access mechanism called time-alignment-value based random access (TARA) is designed to improve the efficiency of random access of NB-IoT. The key mechanism of TARA is to conduct quick retries upon failure by exploiting the difference of time-alignment (TA) values in collided preambles. To analyze TARA rigorously, a theoretical model of TARA is derived, and its validity is verified via simulations. Further simulations are carried out to evaluate TARA with respect to different system parameters. Comparisons with existing schemes are also conducted. Both analytical and simulation results show that, under various system parameters, TARA achieves 30% higher success probability of random access, 75% higher throughput, and 40% lower access delay than the original slotted Aloha mechanism of NB-IoT. It also highly outperforms other random access schemes.

As deep learning inference applications are increasing, an embedded device tends to equip neural processing units (NPUs) in addition to a CPU and a GPU. For fast and efficient development of deep learning applications, TensorRT is provided as the SDK for NVIDIA hardware platform, including optimizer and runtime that delivers low latency and high-throughput for deep learning inference. Like most deep learning frameworks, TensorRT assumes that the inference is executed on a single processing element, GPU or NPU, not both. In this paper, we propose a parallelization methodology to maximize the throughput of a single deep learning application using both GPU and NPU by exploiting various types of parallelism on TensorRT. With six real-life benchmarks, we could achieve 81% 391% throughput improvement over the baseline inference using GPU only.

This review provides a broad summary of the performance characteristics of high-throughput severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) serologic assays with Food and Drug Administration Emergency Use Authorization, which are commonly found in central clinical laboratories. In addition, this review discusses the current roles of serologic testing for SARS-CoV-2 and provides a perspective for the future.

In this paper we present a novel, ultra-compact, True Random Number Generator (TRNG) architecture and its FPGA implementation. The proposed Latched Ring Oscillator (LRO) TRNG allows the generation of a TRNG bit from a single FPGA Slice. Despite its very compact structure, the proposed LRO-TRNG relies on both meta-stability and accumulated jitter as entropy sources, and exhibits very good results in terms of unpredictability and randomness. The proposed architecture has been implemented on Xilinx Spartan-6 devices and the TRNG performances have been extensively validated under supply voltage and temperature variations. Measurements results have shown that the LRO-TRNG exhibits an estimated entropy of about 7.99834 per bit (according to T8 test of the AIS-31) and a throughput of 0.76 Mbits/s with a 50MHz clock. A comparison against the state of the art shows that the proposed LRO-TRNG outperforms most of the previously published TRNGs, in terms of the ratio between throughput and FPGA resources usage.

The traditional finite element method-based fluorescence molecular tomography (FMT)/ X-ray computed tomography (XCT) imaging reconstruction suffers from complicated mesh generation and dual-modality image data fusion, which limits the application of in vivo imaging. To solve this problem, a novel standardized imaging space reconstruction (SISR) method for the quantitative determination of fluorescent probe distributions inside small animals was developed. In conjunction with a standardized dual-modality image data fusion technology, and novel reconstruction strategy based on Laplace regularization and L1-fused Lasso method, the in vivo distribution can be calculated rapidly and accurately, which enables standardized and algorithm-driven data process. We demonstrated the method's feasibility through numerical simulations and quantitatively monitored in vivo programmed death ligand 1 (PD-L1) expression in mouse tumor xenografts, and the results demonstrate that our proposed SISR can increase data throughput and reproducibility, which helps to realize the dynamically and accurately in vivo imaging.

In-situ (InS) server systems are typically deployed in special environments to handle in-situ workloads which are generated from environmentally sensitive areas or remote places lacking modern power supply infrastructure. This special operating environment of InS servers urges such systems to be powered by renewable energy. In addition, the InS systems are vulnerable to soft errors due to the harsh environments they deploy. This paper tackles the problem of allocating harvested energy to renewable powered servers and assigning the in-situ workloads to these servers for optimizing throughput of both the overall system and individual servers under energy and reliability constraints. We perform the energy allocation based on system state. In particular, for systems in low energy state, we propose a game theoretic approach that models the energy allocation as a cooperative game among multiple servers and derives a Nash bargaining solution. To meet the reliability constraint, we analyze the reliability optimality of assigning tasks to multiple servers and design a reliability-aware task assignment heuristic based on the analysis. Experimental results show that with a small time overhead, the proposed energy allocation approach achieves a high throughput from perspectives of both the overall system and individual servers, and the proposed task assignment approach ensures an increased system reliability.

Business cloud workflows are often designed with multiple time constraints for timely response to business requests. To ensure on-time completion of workflow instances, workflow temporal conformance state needs to be constantly monitored and verified at runtime. Considering the fact that there are a large number of workflow instances running in a parallel fashion in many business scenarios, conventional verification approaches for time-related properties using such as temporal logic or timed Petri nets are not feasible due to the limitation of low efficiency at runtime. To address this issue, we propose a new approach to automated runtime verification of temporal conformance for parallel workflow instances in a cloud environment. Instead of using response time to verify temporal conformance of every single workflow as in conventional strategies, workflow throughput is employed as the performance measurement to efficiently monitor a large number of parallel workflow instances. On this basis we present a novel conformance verification strategy. This strategy considers the effect of time delay propagation in the cloud workflow systems to accurately verify workflow runtime temporal conformance. Our verification strategy is implemented in a prototype cloud workflow system and the evaluation results show that it outperforms the state-of-the-art workflow temporal verification strategy.

The global healthcare industry and artificial intelligence has promoted the development of the diversified intelligent healthcare applications. IoT will play an important role in meeting the high throughput requirements of diversified intelligent healthcare applications. However, the healthcare big data transmission is vulnerable to a potential attack, which can cause network outages and serious healthcare security issues. To process complex healthcare security event in real time, security performance prediction is critical for mobile IoT-enabled healthcare networks. In this paper, we first analyze the security performance, and derive the novel expressions. Then, to analyze the security performance in real time, an security performance intelligent prediction algorithm is proposed. An improved CNN model is designed, which combines four layer convolutions and a four-branch inception block. Compared with different methods, the proposed intelligent algorithm can obtain better security performance prediction. In particular, for prediction precision, the proposed intelligent algorithm is increased by 20%.

It is still a grand challenge to implement a high-accuracy and high-performance stereo matching algorithm on a resource-limited hardware platform in stereo vision systems. This paper proposes a resource-efficient pipelined hardware architecture with four-cycle time-sharing for the semi-global matching (SGM) algorithm with weighted path cost aggregation. To save hardware resources, we also combined image down-sampling and disparity skipping in the SGM algorithm. The presented architecture is synthesized and implemented on a Zynq-7 FPGA board, which results in a throughput of 1280 × 960/62.5 fps with 75 disparity levels at the maximum frequency of 216 MHz. To improve the accuracy of the disparity map at close range, we also adapt the presented architecture with two-cycle time-sharing, and the disparity range is increased to 128, which attains the processing of 1280×960/116 fps at 200 MHz on VCU-118 FPGA board; the throughput reaches 18245 MDE/s. The result shows that the whole architecture only takes 50465 LUTs, 48046 Registers, 125.5 BRAMs with 128 disparity levels, which is much more efficient than the latest reference work.