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A 5.8GHz four-channel transmitter RF beamforming IC based on a vector modulator fabricated via the 130 nm RF CMOS process is presented here. The vector modulator controls the gain and phase independently by steering the tail current sources of a Gilbert-cell-based vector synthesizer. It offers 8-bit phase control for 360 ∘ and 4-bit gain control for a 20 dB dynamic range, with the size not depending on the control bits. A four-way differential RF power divider is introduced to implement the four-channel IC, in which off-chip ground bonding inductance is resonated out through the introduction of additional capacitances to a λ/4 impedance transformer of a four-way Wilkinson divider to reduce the insertion losses and errors. The measured total RMS gain error of the vector modulator is 0.312 dB and the total RMS phase error is 0.329 ∘. It shows 20 mW DC power consumption per channel, 5.19 dBm OP1dB, and a 3 dB gain overall including 6 dB of dividing loss.

A frequency-reconfigurable SP4T switch is presented, in which RON×COFF characteristics of switch transistors are enhanced with plaid metal transistors and forward body biasing. Plaid metal transistors (PMT) with forward body bias (FBB) are used for all of the transistors to enhance the FoM. The plaid patterned metal accesses of a transistor for the source and drain decrease the extrinsic resistance and capacitance. FBB increases the overdrive voltage of a transistor and decreases the on-resistance. The SP4T switch includes main switch matrices that route an input signal to four-outputs, a switched inductor (SI) network, and a mode-selection switch. The SI network connected through the mode-selection switch resonates out the off-capacitances of the main switch matrices at RF in the RF mode. The SP4T switch operates without the SI network in DC mode. The SP4T switch is implemented in a 28-nm FDSOI CMOS process. The core area occupies 0.2 mm2. The switch shows less than 2 dB insertion loss from DC to 4.4 GHz in the DC mode and from 4.4 to 5.3 GHz in the RF mode, where isolations are more than 16.8 dB and 18 dB, respectively.

This article presents two millimeter-wave frequency reconfigurable dual-band CMOS power amplifiers (PAs) for fifth-generation (5G) communications comprising a single-stage dual-band PA and a two-stage dual-band PA for higher gain. The PAs cover multiple 5G communication bands, n257 (26.5-29.5 GHz) and n260 (37-40 GHz), which use reconfigurable transmission line transformers (TLTs) for output, input, and interstage matching networks. These matching networks allow the operating frequency bands to be changed, thereby achieving optimum performance. The integrated mode selection switches in the transformers reconfigure the inductances of the TLTs to cover two frequency bands, which allows the PAs to have small overall chip sizes. These are fabricated in a 28-nm bulk CMOS process. The single-stage dual-band PA achieves 20.2-/19.1-dBm saturated output power ( ${P}_{sat}$ ), 18.7-/18.6-dBm 1-dB compressed output power ( ${P}_{1 dB}$ ), and 33.6%/32% peak power-added efficiency (PAE) at 26.5 and 37 GHz, respectively, while occupying a chip area of 0.11 mm². The two-stage dual-band PA achieves 19.1-/19.5-dBm ${P}_{sat}$ , 17-/17.8-dBm ${P}_{1 dB}$ , and 31.3%/30.5% PAE at 26.5 and 37 GHz, respectively, while occupying a chip area of 0.165 mm². Both PAs are tested under 64-quadrature amplitude modulation signals with a 100-MHz channel bandwidth. The single-stage PA achieves 14.7- and 12.3-dBm average output powers ( ${P}_{avg}$ ) with -25.1- and -25-dB error vector magnitudes (EVMs) at 26.5 and 37 GHz, respectively. The two-stage PA achieves 12.3- and 11.6-dBm ${P}_{avg}$ 's with -25.3- and -25.1-dB EVMs at 26.5 and 37 GHz, respectively.

A differential four-way power divider for 24 to 30 GHz and a frequency reconfigurable differential four-way power divider for 24 to 30 GHz and 37 to 43.5 GHz are presented. The differential structure provides sound virtual grounds in a multiple-channel chip. Both circuits have a four-way Wilkinson power divider (WPD) configuration based on lumped elements that provide small chip sizes. The first one has a small core chip area of 0.09 mm², a small insertion loss of 0.93 to 1.94 dB, and the port-to-port isolation of 19.1 to 25.6 dB from 24 to 30 GHz. It has a small amplitude and phase differences at four outputs. The second one allows frequency-reconfigurable operation by switching inductances and capacitances to cover widely separated frequency bands (5G NR n257-n261 bands). In addition, switched capacitors (SCs) are inserted to resonate out the parasitic series inductances in isolation resistors at both bands of 24-30 GHz and 37-43.5 GHz. It has a core chip area of 0.168 mm², insertion losses of 1.65-1.89 dB at 24 to 30 GHz and 2.04-2.70 dB at 37 to 43.5 GHz, respectively. The port-to-port isolations are 23.4-37.6 dB at 24 to 30 GHz and 22.6-28.4 dB at 37 to 43.5 GHz.

This article proposes a method to detect vocal signals and the corresponding locations of multiple humans using a multiple-input and multiple-output (MIMO) frequency-modulated continuous-wave (FMCW) radar system. The signals of multiple humans are extracted with digital beamforming by the virtual array generated by MIMO radar processing. To remove body motion artifacts that distort the speech information detected by the radar, a body motion effect cancellation method is proposed. The technique allows recovering vocal signals from detected distorted signals by estimating phase variations due to body motions. A combination of the proposed vocal signal detection algorithm with a human localization one enables to detect speaking humans by means of the MIMO radar. Experiments verify that the proposed method can accurately locate and detect speaking humans based on their vocal vibration signals.

A Ka -band CMOS two-stage Doherty power amplifier (DPA) is presented, whose back-off efficiency is improved by voltage-mode Doherty load modulation. The input and output networks of its power stage are composed of transmission line transformers (TLTs) and single-ended Doherty networks implemented with lumped elements. An adaptive bias circuit to boost the Doherty operation is included in the gate network of the auxiliary amplifier. It shows a power gain of 16.2 dB with 48.2% peak drain efficiency (DE) and 25% 6-dB back-off DE at 26 GHz. It has two times higher 6-dB back-off efficiency in comparison to that of a theoretical class-A power amplifier. It is fabricated in a 28-nm bulk CMOS process and occupies 0.094-mm2 core size.

A 28-GHz linear CMOS cascode power amplifier (PA) that adopts two types of analog linearization methods, dynamic conductance control (DCC) and body carrier injection (BCI), is presented here. The former method controls the load conductance of a common-source (CS) amplifier according to the input power of the PA. This improves the AM–AM and AM–PM characteristics of the cascode PA, which is also analyzed with an equivalent circuit model. The latter injects the carrier signal into the body of a common-gate (CG) transistor, which increases the voltage headroom of the CS transistor. This improves the AM–AM of the cascode PA and also helps to stabilize the PA by reducing the drain–source capacitance of the CG transistor. The proposed PA is fabricated in a 65-nm CMOS process and shows a gain of 15.9 dB, an output 1-dB compression point of 17.7 dBm, and a saturation output power of 19.1 dBm with a peak power-added efficiency (PAE) of 41.2% at 28 GHz.

In this work, we propose a current-mode dielectric spectroscopy integrated circuit (IC) for the detection of liquids permittivity at microwave frequency range. The current-mode sensing scheme presents wideband operation with enhanced dynamic range compared to conventional voltage-mode sensing approach. A low intermediate frequency (IF) receiver architecture further provides better performances in flicker noise, dc offset, and harmonic mixing that degrade a sensor accuracy in zero-IF receiver architecture. Measured maximum conversion gain is 31.4 dB at 0.4 GHz RF frequency, while the 1dB-compression point ( $P_{\text{1}dB}$ ) is measured to be -8 dBm at 1 GHz RF frequency. The operation frequency of the proposed spectroscopy IC is from 50 MHz to 4 GHz according to 3 dB bandwidth. The permittivity measurements for propanol across the frequency range of 0.03-10 GHz are performed with root mean square (rms) permittivity error of 0.49. The dielectric spectroscopy IC is fabricated in 28-nm CMOS technology with active area of 0.5 mm × 0.2 mm only, while consuming 13 mW from a 1.2 V supply.

This brief presents a variable-gain low-noise amplifier (VG-LNA) with a common gate (CG) cross-summing configuration, which is fabricated using a 65-nm RF CMOS process. It has a wide gain control range as well as a high input 1 dB gain compression point (IP1dB) at high-gain by introducing a split common-gate transistor (SCGT) technique. In addition, output phase compensation is achieved by adopting a tuning capacitor at the cascode node. This LNA is designed as 2-stage cascode, and the area excluding the pad is 0.2 mm2. It consumes 25.2 mW with a 1.2-V power supply. It shows a gain of 25 dB and a noise figure of 3.4 dB at 22 GHz. The measured minimum IP1dB is −27.5 dBm, and the root-mean-square phase error is 0.34° over the gain control range of 14 dB at 22 GHz.

A Ka-band variable-gain phase shifter (VGPS) using a multi-vector summation method is proposed, which represents both phase and amplitude by summing the I and Q signals of multiple vectors. The VGPS has an orthogonal phase and gain control function with a wide gain-control dynamic range because it is designed to keep the input and output impedances almost constant regardless of the control states. It shows a measured RMS phase error of 2.9 ° during 17.3 dB gain control and that of 3.5 ° during simultaneous 17.3 dB gain and 360 ° phase control without any calibration from 30 to 32.5 GHz. The measured average insertion loss ranges from −4 to −2.8 dB from 28 to 33 GHz. It is implemented in a 65-nm RF CMOS process with the size of 0.21 mm2 excluding pads.

An antenna switch embedded in the matching transmission line transformers (TLTs) of a differential power amplifier (PA) and LNA is presented, which selects the transmitter and receiver (Tx and Rx) in 5G communication systems. Because the switching function is implemented in the matching networks of a PA output and an LNA input, the chip size and insertion loss are reduced. A balun, an antenna switch, and matching networks of the PA and LNA are implemented simultaneously by carefully designing a three-port series-combining TLT with Tx and Rx switches. The measured insertion losses of Tx and Rx are 0.42 and 1.01 dB, respectively, at 28 GHz, and the isolation values of the Tx and Rx paths are 24.1 and 31.7 dB, respectively.

A single-pole double-throw (SPDT) CMOS switch at 15–25 GHz is presented, which has a small size, low insertion losses, and high-power handling capabilities for both output nodes. It has an SPDT structure in which nMOS and pMOS are alternately used as series and shunt transistors. An inductor-matching network is placed between two output nodes for input and output matching, which is also used to increase isolation by resonating out the off capacitances. The proposed SPDT switch is fabricated using a 28-nm CMOS process. It achieves an insertion loss of less than 1.9 dB from 15 to 25 GHz. The measured IP0.2dB of two outputs is 17.4 and 18.3 dBm, respectively. It has an isolation of 25 dB at 20 GHz. The measured ON/OFF switching time is less than 2.3 ns. The proposed SPDT switch has a core area of only 0.02 mm2.

A 28-GHz two-stage differential cascode power amplifier (PA) linearized with a simple common-source (CS) body network, in which the body of the CS amplifier at the power stage is connected to the drain through a large resistance. The body network is very simple but very effective to linearize the PA. The linearity improvements are explained and shown with the intermodulation distortions (IMD3) and AM-PM characteristics. The PA also shows a wideband gain because the matching networks consist mainly of transmission-line transformers (TLTs) and distributive interstage matching. It has a gain of 20.1 dB with a bandwidth of 10.8 GHz, a saturation output power of 20.25 dBm, and an output 1-dB compression point of 18.3 dBm, which is fabricated in a 40-nm bulk CMOS process with the area of 0.214 mm 2 .

A 28-GHz in-band full-duplex (IBFD) power amplifier (PA) is presented which integrates a PA with an impedance matched hybrid transformer in a 28-nm bulk CMOS process. The hybrid transformer has a 1:2 turn ratio to match from the optimum load impedance of $25~\Omega $ for a PA to the antenna and balance ports of $100~\Omega $ . Since this allows the additional matching circuits of a PA and an antenna to be obviated, the full-duplex loss is reduced. It shows 28.4-dB isolation between the PA and LNA ports at 28 GHz. For comparisons, a 50- $\Omega $ matched PA and an IBFD PA are designed. The IBFD PA has core sizes of $0.24\times 0.43\,\,{\text {m}}{\text {m}}^{2}$ . Since the impedance matched hybrid transformer has the similar size to the output matching network of the 50- $\Omega $ matched PA, a full duplexer is integrated into the PA without additional chip area. The IBFD PA has 10.6-dB gain and a drain efficiency of 8.9% at 12.3-dBm P1dB.

A 60-GHz polar vector modulator with a lookup table (LUT)-based calibration for a variable gain active phase shifter is presented. It consists of an input buffer, an I/Q generator, a vector summing amplifier, and 6-bit phase/gain digital-to-analog converters (DACs). It is very difficult to obtain accurate gain and phase characteristics of a polar vector modulator due to circuit imperfections, such as I/Q imbalance, current mismatches of DACs, and impedance variations over polar vector states. Thus, calibrations are essential to have accurate gain and phase states. This letter introduces an LUT-based calibration method to map possible 213 states (5-bit gain and 8-bit phase) onto targeted polar states, which minimizes gain and phase errors drastically. The proposed phase shifter with a generated LUT shows an rms gain and phase errors of 0.13 dB and 0.8°, respectively, at the center frequency of 60 GHz. In addition, it has an rms gain and phase errors of

This letter presents a three-stage differential power amplifier (PA) with an adaptive built-in linearizer (ABL) that achieves an enhanced AM–AM linearity. Series inductors are introduced at cascode internodes to improve the output matching conditions of the cascode amplifiers and stabilize a high-gain PA operation. Capacitors at the gate in the common-gate amplifiers at the power stage are used to achieve high differential gain by reducing RF coupling at the virtual ground and equalizing the drain-source voltage swings. Broad-side coupled transmission line transformers are used for all matching networks. It has 25.5-dB peak power gain and 12.2-dBm saturation output power at 110 GHz with 3-dB bandwidth of 92.5 and 117 GHz. It has a core chip size of 0.76 mm2 and a peak power-added efficiency (PAE) of 8.5%.

This paper describes Ka-band inductor-shared RF switches and their applications to a 35.2-ps 6-bit true-time-delay (TTD) switched-line (SL) phase shifter (PS). The inductor-shared RF switches share an inductor to match the input and output (I/O) ports of different states, which are realized with a switched inductor for SP ${n}\text{T}$ case and with a shared matching network for DP ${n}\text{T}$ case. The switches are applied to controlling most significant 3 bits of the proposed TTD SL PS. The delay lines and reference lines of the PS are implemented with microstrip lines and inverted microstrip lines in the same space, respectively. The dual-side microstrip lines allow it to have not only a small size but also compensation of the loss difference between the signal lines with different lengths. The least significant 3 bits are implemented with the modified structure of the SL PS, which reduces the size further by replacing a reference line by a series switch. The test chip is fabricated in a 65-nm CMOS process. It operates in the range of 20–30 GHz occupying a 0.18 mm2 core size. Its measured insertion loss and IP1dB are 11 dB and 6.5 dBm at 28 GHz, respectively. The measured gain error and rms delay error are less than 2 dB and 0.7 ps at operation frequencies.

A 28-GHz power amplifier (PA) with adaptive cross feedback (ACF) is presented. The ACF is employed by an adaptively controllable RC-feedback circuit from the source to the opposite drain nodes of the common-gate (CG) stages in a differential cascode amplifier. The proposed ACF makes the PA stable even with large power transistors. It also linearizes the PA by decreasing the feedback adaptively at high powers which improves amplitude distortion (AM-AM) and power-added efficiency (PAE) as well as the saturation power (P Sat ). The proposed PA is implemented with a 28-nm bulk CMOS process with a 0.144 um2core chip area. It is shown that the ACF increases P Sat , peak PAE, and output 1-dB gain compression point (OP 1dB ) from 20.1 dBm to 20.4 dBm, 34% to 37.2%, and 17.4 dBm to 18.2 dBm, respectively at 28.5 GHz. The proposed PA shows a 28-dB peak gain at 28.6 GHz with 26.8 GHz to 30.8 GHz (14.0%) 3-dB gain bandwidth, which is the highest P Sat and gain among the reported Ka-band bulk CMOS PAs.

A frequency reconfigurable dual-band power amplifier (PA) with reconfigurable transmission line transformers (TLT) is presented, which can be operated at both the n257 (26.5-29.5 GHz) and n260 (37–40 GHz) 5G communication bands. The PA utilizes reconfigurable TLTs for output and input matching networks to reconfigure the PA between the n257 and n260 bands with optimal performance in both bands. The reconfigurable TLTs provide frequency reconfigurability to the PA by changing both the primary and secondary side inductances of the TLTs. The switches for the TLTs are located in the space inside the TLTs, which results in a small overall chip area. The dual-band PA is fabricated using a 28-nm bulk CMOS process. It achieves 20.2 and 19.1 dBm saturated output powers, 18.7 and 18.6 dBm 1-dB compressed output powers and 33.6% and 32% peak power added efficiencies at 26.5 and 37 GHz, respectively. The dual-band PA has a core size of 0.11 mm2.

A differential four-way power divider in 65 nm CMOS process for a beamforming front-end IC is presented, which provides stable virtual grounds regardless of grounding inductance variations. The chip size is reduced by using a 4-way Wilkinson power divider based on lumped elements. It has a small core chip size of 0.09 mm’. At 24 to 30 GHz, it has a low insertion loss of only 0.93 to 1.94 dB, a port-to-port isolation of 19.1 to 25.6 dB from 24 to 30 GHz. It has small amplitude and phase difference which are much better than a single-ended structure.

In this paper, feature-based gesture recognition in a frequency modulated continuous wave (FMCW) radar system is introduced. We obtain a range-Doppler map (RDM) from raw signals of FMCW radar and generate a variety of features from the RDM. The features are broadly defined to reflect radar-specific characteristics as well as statistical values commonly used in machine learning. Among these radar features, those that are highly correlated with gesture recognition are selected by the proposed feature selection algorithm, which is a wrapper-based feature selection algorithm incorporated with a quantum-inspired evolutionary algorithm (QEA). Furthermore, the information factor based on the minimum redundancy maximum relevance criterion is applied to QEA in order to find feature subsets effectively. The proposed algorithm is able to extract from all feature sets feature subsets related to gesture recognition, and improves the gesture recognition accuracy of the FMCW radar system. In addition, we analyze which features of the radar are helpful for gesture recognition and perform effective gesture recognition using the features determined through feature analysis.

A 4-terminal microelectromechanical systems (MEMS) relay has long been sought for signal switching applications because it allows de-coupling of the actuation (body and gate) and signal (source and drain) components unlike a 3-terminal MEMS relay. However, the contact resistance still remains a serious problem in current 4-terminal MEMS relays compared with the 3-terminal MEMS relays. In this paper, using theoretical analysis, we first determined that the two-contact design, which was the most common design in the 4-terminal MEMS relay, was the origin of the high contact resistance. We subsequently developed a 4-terminal MEMS relay with a novel single-contact design. The fabricated 4-terminal MEMS relay with the single-contact design exhibited a contact resistance of 18 $\text{m}\Omega $ . To the best of our knowledge, this result is the lowest value among 4-terminal MEMS relays. In addition, we demonstrated that the two-contacts are the origin of the high contact resistance using measurement. The relay operated up to $1.1\times 10^{6}$ cycles at 1 V / 50 mA in air and hot switching conditions. Finally, the proposed 4-terminal MEMS relay was hermetically packaged for use in commercial applications. [2017-0183]

This paper presents matching condition for detector at THz frequencies, which directly read signals from an integrated antenna. We use direct THz-signal detections with CMOS transistors in non-resonant plasma wave mode, which are embedded in on-chip resonating antennas. The detector detects THz envelope signals directly from the side edges of the on-chip patch antennas. The signal detection mechanism is studied in the view of the impedance conditions of the antenna and the detector. The detectors are implemented with stacked transistors structures to achieve high responsivity. The measured responsivities of the detectors with antenna impedances that were simulated to be 599.7, 912.3, 1565, and 3190.6 Ω agree well with the calculated values. Moreover, the responsivity dependence on the detector impedance is shown with two different input impedances of the detectors. Since CMOS circuit models from foundry are not accurate at frequencies higher than f t , the matching guideline between the antenna and the detector is very useful in designing high responsivity detectors. This study found that a detector has to have a large input impedance conjugately matched to the antenna’s impedance to have high responsivity.

A single-pole double-throw antenna switch integrated with a CMOS power amplifier (PA) and a low-noise amplifier (LNA) by using a three-piece transmission line transformer (TLT) for a frequency-modulated interrupted continuous-wave (FMICW) radar front end is presented. The three-piece TLT consists of a PA output TL, an LNA input TL, and a TL connected to an antenna. Parallel switches and $\lambda$ /4 effective impedance transformers are used to provide high isolation. Due to the effective integration, the chip size and overall insertion loss are reduced significantly. The measured results demonstrate that the proposed switch achieves an insertion loss of 2.2 (2.6) dB with an isolation of 33 (33.4) dB in the antenna-to-LNA input (PA output to antenna) direction. The chip, including the PA, LNA, and switch, for a 79-GHz FMICW radar front end is fabricated in 65-nm CMOS technology, and its size is 0.394 mm2. The PA output power is 10.2 dBm at 79 GHz, and the LNA gain is 15 dB at 79 GHz. FMICW radar waveforms are successfully generated with the switch in this chip. The measured results verify that the proposed device generates an FMICW radar waveform at the switching frequency at 6 kHz.

This letter presents a 28-GHz CMOS linear power amplifier (PA) for 5G beamforming front-end that has dual power modes. The proposed PA consists of parallelly connected cascode cells, which are used to linearize the PA in the high-power mode (HPM). Power modes are implemented by splitting the cascode cells again. To have a low-power mode (LPM), half of the cells are turned off while halving the supply voltage simultaneously. This concurrent change makes it possible to keep the phase of the PA unchanged over two power modes while the dc power consumption is reduced by about half in the LPM. In addition, the good linearity is maintained in the LPM. The PA has gains of 18/14 dB, saturated output powers of 18.5/12.2 dBm, P1dBs of 16.5/10.2 dBm, and peak PAEs of 27.3%/17.8% with a 28-GHz continuous wave (CW) signal. The maximum linear output powers that satisfy EVM $\times100$ -MHz 64-QAM OFDM signal.

A variable-gain low-noise amplifier implemented in a 65-nm CMOS process for a beamforming front-end chip is presented, of which the phase remains constant during gain variations. The phase compensation characteristic is achieved by introducing a shunt PMOS and a parallel resistor at the differential outputs of common-gate (CG) transistors. This allows the gain to be controlled without phase variation by adjustment of the combined gate voltage of the CG transistor and the shunt PMOS at the same time. The proposed device shows a gain of 20.8 dB and a noise figure of 3.71 dB at 31 GHz. It shows a root-mean-square phase error of less than 3° over the gain control range of 10.6 dB at 30–34.5 GHz.

A 17-dB on-/off-ratio modulator operating at 290 GHz that switches resonance frequencies of a transmission line resonator with two varactors is presented for ultrashort-distance communication. The resonance frequency is altered by the control voltage of the varactors. The high on/off ratio can be achieved due to a simple resonance control of a transmission line resonator. High-speed modulation is possible due to a small RC time constant associated with a control voltage node. It is fabricated by using a 65-nm CMOS process with a cutoff frequency of 220 GHz. We demonstrated an insertion loss of 3.49 dB, an on/off ratio of 17 dB, a bandwidth of 28 GHz, and data rates as high as 11.3 Gb/s.

This paper presents a highly linear cascode power amplifier (PA) for 5-GHz 802.11ac (wireless local area network) WLAN applications, which is fabricated with a 0.13- $\mu \text{m}$ standard RF CMOS process. A parallel-cascoded configuration is proposed to cancel out third and fifth intermodulation distortions and third harmonic distortion (HD) due to drain–source current nonlinearity. This also reduces distortions due to drain–source and gate-source nonlinear capacitances at both common source (CS) and common gate (CG) stages. The configuration allows the amplifier linear characteristics to be robust against gate node voltage variations of CG transistors compared to previous multigated transistor linearization methods, because the CG transistors always remain in the saturation region and the nonlinearities of capacitances associated with CG transistors cancel each other under a wide range of output powers. In addition, an active feedback linearizer is applied to improve AM–AM and the power-added efficiency (PAE) at high output powers. At 5.15 GHz, the proposed PA is tested with a 256-quadrature amplitude modulation WLAN 802.11ac signal source without digital predistortions. The output powers satisfying the stringent linearity, a −35-dB error vector magnitude, are 17.8, 17.3, and 15.6 dBm with 11.5%, 10.4%, and 7.5% PAEs at 20, 40, and 80 MHz, respectively.

A dual-mode radio frequency CMOS power amplifier (PA) for Internet of Things application is presented, which is integrated with the other circuits in a 55-nm bulk CMOS process. The low-power mode is achieved by reducing the number of turn-on power transistors, which are also used for linearization. The PA has a gain control scheme that functions by controlling the transconductance ( ${g_{m}}$ ) of the driver stage. A simple body network is introduced to common gate power transistors to improve the linearity of the PA. It is measured with 802.11n 64-quadrature-amplitude-modulation (MCS7) signal and shows a maximum average power of 16 dBm with a supply current of 222 mA under an error-vector-magnitude of −27 dB, which is packaged in a QFN 5 ${\times } \,\, 5$ mm.

This paper presents a CMOS transceiver IC for a single-antenna frequency-modulated continuous wave (FMCW) radar. Since transmitter (Tx) leakage is critical in a single antenna radar with CMOS technology, a comprehensive leakage canceling technique is proposed. It is able to cancel all the leakages caused by antenna reflection, asymmetry of a balanced structure, and lossy substrate without additional power or area. Even-order harmonic leakages from the power amplifier (PA) are also reduced by an even-harmonic filter, which is implemented simply by removing the real ground from the symmetrical point of the PA output transformer. Matching networks are simplified by using a modified coupler structure. A low-noise combining amplifier is used to make the combining circuit compact. As a result, the transceiver achieves the output power of −1.6 dBm, the phase noise of −105.44 dBc/Hz at 1MHz offset, the receiver (Rx) gain of 15.3 dB, and the noise figure of 11.6 dB. Tx leakages are canceled so that the isolation between Tx and Rx is 47.3 dB. The chip consumes 74.1 mA from a 1.5-V power supply. Despite the high integration level, the chip area including pads is 1.7 mm $\times $ 0.9 mm. A $ {K}$ -band FMCW radar module with a single antenna is implemented with this chip.

A dynamic feedback linearizer for an RF CMOS power amplifier (PA) is presented, which consists of a negative feedback network and a dynamic feedback control circuit to inject a reshaped envelope signal to the network. The linearizer compensates for the gain compression of the RF CMOS PA in high-power region by reducing the feedback dynamically, and it also reduces the amplitude-to-phase modulation (AM-PM) distortions. The PA including the linearizer was fabricated using a 0.18- $\mu \text{m}$ RF CMOS process, which has an output transmission-line transformer on a printed circuit board. It delivers an output power of 28.1 dBm at 1.7 GHz with power added efficiency of 40.9%, and adjacent channel leakage ratio (ACLR $_{\mathrm {E-UTRA}}$ ) of under −30 dBc for a 10-MHz 16-QAM long-term evolution signal without digital predistortions.

A 79-GHz variable-gain vector-sum phase shifter is presented, which consists of 5-bit digital attenuators in respective I and Q paths. It is designed to represent any vectors in the entire IQ plane by controlling the digital attenuators with low phase variations. Variable-gain function can be achieved intrinsically without additional variable-gain circuits. The proposed phase shifter can maintain low phase error at high input powers. The phase shifter provides a root mean square (RMS) phase error of 6.74° with a phase resolution of 11.25°. The gain dynamic range and resolution are 21 and 3 dB, respectively, with an RMS gain error of 1.89 dB.

A highly linear and efficient CMOS power amplifier (PA) with adaptive auxiliary amplifier control (AAAC) is presented, which makes the common-gate transistor of an auxiliary amplifier operate in the saturation region for overall output powers. This leads to decrease the AM–PM distortion by reducing the variation of the output susceptance. In addition, the AAAC reduces the current consumption for all power ranges by controlling the auxiliary amplifier. The PA is fully integrated with all matching networks in a 0.18 μm CMOS process. It was measured with an 802.11n 64-QAM MCS7 signal. It achieved a maximum average power of 19.9 dBm with a power-added efficiency of 28% under an error-vector magnitude of −25 dB.

A simultaneous measurement method of the thickness and permittivity of a thin and uniform material which is attached onto the top of a sensor structure is presented. The sensor utilizes the fundamental and harmonic frequencies of a microstrip line ring resonator structure. The thickness and permittivity of a material under test are calculated from two simultaneous equations at the fundamental and second-harmonic frequencies. Fitting equations to calculate the peak resonant frequencies with respect to the thickness and permittivity are also derived. The structure is implemented with a microstrip line on the front side of a TLY-5A substrate and coplanar waveguide access lines on the backside. The permittivity and thickness of the test material are successfully measured simultaneously.

In this paper, on-chip de-embedding methods are compared by applying to transistor characterization for up to 110-GHz. 2-step and 3-step methods, based on lumped circuit models, and hybrid methods, which are a combination of a cascade model and the lumped circuit model, are studied. For cascade models of the hybrid methods, two sets of de-embedding structures are adopted - (LINE, PAD-LINE) and (THRU LR, THRU LLR) are used for the hybrid-1 method and hybrid-2 method, respectively. A single transistor is used as a device under test (DUT) and all de-embedding patterns for the four methods are implemented with 28-nm fully depleted silicon on insulator (FDSOI) process. Transistor characteristics including gate resistance and parasitic capacitances of FDSOI MOSFETs are extracted and analyzed. In addition, ft and f max of the device are estimated by using the hybrid-1 method.

This paper proposes a Ka-band 5-bit switched dual-side microstrip line true-time-delay phase shifter in 28 nm bulk CMOS process. The dual-side microstrip line has vertical arrangements of delay lines and reference lines, which allow implementing compact switched-line phase shifter. The delay cells are implemented with lumped elements which are miniaturized with low self-resonance-frequency inductors. These are very small but have many parasitic capacitances of which resonances are used to make time delays. With these techniques, the proposed TTD phase shifter controls 36.9 ps with the core area of 0.07 mm2. This is the smallest size among the reported Ka-band TTD phase shifters.

A highly efficient 94-GHz push-push frequency doubler is presented. The push-push frequency doubler is implemented with a commercial 65-nm CMOS process and can be operated in high-power mode (HPM) and high-efficiency mode (HEM). In HPM, it shows peak conversion gain of 1.94 dB, operating in the frequency range from 83.6 to 102.9 GHz (20.7%) with the input power of -1 dBm within 3-dB gain variation. Also at 94 GHz, it operates in the input power range of −11.9 to 8 dBm within 3-dB gain variation. In HEM, the peak total efficiency (P OUT /(P DC + P IN )) is 16.28%, which is the highest among those of the reported W-Band frequency doublers.

A wideband W-band 6-bit vector-sum based active phase shifter which was implemented using a 28-nm RF CMOS process is presented. The proposed phase shifter consists of a differential I/Q generator and a vector-summing amplifier with differential input and output buffers to use virtual grounds at high frequencies. The I/Q generator was designed with a differential hybrid coupler structure, and the mismatch in its differential input should be small to obtain accurate I/Q signals. To reduce the differential mismatch at the I/Q generator input, source cross-coupling capacitors are introduced at the common-gate stage of the cascode input buffer. The measured results indicate a root mean square (RMS) gain error of 0.69-0.98 dB and RMS phase error of 6.8-9.3 degrees over a wide frequency range of 76 GHz to 104 GHz. The average peak gain of all 64 states is 3.5 dB at 82 GHz. The fabricated phase shifter has a chip area of 0.32 mm2 with power consumption of 26 mW.

Millimeter-wave beamforming front-end ICs have been studied intensively as the service of 5G wireless communication is scheduled to begin in the near future [1–4]. The ICs include circuit elements such as PAs, LNAs, phase shifters, variable gain blocks, and switches to support antenna arrays for RF/hybrid beamforming. Due to the large number of antennas required for beamforming, the beamforming IC should include as many circuit elements as possible in a chip. The IC also needs high phase- and gain-control resolutions not only for controlling the beams precisely but also for error corrections and calibrations [1]. However, higher-bit controls of the phase and gain as well as high transmitting power increase the chip size in conventional structures, posing a trade-off between them. The front-end IC structure proposed here increases both transmitting power and gain/phase resolutions without increasing either the chip size or the power consumption.

A common-gate (CG) transistor in a cascode power amplifier has a large input capacitance variation in the saturation region with respect to the source voltage. This causes large nonlinearity in a CMOS PA that utilizes a cascode configuration. Here, we propose a method to reduce the capacitance variation by introducing a parallel auxiliary transistor that works in both the saturation and depletion regions by applying a bias voltage that is slightly different from the main one. This provides the proposed CMOS PA a gain of 27.8 dB and an output power of 16.7 dBm with a PAE of 14.7% for an 802.11n modulated signal with an EVM of −25 dB. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:125–128, 2017

A fully integrated RF CMOS front-end (FE) IC (FEIC), which is fabricated with a 0.13- $\mu\text{m}$ bulk RF CMOS process for wireless local area network/Bluetooth (WLAN/BT) applications, is presented. The proposed FEIC includes a dual-mode power amplifier (PA), integrated switches, and a shared low-noise amplifier (LNA) without external matching networks. The proposed compact reconfigurable matching network satisfies the optimum matchings for a multimode PA and a shared LNA. Measurements showed a 16.2-dBm $P_{\mathrm{OUT}}$ , with a 6.7% power-added efficiency (PAE), at −34-dB error vector magnitude, with an 802.11ac signal source, with a high-power-mode WLAN PA. With a low-power-mode BT PA, it showed a 13.7-dBm $P_{\mathrm{OUT}}$ , with a 10.9% PAE, with a 2.1+EDR signal. The shared LNA has a 14.8-dB gain and a 3.6-dB noise figure. All the measurements were carried out, including integrated mode-change switches for time-division duplex operation without any digital predistortion.

A fully integrated transformer-based quasi-Doherty power amplifier (DPA) with an adaptive power divider (APD) is presented in this paper. A novel folded combining transformer is designed for power combining, which has smaller insertion loss than a conventional one. An APD adaptively controls the power delivered to carrier and peaking amplifiers by altering the input impedance of the peaking amplifier, which has a variable resonance frequency that changes according to the input power. Most of the power is delivered to the carrier amplifier at low incoming power, and it is divided between the carrier and the peaking amplifiers at high incoming power. With continuous wave signal at 1850 MHz, the quasi-DPA implemented with an SOI CMOS process achieves 39.8% and 44.4% power-added efficiencies (PAEs) at the first and the second peak, respectively. With wideband code division multiple access signal, it has 29.2-dBm average linear output power and a 40.47% PAE with a −33-dBc adjacent channel leakage ratio 1. With long-term evolution (LTE) signal, it delivers 27.2-dBm average linear output power and a 37.7% PAE, satisfying linearity requirements for the LTE.

A 79-GHz adaptive-gain and low-noise ultra-wideband radar receiver RF front-end integrated circuit in 65-nm CMOS is presented in this paper. The receiver consists of an adaptive-gain low-noise amplifier (AGLNA) and a ${ g}_{ m}$ -boosted sub-harmonic mixer (SHM). The proposed AGLNA controls the gain with adaptive biased circuits, which lowers the gain as the received signal power increases to provide wide dynamic range to the radar receiver without any external controls. We analyzed the input impedance of a cascode amplifier with a parallel resonant inductor, which improves the noise figure. The proposed ${ g}_{ m}$ -boosted SHM uses a transformer-based feedback network with NMOS bleeding circuits to provide a high conversion gain. The SHM was designed to use a differential local oscillator (LO) signal to have a simple structure and operate at low LO power. The measured conversion gain range was from 16 to $-{\hbox{7.5 dB}}$ with a received power range from $-{\hbox{45}}$ to $-{\hbox{5 dBm}}$ at 79.5 GHz. The measured noise figure was 10.5 dB and the measured 2LO-to-RF isolation was 70 dB. The chip area is ${\hbox{0.47}}\times {\hbox{1.23}}~{\hbox{mm}}^{2}$ .

A CMOS common-gate (CG) combining power amplifier is introduced, which has a simple load impedance adaptor. The CG stage of a cascode amplifier consists of a main amplifier with a load impedance adapter and an auxiliary amplifier with a phase compensator, which are biased for classes AB and C, respectively. The proposed configuration not only increases the efficiency of the power amplifier (PA) at back-off powers, but also increases the linearity at high output powers by canceling AM–AM and AM–PM nonlinearities of the main amplifier with those of the auxiliary amplifier. A load impedance adaptor can be used to match two different optimum load impedances of the main and auxiliary amplifiers simultaneously. A phase compensator is introduced to match the output phases of both amplifiers. It has a die size of $0.9 \times 1.63$ mm2 operates at 2.484 GHz with a 3.3 V supply, which is implemented with the 0.18- $\mu \text{m}$ CMOS technology. It shows a linear output power of 22.1 dBm with a PAE of 32% for an 802.11 n signal at error vector magnitude (EVMs) of −25 dB, and it also shows apparent efficiency improvements at back-off powers.

This letter proposes a highly efficient CMOS linear power amplifier (PA) with cascode–cascade configuration. The proposed configuration improves AM–PM distortion through a capacitance variation compensation of the input capacitance of a common-gate stage in the main amplifier and a common-source stage of an auxiliary amplifier. In addition, the current consumption in the low-power region is significantly reduced structurally because the auxiliary amplifier is turned off. The PA is implemented in 0.18- $\mu \text{m}$ CMOS process with an output combining network in printed circuit board. It provides an average power of 24.5 dBm with a PAE of 45.6% for a long-term-evolution 10-MHz up-link signal with the ACLRE–UTRA of −30 dBc at 2 GHz.

A delta-sigma-modulated intermediate-frequency-over-fiber (IFoF) transmission system assisted by a correlative-level coding technique is proposed and experimentally demonstrated. Unlike conventional delta-sigma IFoF systems with multiple output levels to achieve higher signal quality or larger capacity, a correlative-level encoder is exploited as a second modulator preceded by the delta-sigma modulator. The encoder compresses the bandwidth of the delta-sigma modulated signal by creating a correlation between adjacent signal symbols. As a result, the sampling frequency of the delta-sigma modulator in the proposed system can be increased beyond the transmission bandwidth of the IFoF system, considerably improving the in-band signal quality and the transmission capacity over the conventional multi-level approach. This is because the quantization noise from the delta-sigma modulation in the proposed scheme is more aggressively pushed away from the signal bandwidth with the high sampling frequency. According to experimental results, the proposed link provides at least a 40% larger transmission capacity for similar in-band signal quality or 2.1% better average EVM performance for the same capacity than the conventional four-level pulse-amplitude-modulation delta-sigma IFoF systems.