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In a gravity-free or microgravity environment, liquid metals without crystalline nuclei achieve a deep undercooling state. The resulting melts exhibit unique properties, and the research of this phenomenon is critical for exploring new metastable materials. Owing to the rapid crystallization rates of deeply undercooled liquid metal droplets, as well as cost concerns, experimental systems meant for the study of liquid metal specimens usually use low-resolution, high-framerate, high-speed cameras, which result in low-resolution photographs. To facilitate subsequent studies by material scientists, it is necessary to use super-resolution techniques to increase the resolution of these photographs. However, existing super-resolution algorithms cannot quickly and accurately restore the details contained in images of deeply undercooled liquid metal specimens. To address this problem, we propose the single-core multiscale residual network (SCMSRN) algorithm for photographic images of liquid metal specimens. In this model, multiple cascaded filters are used to obtain feature information, and the multiscale features are then fused by a residual network. Compared to existing state-of-the-art artificial neural network super-resolution algorithms, such as SRCNN, VDSR and MSRN, our model was able to achieve higher PSNR and SSIM scores and reduce network size and training time.

We investigate high-throughput, multi-band transmission in a 4-core multi-core fiber (MCF) with the same 125 μm cladding diameter of standard single-mode fiber (SMF). A single wideband comb source is used to transmit up to 561 wavelength channels with 25 GHz spacing over a 120 nm bandwidth in S, C, and L bands. We demonstrate a maximum decoded throughput of 610 Tb/s in PDM-256QAM and PDM-64QAM signals over a 54 km fiber, transmitting more than 155 Tb/s in a single core and measuring a per-core average throughput exceeding record transmission demonstrations in SMF. In addition, we use noise loading measurements to characterize the achievable signal quality across the wideband transmitter. These results show that a single comb source can enable high-spectral efficiency modulation over wide bandwidths and further that low-core count homogeneous MCF technology can offer the same transmission performance as single-mode fibers without sacrificing mechanical reliability, and still offering the benefits of shared resources and greater efficiency that drives SDM technologies.

As multiple functions have been added to single-core-based engine electronic control units (ECUs) in vehicles, automotive researchers and manufacturers have actively studied multi-core architecture for engine ECUs. Multi-core architecture can provide load balancing and parallelism that can meet the requirements of international organization standard (ISO) 26262. However, since real-world engine ECUs have the most complex automotive open system architecture (AUTOSAR)-based control logic and datasets among automotive ECUs, developing multi-core-based engine ECUs is a substantial amount of work. Thus, automotive researchers and manufacturers will need new methodologies for multi-core-based engine ECUs. In this paper, we focus on designing a multi-core migration methodology and applying it to a real-world AUTOSAR-based engine ECU from HYUNDAI. We verify its practicability and enhanced performance. In conclusion, through connection with other automotive domain ECUs, it is demonstrated that a multi-core engine ECU using our migration technology can be applied in real-world automotive vehicles, leading to a significant improvement in performance.

Recent studies on compact and lightweight electronic devices have demonstrated that the LLC resonant converter (LRC) can facilitate achieving high efficiency and high power density. Moreover, employing a planar transformer can further improve the overall system power density. Although the planar transformer can assist in reducing the size of the converter, its high magnetic coupling makes the leakage inductance too small for a resonant inductor in the LRC. Therefore, an extra inductor must be employed separately, leading a considerable decrease in the power density. From this reason, significant research on integrated magnetics has been conducted to combine a transformer and external inductor into a single core. However, they require additional wires or magnetic sheets, and their structures are complex and costly. To overcome these limitations, the integrated magnetics planar transformer (IMPT) for a high power density LRC is proposed in this paper. In the proposed approach, since the primary wire is split into each side leg of the EE-type magnetic core and each operates as a transformer and a resonant inductor alternatively, an external inductor or additional wires are unnecessary. In addition, since the magnetic flux density of the IMPT is approximately equivalent to that of conventional transformer, the core size and the number of turns are almost the same. Therefore, the proposed IMPT features higher efficiency and power density without additional size and costs. To confirm the validity of the proposed IMPT, the operational principles, theoretical analysis, design considerations, and experimental results from a 350 W prototype are presented.

Insulated underground cables have the potential to reduce power outages, maintenance costs, and transmission losses compared to overhead lines. On the other hand, they are exposed to several risks and physical damages, since they are buried in the ground. Though the cables are armoured in order to provide mechanical protection and achieve tensile strength, and also to provide effective conductance of earth fault currents. The main purpose of this paper is to introduce insulated underground cables, armouring process, and to analyze the induced currents in metallic parts such as sheath and armour that causeohmic losses which are categorized mainly in two groups as circulating current and eddy current. This paper presents a review on analytical techniques used to analyze the effect of magnetic fields, andcalculate the losses in the armour of the cables, besides providing the strategies and solutions used for armour loss reduction.

RISC-V has been experiencing explosive growth since its first appearance in 2011. Dozens of free and open cores developed based on this instruction set architecture have been released, and RISC-V based devices optimized for specific applications such as the IoT and wearables, embedded systems, AI, and virtual, augmented reality are emerging. As the RISC-V cores are being used in various fields, the demand for multicore platforms composed of RISC-V cores is also rapidly increasing. Although there are various RISC-V cores developed for each specific application, and it seems possible to pick them up to create the most optimized multicore for the target application, unfortunately it is very difficult to realize this in reality. This is mainly because most open cores are released in the form of a single core without cache coherence logic, which requires expensive design effort and development costs to address it. To tackle this issue, this paper proposes a method to solve the cache coherence problem without additional effort from the developer and to maximize the performance of the multicore composed of the RISC-V core selected by the developer. Along with a description of the sophisticated operating mechanisms of the proposed method, this paper details the architecture and hardware implementation of the proposed method. Experiments conducted through the prototype development of a RISC-V multicore platform involving the proposed architecture and development of an application running on the platform demonstrate the effectiveness of the proposed method.

The growing share of medium voltage cable lines in distribution networks challenges distribution network operators in terms of proper mode of operation of these lines. It is related to the reduction of energy losses in cable conductors and metallic cable screens. The article focuses on energy losses in metallic cable screens of cable lines and substation busbar bridges composed of single-core cables with metallic screens and possible ways of their reduction. Simulation and measurement analysis of the level of energy losses in the metallic screens of cables is presented together with the economic analysis of various variants of losses reduction through the change of the way these screens are operated in relation to the traditional bilateral earthing at both ends of cable. Technical problems and threats connected with the use of considered modifications of metallic screens operation during earth fault disturbances in distribution networks are also presented

Single nanowire memory units are of particular interest in the design of high-density nanoelectronic circuits, but the performance due to weak contact state remains a major problem. In this paper, bonding between core/shell SiC/SiO2 nanowire and Au electrodes can be improved via local contact engineering with femtosecond (fs) laser irradiation. An optimized heterojunction (Au-SiO2-SiC) is possible since plasmonic enhanced optical absorption can be localized at the metal-oxide (Au-SiO2) interface. Electron transport across the barrier and charge accumulation at the oxide-semiconductor (SiO2-SiC) interface are improved in nanowire circuits. A fast and stable resistance change can be achieved after only one biasing cycle ('write') and the written state can be read/extracted at a low voltage (∼ 0.5 V). Unlike other as-built nanowire circuits, the resistance state can be retained for 10 min in the absence of external power, indicating that these devices can be used for short-term memory units. High current tolerance is also provided in the circuit by the surface oxide shell which acts to protect the inner SiC core. The current density carried by the single SiC/SiO2 nanowire circuit can be as high as ∼3 × 106 A cm-2 before break down, and that breakdown occurs as a two-stage process.

As the need for on-device machine learning is increasing recently, embedded devices tend to be equipped with heterogeneous processors that include a multi-core CPU, a GPU, and/or a DNN accelerator called a Neural Processing Unit (NPU). In the scheduling of multiple deep learning (DL) applications in such embedded devices, there are several technical challenges. First, a task can be mapped onto a single core or any number of available cores. So we need to consider various possible configurations of CPU cores. Second, embedded devices usually apply Dynamic Voltage and Frequency Scaling (DVFS) to reduce energy consumption at run-time. We need to consider the effect of DVFS in the profiling of task execution times. Third, to avoid overheat condition, it is recommended to limit the core utilization. Lastly, some cores will be shut-down at run-time if core utilization is not high enough, in case the hot-plugging option is turned on. In this paper, we propose a scheduling technique based on Genetic Algorithm to run DL applications on heterogeneous processors, considering all those issues. First, we aim to optimize the throughput of a single deep learning application. Next, we aim to find the Pareto optimal scheduling of multiple DL applications in terms of the response time of each DL application and overall energy consumption under the given throughput constraints of DL applications. The proposed technique is verified with real DL networks running on two embedded devices, Galaxy S9 and HiKey970.

The reduction of the overall budget of the project leads to the cost effective one and there should besuch criteria of reduction of the cost in different manner. To make economic structure without losing the stiffnesscriteria, the work has been performed in two stages. The former one is building with single shear wall core andthe latter one is building with dual core shear wall; the entire work has performed with four different phases. Infirst phase total 5 buildings that are modeled with different openings in single core types shear wall and thensecond phase performs the analysis procedures of the same. The third phases have total 6 buildings that aremodeled with different openings in dual core types shear wall and then fourth phase performs the analysisprocedures of the same. The result analysis has been performed and then conclusions are drawn. Building with25% opening area in single core type shear wall and 50% opening area in dual core type shear wall performswell to reduce the cost of the project.

Motivation Fast, lightweight methods for comparing the sequence of ever larger assembled genomes from ever growing databases are increasingly needed in the era of accurate long reads and pan-genome initiatives. Matching statistics is a popular method for computing whole-genome phylogenies and for detecting structural rearrangements between two genomes, since it is amenable to fast implementations that require a minimal setup of data structures. However, current implementations use a single core, take too much memory to represent the result, and do not provide efficient ways to analyze the output in order to explore local similarities between the sequences. Results We develop practical tools for computing matching statistics between large-scale strings, and for analyzing its values, faster and using less memory than the state-of-the-art. Specifically, we design a parallel algorithm for shared-memory machines that computes matching statistics 30 times faster with 48 cores in the cases that are most difficult to parallelize. We design a lossy compression scheme that shrinks the matching statistics array to a bitvector that takes from 0.8 to 0.2 bits per character, depending on the dataset and on the value of a threshold, and that achieves 0.04 bits per character in some variants. And we provide efficient implementations of range-maximum and range-sum queries that take a few tens of milliseconds while operating on our compact representations, and that allow computing key local statistics about the similarity between two strings. Our toolkit makes construction, storage and analysis of matching statistics arrays practical for multiple pairs of the largest genomes available today, possibly enabling new applications in comparative genomics. Availability and implementation Our C/C++ code is available at https://github.com/odenas/indexed_ms under GPL-3.0. The data underlying this article are available in NCBI Genome at https://www.ncbi.nlm.nih.gov/genome and in the International Genome Sample Resource (IGSR) at https://www.internationalgenome.org. Supplementary information Supplementary data are available at Bioinformatics online.

With the development and progress of automobile industry, the automobile electronic control system has put forward higher and higher requirements to the controller. From the realization of the controller to vehicle test, all need hardware in loop test, and ensure the real test results of core is to run in real-time processor on the real-time operating system, at the same time with a single core processor in the operation of the real-time system bottlenecks, this paper USES the multi-core processor platform to build real-time problems of real-time system research. The Linux system is studied in this paper after the defects in real time, this paper proposes a by adding preemption patch solution to realize real- time Linux system, at the same time, using the advantages of multi-core processors, the CPU resources of real-time and non- real-time tasks are divided, and the number of interrupts on the CPU where the real-time task is located is reduced. Finally, a specific RTOS development case based on the PREEMPT_RT patch is given, and on this basis, the effectiveness of the proposed scheme in the real-time performance of the system is verified.

This work presents a current-mode inverse Class-D digital PA (DPA) with enhanced power back-off (PBO) efficiency. The PA adopts extra switches, which allows the scaling in the output voltage swing by half, leading to (theoretically) 6 dB enhancement in PBO efficiency while maintaining (ideally) 100% drain efficiency (DE). Implemented in a 65 nm CMOS, the proposed DPA shows the improvement in DE by ×1.5 at 4.2 dB PBO in comparison with normalized Class-B PA while requiring only one transformer and single-supply voltage.

With the development of long-distance large-capacity DC power transmission technology, and the advantage of the integrated energy pipeline simultaneously transmits electric energy and LNG, high-temperature superconducting(HTS) cable plays an important role in energy pipeline carrier because of its advantages of zero resistance, high efficiency transmission and cooling capacity sharing. HTS cables work in liquid nitrogen, and HTS cables can realize the cold energy sharing of transmission fuel and electricity. Therefore, it is necessary to analyze the current carrying capacity of HTS cable based on the research of energy pipeline. In this paper, two different structures of HTS cable, coaxial bipolar and single core bipolar cable core, are analyzed by electromagnetic simulation. According to the anisotropy of each superconducting material, the influence of magnetic field on the critical current of different structures is analyzed. In order to verify the accuracy of this design, a HTS DC cable with rated current of 1000A at 90K is completed, and the relevant data parameters are given. Finally, a series of current carrying capacity tests were carried out on the HTS DC current sample, including the critical current test under different temperature, the temperature rise of the inner and outer layers of the cable core. The test results and current carrying capacity were analyzed.

We experimentally demonstrate four-wave mixing (FWM) in a triple-core microstructure fiber for a pump wavelength of 1064 nm. We study the transition between the case where FWM happens primarily in a single core and the case where FWM is distributed among multiple cores. The effective nonlinear coefficient is reduced by a factor of 3 (the number of cores) for distributed-core FWM compared with that for single-core FWM. This effect also leads to a three-fold reduction in the FWM bandwidth for distributed-core FWM. We report on the wavelength and polarization dependence of the core-to-core coupling length, and how those phenomena produce power-dependent coupling among the cores. These are the first reported experimental measurements of FWM in a 3-core microstructure fiber providing critical information for their use as nonlinear optical devices.

For decades now, thermal rise has been spotted as one of the major constraints of performance for high-end safety-critical processors. In this context, Dynamic Voltage and Frequency Scaling () based solutions have proven to be effective to manage the chip temperature. In this paper, we consider the scheduling problem of non-preemptive periodic tasks on a single-core processor with DVFS-enabled capabilities under thermal-aware design. We assume that the tasks are scheduled by following any Fixed-Task-Priority (FTP) scheduler such as the traditional Rate Monotonic (RM) and Deadline Monotonic (DM). Then, we propose a new scheduling scheme, referred to as NP-COIN, which makes it possible to control both the processor activity and the triggering of the cooling mechanism with as little impact on performance as possible. We provide a thorough theoretical analysis of our solution, in terms of average temperature gain and timing penalty, against the classical schedule. Finally, we validate our theoretical results and assess the performance of our solution through a real-world use-case study from the avionics domain and through intensive simulations by using synthetic test cases.

In recent days, the developments in automobiles are a tremendous one. Especially, in the cars, the developments are increasing day by day. Initially, the operations of the car are using manual one but now various features are incorporated and moving towards the autonomous driving mode. For all these developments and working a control unit is needed to operate properly which is called Electronic control units in an automobile. These ECUs are different for different operations. The ECUs are increasing in parallel along with the developments in the car. But, the more number of ECUs implementations results in a high overhead communication and device is large in nature. To minimize the ECUs as well as to perform the operations effectively the core concept is introduced. In the core, the more no of electronic control units are replaced by runnable and it is operated in a real-time operating system. The single core effectively operated but when a high priority operation or interrupt occurs it performance reduces due to the single core architecture. To improve the performance of device a migration of single core architecture to multicore architecture takes place. The multicore architecture provides a parallel execution of different tasks along with the interrupts without any interventions. Several algorithms like First in First out, Round robin, etc., were introduced to improve the scheduling of operations. All these concepts were based on the task periods or priority. Hence to improve and provide a better scheduling algorithm this paper introduced an optimization concept based on the utilization factor using the Satin Bowerbird algorithm. The performance is analysed through the controller wait time and utilization time.

This paper presents an advanced technique for the differential protection of single core phase shifting transformers. The proposed technique is based on sensing electrical signals without sensing tap position. Only terminals currents are sensed by using two current transformers (CTs) per phase unlike other methods that need more CTs. Other methods use at least four transducers per phase and, in addition, sense the tap changer position, which increases the cost of the protection system. The proposed technique is based on the analysis of magnetically coupled and metallically connected circuits. The excitation winding currents are calculated to represent input currents to the differential protection relay. Tap changer position is estimated according to the phase shift between sources currents. The technique is checked for various types of shunt faults inside and outside the protection zone. The results prove the relay sensitivity and stability for internal and external faults, respectively. The effects of inrush current, series winding and CTs saturation are taken into consideration.

Advanced-computing demand has grown exponentially over the past several decades [1], [2]. Figure 1 reports computing feature trends, such as number of logic cores, operational frequency, power consumption, system performance measured in terms of the Standard Performance Evaluation Corporation integer (SPECint), and the number of transistors in the processor. The number of transistors, either in a single core or in multiple cores, and the operating frequency have increased to keep up with this demand. However, the typical power, which is indicated by the red cluster dots, has remained relatively constant.

This paper presents kNN STreaming Unit For Fpgas (kNN-STUFF), a modular, scalable and efficient Hardware/Software implementation of k-Nearest Neighbors (kNN) classifier targeting System on Chip (SoC) devices. It takes advantage of custom accelerators, implemented on the reconfigurable fabric of the SoC device, to perform most of the classifier's workload, whereas the processor coordinates the accelerators and runs the remaining workload of the kNN algorithm. kNN-STUFF offers a highly flexible framework, where the designer has the possibility to define the number of parallel instances of the classifier and the parallelism within each instance. This capability allows creating the most suitable implementation for a target device of any size. Results show that kNN-STUFF, with 24 accelerators, attains performance improvements up to 67.4×, when compared to an optimized (-O3) software-only implementation of the kNN running on a single core of the ARM Cortex-A9 CPU. Furthermore, its energy efficiency improvements are as high as 50.6×.

This paper details a hydrodynamic model based on Blade Element Momentum Theory (BEMT) developed to assess ’conventional’ 3-bladed tidal stream turbines (TSTs), adapted here to analyse an ’unconventional’ case of a ducted and open centre device. Validations against a more detailed coupled Reynolds averaged computational fluid dynamics (RANS-BEM) model shows excellent agreement, of within 2% up to the peak power condition, with associated computational times in the order of a few minutes on a single core. The paper demonstrates the application of hydrodynamic forces into a structural analysis tool, in order to assess blade stress distributions of a generic hubless turbine. Incorporation of parameters such as non-uniform inflows and blade weight forces are investigated, with their effects on stress profiles presented. Key findings include: i) the adapted BEMT model replicates the majority of turbine performance characteristics estimated through previous CFD assessments; ii) the proposed model reduces the computational effort by several orders of magnitude compared to the reference coupled CFD, making it suitable for engineering assessments iii) blade stress distribution profiles are quantified, detailing concentration zones and cyclic values for use in fatigue analyses. This work forms part of a greater project aimed to develop a suite of analytical tools to perform engineering assessments of bi-directional ducted TSTs.

A previously proposed high step-up dc–dc converter based on Z -source circuit is improved such that conduction losses of the converter and current stress of its power switch are reduced. The improved converter contains only one magnetic core and all of the inductors are coupled. It is shown that using one core allows us to use windings with lower copper resistance that results in reducing resistive losses of the coupled inductors. Also, by rearranging two diodes of the converter, the switch current and its conduction loss are reduced. In addition, a previously proposed auxiliary circuit for zero-voltage-transition operation is employed with a minor modification that makes it possible to use a relatively large snubber capacitor that significantly decreases current–voltage overlap of the main switch at turn-off instant. Improvement in the overall efficiency of the presented structure over the existing high step-up Z -source converter is demonstrated by implementing a 100-W prototype of each converter for 30- to 300-V voltage conversion.

The massively parallel computing systems composed of many processors are connected on chips, which will become more and more complex and unreliable. This paper presents an error-tolerant design based on the autonomous error-tolerant (AET) architecture that aims to have a self-repairing capability. A nearby error sensing mechanism is designed to discover faults, and an active evolution scheme is studied to handle unrecoverable errors. A circuit backup switching mechanism is proposed to bypass the failed nodes. The board-level prototype is implemented based on dual-core embedded processors. The analysis shows that the error-tolerant capability of the proposed architecture is better than the conventional multimodular redundant system when the failure rate of a single core is less than 0.7. In the AET test system consisting of 16 processors, the error-tolerant capability is verified. The results show that the relative variation of the overall performance of the AET system will not be changed due to the high reliability requirements of the system. Through experimental comparison, under the premise that the architecture of AET and the triple modular redundancy method are basically consistent in reliability, whether on the logical-level error tolerant or on the physical-level error tolerant, the former has lower power consumption.

Automated fruit inspection using cameras involves the analysis of a collection of views of the same fruit obtained by rotating a fruit while it is transported. Conventionally, each view is analyzed independently. However, in order to get a global score of the fruit quality, it is necessary to match the defects between adjacent views to prevent counting them more than once and assert that the whole surface has been examined. To accomplish this goal, this paper estimates the 3D rotation undergone by the fruit using a single camera. A 3D model of the fruit geometry is needed to estimate the rotation. This paper proposes to model the fruit shape as a 3D spheroid. The spheroid size and pose in each view is estimated from the silhouettes of all views. Once the geometric model has been fitted, a single 3D rotation for each view transition is estimated. Once all rotations have been estimated, it is possible to use them to propagate defects to neighbor views or to even build a topographic map of the whole fruit surface, thus opening the possibility to analyze a single image (the map) instead of a collection of individual views. A large effort was made to make this method as fast as possible. Execution times are under 0.5 ms to estimate each 3D rotation on a standard I7 CPU using a single core.

Coarse Grained Reconfigurable Arrays (CGRAs) are emerging as energy efficient accelerators providing a high grade of flexibility in both academia and industry. However, with the recent advancements in algorithms and performance requirements of applications, supporting only integer and logical arithmetic limits the interest of classical/traditional CGRAs. In this paper, we propose a novel CGRA architecture and associated compilation flow supporting both integer and floating-point computations for energy efficient acceleration of DSP applications. Experimental results show that the proposed accelerator achieves a maximum of 4.61× speedup compared to a DSP optimized, ultra low power RISC-V based CPU while executing seizure detection, a representative of wide range of EEG signal processing applications with an area overhead of 1.9×. The proposed CGRA achieves a maximum of 6.5× energy efficiency compared to the single core CPU. While comparing the execution with the multi-core CPU with 8 cores, the proposed CGRA achieves up to 4.4× energy gain.

The number of electronic control units employed in automobiles increases as the functions of automobiles diversify in response to demands for improved convenience and stability. Furthermore, the complexity and size of software loaded on controllers are increasing. As the number and types of software to be reprogrammed increase, the time to reprogram a vehicle also increases. In this paper, we propose an efficient method to store software in flash memory using the multicore function when reprogramming the electronic control unit. This method can efficiently transfer data from RAM to flash memory using two cores alternately. As part of this study, an experiment was performed using an embedded system, and the data transfer time was compared with that required when storing software in flash memory using only one core. The results of this comparison demonstrate that the proposed method can optimize memory usage during reprogramming.

16 pags., 9 figs., 1 tab., A new methodology to completely characterize active multicore waveguides is proposed. The method is applied to two-core waveguides written in an Er3+/Yb3+ co-doped phosphate glass by femtosecond laser inscription. Determination of the core diameter and refractive index variation is based on asymmetric excitation of the dual core waveguide and measurements of the intensity output distribution. Moreover, a single core waveguide has also been written for characterization purposes and signal enhancement measurements carried out on it have allowed the determination of the glass active properties. Finally, enhancement measurements on the two-core waveguides for different pump powers and core-to-core separations have been performed, together with simulations of the experiments using the parameters determined in the characterization procedure. The good agreement between measurements and simulations supports the validity of the characterization method presented. The proposed characterization technique is suitable for any multicore symmetric structure regardless the fabrication method and the number of cores, allowing the benefits of multi-core fibre designs to be transferred to integrated active structures., This work was supported in part by the Spanish Ministry of Science and Innovation under Grant PID2019-108598GB-I00 and Project, in part by the Department of Industry and Innovation (Government of Aragon) through the research group under Grant E44-20R (cofinanciando con Feder 2014-2020: Construyendo Europa desde Aragón), in part by the National Research under Grant UDiSON (TEC2017-82464-R) from the Spanish Research Agency (AEI, Ministry of Research and Innovation), and in part by the European Regional Development Fund (ERDF), as well as the Consejo Superior de Investigaciones Científicas through the “intramural” Project under Grant 201850E057 is simi- larly acknowledged. (Corresponding author: Juan A. Vallés)

In this paper the sequence impedances of an existing HVAC insulated cable, protected by a steel reinforced concrete structure, are estimated. The paper aims at investigating if the presence of metallic protective structures significantly affects the sequence impedances of the line. The present analyses are carried out by applying both the multiconductor cell analysis and the finite element method in order to model the HVAC line with and without protective structure. The results arising from the use of the different modelling approaches are compared.

We model the application of multicore optical fibers for submarine systems using an approach to estimate relative cost/bit. While multicore fibers may offer higher capacity, achieving lower cost/bit than single core fiber systems remains challenging.

This paper explores adding support to SwiftVis2, a plotting library written in Scala, for compiling and running across the JVM, web browsers, and native compiled code. We find that it is possible to use a single core library written in standard Scala across these various compile targets with little additional code. The quality of the output and ability to handle large datasets varies significantly for different implementations. The use of Scala, or other languages that have compilers targeting multiple platforms, makes it possible to easily target many platforms with relatively little effort.

As vehicles added many functions, the number and complexity of the controllers are increasing. Because of the complexity of software increasing, the CPU load on a single core based controller reaches its limits. To overcome the limitations of the single-core-based controller, a multicore based controller has been introduced. One of the problems encountered when converting software from a single-core-based controller to a multicore-based controller's software is scheduling. This paper proposes an algorithm for generating offset considering the period, execution time, and priority of controller software's internal tasks. This algorithm's offset allows you to reduce the maximum load on the controller among the measured loads every specific period. This period equals the period of task with the highest CPU load. We simulated the HMC engine electronic control unit (ECU) software with the Timing Architects Tool Suite (TA) tool. And using Hardware In the Loop Simulation (HILS), the offset was applied to the ECU of the HMC. Also, we verify the reduction of peak load among the loads measured every specific period that is the same as the task's period with the highest CPU load by offsets generated.

A side-polished fiber-fiber directional coupler was fabricated using a four-core fiber with the standard cladding diameter. Coupling ratio of >99% and excess loss of

The NDN Forwarding Deamon (NFD) has been a reference forwarder implementation of Named Data Networking. Its good modularity and extensibility make it easy to experiment with new ideas, but it shows limited forwarding performance even with multi-core CPUs because its forwarding structure uses only single core. We present the Multi-Worker NFD (MW-NFD), an NFD-compatible NDN forwarder with parallel forwarding capability on multi-core CPUs. Since the NFD's forwarding architecture is maintained as is, MW-NFD inherits the advantages (modularity and extensibility) of NFD, and it is fully compatible with NFD and existing NDN applications. In this demo, we shows that MW-NFD can yield high forwarding performance, about 13 times higher than NFD's performance.

The need for the enhancement of channel capacity of optical fiber, space division multiplexing (SDM) transmission fibers- such as the multicore fiber, the multimode fiber and the few-mode multicore fiber, etc., - have been researched for long-distance communication system. In this paper, a special type of homogeneous multicore fiber structure is introduced and the array of holes is placed between each core. The normalized propagation constant, mode field diameter (MFD) of LP 01 mode of this structure are studied here. The empirical relation between normalized propagation constant and V number of LP 01 mode of a single core single-mode fiber is compared with simulation results of LP 01 mode of a multicore fiber. The mode field diameter of MCF is derived by noting the beam radius where the intensity drops to 1/e2 of the intensity on the beam axis. The theoretical prediction match well with COMSOL results. These results are useful for the investigation of the detailed characteristics of different types of MCF.

We report on the first, to the best of our knowledge, implementation of a fluorine co-doped large-mode-area REPUSIL fiber for high peak power amplification in an ultrashort-pulse master oscillator power amplifier. The core material of the investigated step-index fiber with high Yb-doping level, 52 µm core and high core-to-clad ratio of 1:4.2 was fabricated by means of the REPUSIL powder-sinter technology. The core numerical aperture was adjusted by fluorine codoping to 0.088. For achieving high beam quality and for ensuring a monolithic seed path, the LMA fiber is locally tapered. We demonstrate an Yb fiber amplifier with near-diffraction-limited beam quality of M 2 = 1.3 , which remains constant up to a peak power of 2 MW. This is a record for a tapered single core fiber.

Guiding system reform and further innovation of embedded technology development under the background of the mathematical modeling is analyzed in the paper. In our research, we have the following novelties. (1) Industrial modularization is basis of the industrial integration, which refines the enterprise, organization and target object in the value chain into a subsystem that can then run independently. (2) System processing primary functions are no longer concentrated on the single core processor, but are shared by multiple processors based on functional classification to then from a single core to multiple cores. (3) The data mining and mathematical modelling are combined to then construct the efficient system. Based on the proposed model, we then propose the suggestions for the guiding system reform and further innovation.

International audience; Near infrared (NIR) activable photopolymers suitable for versatile fabrication of micro-optical elements were developed. The first main objective of this paper is to show that these new photopolymers can be used for microfabrication and investigate the parameters governing the microfabrication process. The impact of photonic, physico-chemical and chemical parameters is discussed. High quality microstructures with a good control over their size and shape are demonstrated. The second main objective is to show practical examples of microlenses and waveguides implemented on single core and multiple core optical fibers, VCSELs, and glass slides are then presented. The NIR photosensitivity of this negative tone photoresists allows using the device source itself as to start the crosslinking process, which constitutes a convenient approach for micro-optics self-positioning on NIR sources and justifies the interest of such NIR photopolymer for the fabrication micro-optical elements and optical interconnects. 2

Spatial Division Multiplexing (SDM) could potentially address optical density and cable capacity challenges in data center and subsea networks. In co-packaged optics, the multicore fiber (MCF) offers up to 3X higher density than regular fiber solution; In long haul submarine networks, however, single core fiber based SDM solution will provide overall lower cost per bit than MCF.

Recent progress on ultra-high capacity, space division multiplexed optical transmission is reviewed. The highest capacity of 10.16 Pbit/s has been achieved by using 19 core 6 mode fiber, and the highest capacity of 402.7 Tbit/s for multimode single core fiber has been demonstrated by using weakly-coupled 10 mode fiber with a standard cladding diameter.

Laser shock surface treatment applications, ie with plasma formation, require pulses of very high peak power and duration of the order of a few tens of nanoseconds. This processing technique are generally performed in free space due to the difficulties to inject such peak power in a single core fiber. We present a innovative method allowing to inject 500 mJ pulses at 1064 nm in a single core multimode fiber. This subsystem allows at once to secure the input interface of the fiber and to reduce the optical losses due to Brillouin scattering.

Interleaved boost converter has been widely used due to its current sharing characteristics and reduced input current ripple with reduced inductor size. To further improve the power density of the converter, coupled inductors are employed. This paper analyzes the operation of high gain switched capacitor interleaved boost converter with coupled inductor configuration. The coupled inductor configurations discussed are easy to implement with standard available cores. The converter is operated in Zone I, which corresponds to the highest gain and the converter possesses inherent current sharing among different phases. The coupled inductors are loosely coupled in order to keep the input as well as inductor current ripple low and to reduce the size keeping the efficiency same or more. The proposed integrated magnetics design is validated through a 2kW 4-phase hardware prototype. The net inductor volume, in case of coupled inductor with single core is reduced by 36% while the efficiency at rated power increases by 0.2% compared to non-coupled inductor configuration. Also, it is shown that the net inductor volume can be reduced upto 56% in case of coupled inductor with same results as compared to non-coupled inductors.

Convolutional neural networks (CNNs) require high throughput hardware accelerators for real time applications owing to their huge computational cost. Most traditional CNN accelerators rely on single core, linear processing elements (PEs) in conjunction with 1D dataflows for accelerating convolution operations. This limits the maximum achievable ratio of peak throughput per PE count to unity. Most of the past works optimize their dataflows to attain close to a 100% hardware utilization to reach this ratio. In this paper, we introduce a high throughput, multi-threaded, log-based PE core. The designed core provides a 200% increase in peak throughput per PE count while only incurring a 6% increase in area overhead compared to a single, linear multiplier PE core with same output bit precision. We also present a 2D weight broadcast dataflow which exploits the multi-threaded nature of the PE cores to achieve a high hardware utilization per layer for various CNNs. The entire architecture, which we refer to as NeuroMAX, is implemented on Xilinx Zynq 7020 SoC at 200 MHz processing clock. Detailed analysis is performed on throughput, hardware utilization, area and power breakdown, and latency to show performance improvement compared to previous FPGA and ASIC designs., Comment: To be published in ICCAD 2020

The paper deals with the sequence impedances (positive/negative and zero sequences) of high- and extra-high-voltage land single-core insulated cables. In particular, it presents the comparisons between sequence impedance measurements and computations. The computations of the sequence impedances are carried out by means of the most important international normative and council references (IEC/Cigr&eacute, ) and of multiconductor cell analysis which is a consolidated and powerful tool developed by University of Padova in order to analyse power frequency regimes of multiconductor asymmetric power systems. The comparisons are presented with reference to four high- and extra-high voltage insulated cables, even if the available ones are much higher: however, the conclusions derived from these four reference cases are general and can be useful for transmission system operators and for power electric system engineers involved in insulated cables. The paper demonstrates, for the first time in technical literature, that direct formulae cannot correctly evaluate the sequence impedances of installed single-core land cable systems. Extensive on-field measurement campaigns have served to this purpose.

Existing simulation methods cannot provide functionally and temporally correct simulations for the cyber-side of automotive systems since they do not correctly model temporal behaviours such as varying execution times and task preemptions. To address such limitations, our previous work proposes a novel simulation technique that guarantees the functional and temporal simulation correctness. However, the simulation technique is designed assuming a single core simulator. In this work, we extend the single core simulator targeting a multicore simulator to enhance the simulation capacity. In this multicore extension, a major challenge is the inter-core interferences in a multicore environment, which causes unpredictability of simulated job execution times, which in turn makes it hard to model the timings of the real cyber-side of an automotive system. To overcome the challenge, this paper empirically analyzes the inter-core interferences for typical automotive workloads and proposes a practical multicore extension approach, which can still provide a functionally and temporally correct simulation, without using complex inter-core isolation mechanisms. Our experimental study shows that the proposed multicore extension approach can significantly improve the simulation capacity over the previous single core simulator while still preserving simulation correctness.

Coaxial cable telemetry is most commonly used in the field of underwater applications like data logging in oil rigs, underwater wireless modem, underwater acoustic measurements, borehole measurements, deep sea telemetry for sediment analysis, airborne sonars, imaging sonars etc. In all the above applications coaxial multicore cables are used. The design and development of relay based coupling scheme which helps to replace the multi core cable with a single core coaxial cable for telemetry application is described. Single core cable is suitable for long distance data communication. Multi core cables are generally heavy and due to the size, may not meet space constraints in complex systems. They are not economical too. The relay based coupling scheme is used to mix or separate the high speed bi-directional communication data, high voltage DC and high power pulsed AC. In single relay scheme one relay is used to switch the centre core of single core coaxial cable. Here the ground is common for both high power AC transmission and high speed bi-directional data path. A dual relay scheme is discussed where two relays are used to switch both the centre core and ground of the single core coaxial cable. This provides more ground isolation and can avoid ground lifting issues while high power AC transmission occurs. The simulation of the coupling scheme was done using PSpice®. A prototype of the coupling scheme was also made for analysis. Filter responses were analysed for each coupling path. The DC coupling filter has 85 Hz cut-off frequency at -3 dB. The cut-off frequency of high speed data coupler is 500 KHz at -3 dB. A 4.3KV peak to peak of 3 KHz and 7 KHz AC signals were transmitted and measurements were taken to analyse the effect of high voltage over different coupling paths. The 3 KHz signal has a peak of 61.88 dB and that of 7 KHz signal, the peak is 62.50 dB. The signal components of 3 KHz signal in the DC path has a voltage level of 9.375 dB and that of 7 KHz signal is 25.63 dB.

Shared tree multicast uses a single core to handle entire multicast traffic load in a domain. In this paper, we present a new multicast approach with multiple cores to reduce the traffic load. Main objective of our present work is to create a group-to-core mapping table a priori, i.e. even before a multicast session begins; it is done immediately after the network is booted. To the best of our knowledge, there does not exist any such multicast architecture for PIM SM related to load sharing. We select statically a set of k primary cores for possible load share with complexity O(n2). This selection is done immediately after the network is booted. At the same time, we create statically k partitions on all possible multicast addresses. The ith partition maps to the ith core in the list of k cores – this means that any new multicast session with multicast group address belonging to the ith partition will use the ith core from the list of k cores to implement PIM SM. In addition, we have incorporated fault tolerance in our approach to tackle the problem of any number of primary core failures.

Cables intended to interconnect offshore wind farms with the mainland are currently treated as separate lead-type cables by IEC 60287. A single core equivalent thermal model (SCETM) is implied, that is, a thermal model accounting for 1-D (radial) heat transfer only. While this approach is expected to be reasonable when smaller cables are rated, the 1-D representation is less valid in larger cable sizes. This paper uses 2-D finite-element models to reveal certain weak points of the representation of the thermal resistances in the existing SCETM. For constant losses, the IEC SCETM seems to underestimate the temperature by up to 8 °C. Suitable replacement formulae are proposed that could improve the accuracy of the SCETM. Finally, the issue of nonsolid fillers is considered and modelling guidelines are given.

In recent years, many applications have started using serverless computing platforms primarily due to the ease of deployment and cost efficiency they offer. However, the existing scheduling mechanisms of serverless platforms fall short in catering to the unique characteristics of such applications: burstiness, short and variable execution times, statelessness and use of a single core. Specifically, the existing mechanisms fall short in meeting the requirements generated due to the combined effect of these characteristics: scheduling at a scale of millions of function invocations per second while achieving predictable performance. In this paper, we argue for a cluster-level centralized and core-granular scheduler for serverless functions. By maintaining a global view of the cluster resources, the centralized approach eliminates queue imbalances while the core granularity reduces interference; together these properties enable reduced performance variability. We expect such a scheduler to increase the adoption of serverless computing platforms by various latency and throughput sensitive applications.

A push&ndash, push transformer-based oscillator (TBO) adopting a power leakage suppression technique has been proposed. The proposed technique reduces the power loss due to unwanted leakage path without additional DC power consumption, hence improving the output power and DC-to-RF efficiency. The measured output power of the proposed single core oscillator is &minus, 4.5 dBm at 270 GHz with 2.1% DC-to-RF efficiency.

Modern microprocessors are more vulnerable to transient faults or soft errors than ever before due to design trends mandating low supply voltage and reduced noise margins, shrinking feature sizes and increased transistor density for fast, low-power circuits. As industry now supports Hardware Transactional Memory (HTM), the features of HTM can be leveraged to add core resiliency to transient errors. In this paper, we propose a novel microarchitecture for transient error detection and recovery based on time redundancy and backward error recovery leveraging HTM's existing features especially its rollback mechanism. We provide implementation details for single-core reliability, minimizing additions to existing HTM supports. We evaluate the performance overheads of the single core with the reliability feature by comparing it to the base machine without the reliability feature. Finally we show how single-core reliability can be extended to multi-core reliability.