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This paper presents a novel spiking neural network (SNN) classifier architecture for enabling always-on artificial intelligent (AI) functions, such as keyword spotting (KWS) and visual wake-up, in ultra-low-power internet-of-things (IoT) devices. Such always-on hardware tends to dominate the power efficiency of an IoT device and therefore it is paramount to minimize its power dissipation. A key observation is that the input signal to always-on hardware is typically sparse in time. This is a great opportunity that a SNN classifier can leverage because the switching activity and the power consumption of SNN hardware can scale with spike rate. To leverage this scalability, the proposed SNN classifier architecture employs event-driven architecture, especially fine-grained clock generation and gating and fine-grained power gating, to obtain very low static power dissipation. The prototype is fabricated in 65 nm CMOS and occupies an area of 1.99 mm2. At 0.52 V supply voltage, it consumes 75 nW at no input activity and less than 300 nW at 100% input activity. It still maintains competitive inference accuracy for KWS and other always-on classification workloads. The prototype achieved a power consumption reduction of over three orders of magnitude compared to the state-of-the-art for SNN hardware and of about 2.3X compared to the state-of-the-art KWS hardware.

In this paper, we examine the feasibility of FPGA as a platform for training a convolutional binary-weight neural network. Training a neural network requires more data movement compared to inference. Acceleration of training on an FPGA is, therefore, a challenge because the data movement increases off-chip memory accesses. We try to address this problem by storing most of the data in the on-chip memory and adopting batch renormalization. This allows for training a large network by reducing the required intermediate data and its movement. For the case where all data except the input images can be stored on an FPGA chip, we present an accelerator for training CNNs to classify the CIFAR-10 dataset. Further, we study the impact of network size on performance and energy of FPGA and GPU. Our accelerator mapped in the Arria 10 FPGA chip obtains up-to 9.33X higher energy efficiency compared to the Nvidia Geforce GTX 1080 Ti GPU at similar performance.

We present a sub-µW Neural Spike Processor integrated with a Power Management Unit (PMU) for on-implant processing in motor intention decoding, demonstrating: (i) among the highest level of integration including spike detection, feature extraction, sorting, the first half of decoding, which reduces wireless data rate by more than 4 orders of magnitude; (ii) on-chip PMU integration enabling the system directly powered by harvesters; (iii) the lowest power dissipation of 0.78µW for 96 channels, 21x lower than the prior art at a comparable/better accuracy.

Today's microprocessors and Systems-on-Chip are thermally limited. Many, therefore, employ dynamic thermal management (DTM) to maximize performance under a reliability constraint. Accurate thermal monitoring is critical as temperature underestimation can hurt reliability by excessively aging devices and overestimation can hurt performance by unnecessarily throttling computing components. Placing temperature sensors close to potential hotspots can help accuracy, but it is non-trivial as hotspots often form inside digital blocks consisting of densely placed digital cells. Large sensors can disrupt cell placement thereby increasing wire lengths and circuit delays. Furthermore, the sensor needs to operate from the same digital power grid as the circuit, one that can be scaled down to near-threshold regime via dynamic voltage scaling. Absent this ability, a separate power grid and dedicated supply voltage for the sensors further increases area overhead. In this paper, we present a sensor circuit that is compact and deeply voltage-scalable and can be embedded among digital cells with little disruption. Simulation results show that it achieves a comparable accuracy to other compact sensor circuits for DTM.

This paper presents analysis and evaluation of the impact of size and voltage scalability of on-chip temperature sensor on the accuracy of hotspot monitoring and temperature estimation in dynamic thermal management of high performance microprocessors. The analysis is based on both the layout level and the system level across state-of-the-art sensors in terms of accuracy, voltage-scalability, and silicon footprint. Our analysis shows that a sensor having compact footprint and good voltage scalability can be placed on exact hotspot locations, typically among digital cells, significantly improving accuracy in tracking hotspots and estimating temperature of microarchitecture blocks, as compared to two other sensors that have higher sensor-circuit accuracy, large footprint and little voltage scalability limiting flexible placement.

Conventional radiography with film (CRF) has been in use for diagnostic purposes for a long time now. It has proved to be a great assert for the radiographers in assessing various abnormalities. With recent advances in technology it is now possible to have digital solutions for radiography problems at a very cost effective, environment friendly and also with better image quality in certain applications when compared to CRF. Rather than using a CRF a computed radiography (CR) uses imaging plates to capture the image. The imaging plate contains photosensitive phosphors which contain the latent image. Later this plate is introduced into a reader which is then converted into a digital image. The major advantage and the cost effective element of this system is the ability to reuse the imaging plates unlike the photographic film where in only a single image can be captured and cannot be reused. The computed radiography drastically reduces the cost by eliminating the use of chemicals like film developers and fixers and also the need for a storage room. It also helps to reduce the costs that are involved in the disposal of wastes due to conventional radiography. This paper investigates whether it is cost effective to use computed radiography over film based system at Al-Batnan Medical Center (BMC), Tobruk, Libya by using Cost Benefit Analysis (CBA). Apart from the initial cost of the CR System, based on the data collected from the center, from the year 2008 to 2012 (until June 2012) a total of 581,566 images were produced with the total cost incurred using film based system being USD 4,652,528. If the same number of images were produced using a CR system the total cost incurred would have been USD 82,600. Taking into consideration the cost of a new CR system to be USD 120,000 the overall cost of producing these images is USD 202,600. It is observed that an amount of USD 4,449,928 could have been saved over the period of 5 years starting from 2008 to 2012 by using the CR system at BMC. Using Cost Benefit Analysis, the average value of the net difference between the costs and benefits for the conventional film based system is ?83.38 where as for the Computed System it is 22.06. Based on the principles of Cost Benefit Analysis it can be concluded that the system with a net positive difference is more cost beneficial than the other. With the help of the above two analysis it can be concluded that the use of computed radiography is definitely more cost effective for use at BMC, when compared to the conventional x-ray radiography.