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Editor’s note: Semiconductor industry is steadily on the quest for emerging devices and device technologies that lead to higher performance and higher efficiency of computing over CMOS technology. This tutorial introduces the potential of emerging devices that integrate ferroelectric material into digital as well as analog circuits. With a focus on FeFET technology, the authors first present device characteristics, and advantages in comparison to CMOS but also other emerging technologies such as RRAM. The article comprehensively demonstrates the use of FeFET technology in circuits, architectures, and applications.— Jurgen Teich, FAU Erlangen

A metal ion threshold switch (MITS) based on an Ag/TiN/HfO2/Pt stack is experimentally demonstrated with improved endurance. The incorporation of a low-temperature atomic layer deposition (ALD) TiN layer as an efficient diffusion barrier enables optimum Ag infiltration during the electroforming step. Further, the tunability of the threshold voltage (VTS) from 0.25 to 1.1V via bottom electrode (BE) work function engineering is demonstrated. The Ag/TiN/HfO2/Al MITS selector exhibits a 4.4x increase in VTS, $100~\mu \text{A}$ ON-current handling capability, low leakage (~10 pA), $10^{{7}}$ half-bias non-linearity and fast (

In this work, we exploit the spatio-temporal switching dynamics of ferroelectric polarization to realize an energy-efficient, and massively-parallel in-memory computational primitive for at-node sensor data fusion and analytics based on an industrial 28nm HKMG FeFET technology [1]. We demonstrate: (i) the spatio-temporal dynamics of polarization switching in HfO 2 -based ferroelectrics under the stimuli of sub-coercive voltage pulses using experiments and phase-field modeling; (ii) an inherent rectifying conductance accumulation characteristic in FeFET with a large dynamic range of $G_{\max}/G_{\min} > 100$ in the case of 3.0V, 50ns gate pulses; (iii) transition to more abrupt accumulation characteristics due to single/few domain polarization switching in scaled FeFET (34nm L G ); and (iv) successful detection of physiological anomalies from realworld multi-modal sensor data streams.

While continuing the CMOS scaling-down becomes unprecedentedly more challenging than before, intensive exploration on beyond-CMOS nanodevice technologies is an appealing approach to further continue the power scaling-down. This chapter reviews some promising beyond-CMOS emerging transistor technologies, including Tunnel FETs, Ferroelectric FETs, and Hyper-FETs. Circuit design techniques based on these emerging devices are also reviewed to provide insights for future energy-efficient analog and digital signal processing. In addition to the opportunities, this chapter also discusses the challenges of emerging devices in circuit and systems.

In this work, we demonstrate a novel Hybrid-FeFET (H-FeFET) that leverages the threshold switching characteristics of Ag/HfO 2 to overcome the fundamental trade-off between memory window MW /read current ratio (I read,1 /I read,0 ) , and program voltage (V prog )/maximum electric-field in standard FeFETs for non-volatile memory application. The H-FeFET incorporates the threshold switch (TS) in the source of the FeFET, and is designed to exhibit a ferroelectric state-dependent volatile HRS to LRS transition (I ON /I OFF >107) – during read, the TS turns ON only if the FeFET is in the low-V T SET state, and remains OFF if the FeFET is in the high-V T RESET state, thus, selectively suppressing the RESET read current. Leveraging this principle, the H-FeFET: a Demonstrates 77% higher MW and 1000× larger I read,1 /I read,0 compared to the FeFET, at iso-V prog (DC); (b) Enables 25% reduction in V prog at iso-I read,1 /I read,0 during pulse operation-facilitated by the 8× improvement in I read,1 /I read,0 ; (c) Exhibits 2.5×reduction in programming power at iso-I read,1 /I read,0 in the H-FeFET-based AND array architecture, as shown by simulations. Thus, the H-FeFET overcomes the FeFET design challenges while retaining its existing advantages, making it a promising candidate for nonvolatile memory applications.

In this work we develop a compact model of ferroelectric field-effect-transistors (FeFET) for memory applications, enabling their exploration at the circuit and architecture level. In contrast to Landau-Khalatnikov (L-K) based approaches, the presented model is founded on the combination of a nucleation dominated multi-domain Presiach theory of ferroelectric switching with a conventional transistor model. The model successfully reproduces the evolution of the FeFET memory window as a function of the program and erase conditions (amplitude, pulse width, and history). To calibrate the model, we fabricated 10nm thick Hf 0.4 Zr 0.6 O 2 (HZO) MFM capacitors and FeFETs and characterized the polarization switching dynamics. Our results highlight the importance of accounting for the switching history, minor loop trajectory, and coupled time-voltage response of the ferroelectric to quantitatively reproduce the measured FeFET characteristics.

Electrically induced phase transitions are being investigated for applications in steep-slope transistors, neuromorphic computing, and coupled oscillator networks. Here, we present an avenue to integrate a layered 2D phase transition material 1T-TaS 2 with monolayer MoS 2 via direct synthesis. We experimentally demonstrate that the charge density wave (CDW) based phase transition is preserved when grown directly on MoS 2 , however a 42% reduction in the ON/OFF ratio compared to exfoliated devices is observed. First principles calculations of the 1T-TaS 2 /MoS 2 heterostructure reveal a 39% reduction in the bandgap of 1T-TaS 2 compared to the free-standing 1T-TaS 2 case.

In this paper, we consider devices, circuits, and systems comprised of transistors with integrated ferroelectrics. Said structures are actively being considered by various semiconductor manufacturers as they can address a large and unique design space. Transistors with integrated ferroelectrics could (i) enable a better switch (i.e., offer steeper subthreshold swings), (ii) are CMOS compatible, (iii) have multiple operating modes (i.e., I-V characteristics can also enable compact, 1-transistor, non-volatile storage elements, as well as analog synaptic behavior), and (iv) have been experimentally demonstrated (i.e., with respect. to all of the aforementioned operating modes). These device level characteristics offer unique opportunities at the circuit, architectural, and system-level, and are considered here from device, circuit/architecture, and foundry-level perspectives.

Random number generators (RNG) are a fundamental hardware component in modern cryptographic systems [1]. The generation of random numbers can be subdivided into two classes, pseudo-RNGs and hardware RNGs. In pseudo-RNGs software algorithms are implemented on deterministic hardware but are dependent on a set of initial values or “seed”, which reduces the security. In contrast, hardware RNGs generate random numbers from a naturally occurring physical phenomenon, such as thermal noise. However, implementations often suffer from large silicon footprints due to the need to create resistor-amplifier-ADC chains [2] or bias removal circuits [3]. In this work, we experimentally demonstrate a compact and scalable 1T1R based RNG by harnessing the inherent stochasticity in the insulator-to-metal phase transition (IMT) in vanadium dioxide (VO 2 ).

Two-dimensional materials are being investigated for potential nanoelectronic applications such as transistors for scaled technology nodes. Here we investigate the possibility of further augmenting the performance of such 2D materials through a novel device concept known as the hybrid-phase transition FET or Phase-FET. The MoS 2 based Phase-FET incorporates an insulator-to-metal transition material VO 2 integrated in series with the source of a MOSFET, which provides an internal amplification across the insulator-to-metal transition and results in steep slope switching.

We demonstrate a novel Ag/HfO 2 based threshold switch (TS) with a selectivity∼107, a high ON-state current (Ion) of 100 μA, and ∼10pA leakage current. The thresholding characteristics of the TS result from electrically triggered spontaneous formation and rupture of an Ag filament which acts an interstitial dopant in the HfO2 insulating matrix. Further, we harness the extreme non-linearity of the TS in (1) Selectors for Phase Change Memory (PCM) based cross-point memory. We show through array level simulations of a 1024kb memory, a read margin of 28% and write margin of 32% for a leakage power of ds ), and >10x Ion improvement over the conventional FET (at iso-I off ) at T=90C (50x at T=25C); making this a promising TS for both emerging memory, and steep-slope transistor applications.

Coupled oscillators provide an efficient non-Boolean paradigm for solving a variety of computationally intensive problems in computer vision. This motivates the realization of large networks of low-power coupled oscillators. In this work, we experimentally demonstrate: (i) a relaxation oscillator based on the insulator-metal transition (IMT) in vanadium dioxide (VO 2 ) with record low DC input (peak) power of ∼23 µW; (ii) a network of coupled VO 2 oscillators with record number of elements (6 oscillators) which perform image processing functionalities in high dimensional space like color detection and morphological operations such as dilation and erosion). Calibrated simulations show that 10× reduction in power compared to a 32 nm CMOS accelerator at iso-throughput.

Insulator-metal transitions (IMTs) are the subject of intense fundamental and applied research including their potential applications in electronic devices like coupled relaxation oscillators [1], neuromorphic devices [2], Phase FETs [3], and RF switches [4]. A key requirement for practical device application of IMT materials is that the IMT temperature (IWr) should be greater than 358 K (85C) which is the operating temperature of electronic chips (Fig. 1). In this work, we investigate the electrically induced IMT in epitaxially grown 0.3% tensile strained Ca 2 RuO 4 thin films wherein strain engineering increases the transition temperature (Timt) to more than 550K from a bulk value of ∼357K (ΔΤ I μT >190K). Using systematic DC and transient I-V measurements, we show that the origin of the electrically induced IMT in Ca 2 RuO 4 is current induced self-heating.

Vanadium dioxide (VO 2 ), which exhibits electrically induced abrupt insulator-to-metal phase transition (IMT), is monolithically integrated with Silicon MOSFET to demonstrate a steep-slope (sub-kT/q) Phase-Transition FET (Phase-FET). The Phase-FET exhibits switching-slope (SS) of 8mV/decade leading to 36% increase in ON current (I ON ) over baseline MOSFET. We analyze the electrical characteristics of several threshold-switching materials with enhanced resistivity ratios (>105) beyond VO 2 and harness them to enhance the performance of 14nm node FinFETs. Our analysis shows that up to 2.9× increase in I ON , and 1.86× reduction in energy at (iso-delay) for an 11 stage ring oscillator (RO) is achievable with Phase FETs using Cu-doped HfO 2 threshold switches.

The switching dynamics of electrically driven insulator-to-metal transition (IMT) and metal-to-insulator transition (MIT) in vanadium dioxide are investigated. The transient response of time domain measurements are modeled using a domain based 2-D heterogeneous resistive network, taking into account local electronic potential and local Joule heating. It reveals, the switching time is dominated by a spatially non-uniform percolation of the metallic phase during the IMT driven by electro-thermal forces. We demonstrate an IMT switching time of 793ps in scaled VO 2 devices and project IMT and MIT switching speed for scaled devices.

Dense analog synaptic crossbar arrays are a promising candidate for neuromorphic hardware accelerators due to the ability to mitigate data movement by performing in-situ vector-matrix products and weight updates within the storage array itself. However, many analog weight storage cells suffer from long latencies or low dynamic ranges, limiting the achievable performance. In this work, we demonstrate that the voltage-controlled partial polarization switching dynamics in ferroelectric-field-effect transistors (FeFET) can be harnessed to enable a 32 state non-volatile analog synaptic weight cell with large dynamic range (67×) and low latency weight updates (50 ns) for an amplitude modulated pulse scheme.

An electrically triggered VO2 RF switch with a record switching cut off frequency (FCO) of 26.5THz was demonstrated. The switch exhibits an isolation better than 35dB and a low 0.5dB insertion loss up-to 50GHz. The switch features a highly linear response with 1-dB compression point (PidB) better than 12dBm and output third-order intercept point (OIP3) better than 44dBm. The fast insulator to metal-transition (IMT) of the VO2 enables the switch to have an electrical-turn on delay of less than 25ns.