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This article aims to align business strategy and knowledge creation in banking industry through knowledge management (KM) approach by maximizing the tangible and intangible resources. Prior study offered more general context of KM approach while misplaced and less discussed practical process of knowledge sharing practices in the context of banking industry. We developed research model by focusing on banking organization, especially in a developing country. The authors use literature review and document analysis of business strategy in bank. This article integrated and analyzed knowledge gap and business strategy to develop a comprehensive approach for banking company. The gap between what a bank knows and needs to know is an internal knowledge gap, in a sense representing the strengths and weaknesses of a “the alignment between knowledge–business” analysis. The gap between what they know and what its competitors know is an external knowledge gap. It represents the opportunities and threats of a knowledge–business analysis. In addition, there is still no specific team, department, and strategy to manage knowledge assets. The results of this research may help finance companies and managers to initiate KM or to encourage knowledge sharing in banking organization. Therefore, managerial level is supposed to develop a strategy and regulation to encourage employee's participation in knowledge transfer schema. We combined numerous methods and theories namely Zack and Nonaka models as tools to solve the obstacle of alignment between business-knowledge strategic gap and knowledge sharing schema.

The continuity strategy of business innovation to deal with the disruption condition, it is still many to be designed and explained. Referring to a sociotechnical systems (STSs) approach, this article conceptualizes and practically examines the business analytics, virtual business, and knowledge absorptive capacity that increase and produce the continuity capability of business innovation in uncertain business environment (e.g., COVID-19). We used SmartPLS to empirically evaluate the model based on 145 companies in a developing country of Indonesia that is currently under high disruption. Drawing a technical perspective, business analytics has successfully enhanced business continuity innovation and knowledge absorptive capacity. In a socio perspective, knowledge absorptive capacity significantly produces business continuity innovation. Business continuity innovation suffers if firms adopt virtual business without increasing their knowledge capabilities. Furthermore, mediating effects present higher support from management level to knowledge absorptive capacity strategy, a bigger impact for business analytics, and virtual business to improve and increase the goals opportunities of business continuity innovation. A novel contribution is the integration of STSs (business analytics, virtual business, and knowledge absorptive capacity) that drives business continuity innovation to deal and recover from uncertain environment. Our efforts also align several fields such as information technology-business alignment strategy, knowledge management, and knowledge-business services. Future research would be worthwhile and interesting whether our framework will suitable to different companies/respondents, business context, industry area, and crisis condition.

Novel ESD compact modeling methodology using machine learning techniques is proposed for the first time in this paper. ESD compact modeling for snapback and non-snapback ESD protection devices are discussed. Comparisons between conventional, novel fitting methodology and different machine learning models are discussed. The advantages of this novel methodology are introduced and methods to further improve the model accuracy are also discussed.

Meng Miao,1 Fang Yuan,2 Xiaotian Ma,3 Haiming Yang,1 Xiang Gao,1 Zhengyu Zhu,4 Jianzhong Bi4 1Department of Neurology, Qilu Hospital (Qingdao), Cheeloo College of Medicine, Shandong University, Qingdao, Shandong, 266035, People’s Republic of China; 2Department of Health Care, Qilu Hospital (Qingdao), Cheeloo College of Medicine, Shandong University, Qingdao, Shandong, 266035, People’s Republic of China; 3Department of Medicine Experimental Center, Qilu Hospital (Qingdao), Cheeloo College of Medicine, Shandong University, Qingdao, Shandong, 266035, People’s Republic of China; 4Department of Neurology, The Second Hospital, Cheeloo College of Medicine, Shandong University, Jinan, Shandong, 250033, People’s Republic of ChinaCorrespondence: Zhengyu Zhu; Jianzhong BiDepartment of Neurology, The Second Hospital, Cheeloo College of Medicine, Shandong University, Jinan, Shandong, 250033, People’s Republic of ChinaTel +8617660083488; +8615153178111Email zhuzhengyu_1@hotmail.com; bjz@sdu.edu.cnBackground: Early cognitive impairment after transient ischemic stroke (TIA)/mild ischemic stroke (MIS) is common but easily overlooked. It has been demonstrated that DNA methylation plays a significant role in cognitive impairment and ischemic stroke. Furthermore, it has been reported that the RIN3 gene influences transportation of the amyloid β-protein. However, to our knowledge, there has been no research related to correlations between RIN3 methylation and early-onset cognitive impairment after TIA/MIS. Therefore, this study aimed to investigate this relationship in TIA/MIS patients.Methods: This study include 28 control subjects and 84 patients with TIA/MIS who were evaluated within 7 days of TIA/MIS onset using four single-domain cognitive scales. In addition, DNA methylation of whole blood was tested. RIN3 methylation was compared between TIA/MIS and control groups and between TIA/MIS patients with early cognitive impairment and those without early cognitive impairment. Clinical variables and RIN3 methylation sites with statistical differences were then used to construct a predictive model.Results: Hypomethylation of the RIN3 gene was observed in the whole blood of TIA/MIS patients relative to healthy controls. Furthermore, patients with early cognitive impairment after TIA/MIS had hypomethylation of RIN3 relative to those without early cognitive impairment.Conclusion: RIN3 methylation is strongly associated with TIA/MIS and TIA/MIS with early cognitive impairment. It is possible to influence the disease process by methylation via appropriate lifestyle and clinical interventions, and methylation of RIN3 gene sites may predict the occurrence of TIA/MIS with early cognitive impairment.Keywords: amyloid &Bgr;-protein, cognitive impairment, hypomethylation, ischemic stroke, transportation

This paper documents the emergence of a large bank loan market in the absence of contracting institutions: the trusted assistant loan market in 19th century China. These loans were legally unenforceable, one-shot loans to poor scholars that funded the costs of assuming lucrative administrative appointments offering ample opportunities for corruption. The trusted assistant loan’s distinguishing feature was a legally unenforceable stipulation that the borrower incorporate an agent of the creditor into his administrative cadre. We model the enforcement of these loans through expertise leverage and test the model’s predictions using data from officials’ diaries and a bank loan book. JEL classifications:G21, O16, D86

Diode trigger SCR (DTSCR) structure is introduced in FinFET technology for low voltage circuit ESD protection. The current direction is chosen to flow vertically down through the fins to make full use of the bulk silicon region. Further optimization of DTSCR is investigated to improve layout efficiency.

We demonstrate the negative impact of air pollution on China’s Initial Public Offering review process. We find that the pass rate of firms with connection to the review committee is increased by 10 percentage points when reviewed on a polluted day. The effect only exists for air pollution during working hours and pollutants near the workplace of the reviewers. The result is unchanged when using the wind speed as an instrumental variable and when controlling for a variety of potential missing factors. Using LDA (Latent Dirichlet Allocation) model, we show that the reviewers intentionally ask trivial questions during the review, supporting the idea that the committee members become more reckless during hazy days. This effect translates to an economic loss amounting to RMB 200 billion (USD 33 billion).

A predictive ESD TCAD deck including the workflow is developed for the 12nm FinFET technology. ESD failure in the I/O FET and ESDNFET is analyzed through TCAD simulation with calibrated silicon fin dimension-dependent thermal conductivity.

The downsizing of CMOS technology into the decananometer range has called for the redesign of the ESD protection devices because of the constraints of lower operation voltage and smaller breakdown voltage of the ultrathin gate oxide. In this work, we had developed a two-dimensional diode-triggered silicon-controlled rectifier (TD-DTSCR) structure to cope with the narrowed ESD design window in the 28 nm CMOS technology. A sufficient large SCR trigger voltage was obtained by directing the triggering current to both longitude and lateral directions, through two parasitic diodes and the P-Well, so as to save the chip area for realization. Optimization was done by varying several device parameters and the best ESD robustness obtained was 53.7 mA/μm which was about 65% larger than that of a simple SCR with the same width of 30 μm and realized using the same technology. Failure analysis was also conducted to identify the possible weak spots of the proposed structure.

The study aimed to explore the reliability and validity of the Sub-Health Measurement Scale version 1.0 (SHMS v1.0) for the assessment of the suboptimal health status (SHS) of Tianjin residents. This was a cross-sectional study that surveyed 2640 urban residents in Tianjin from June 2016 to January 2018. Demographic and clinical characteristics were collected. Each subject completed the SHMS v1.0 and Short Form-36 (SF-36) scale assessments. The retest coefficient was 0.675. The overall Cronbach's α coefficient was 0.921. The correlation between SHMS v1.0 and SF-36 was 0.781 (P 25 years old (P = .009), bachelor degree or above (P 10 hours (P 9 (P

Thermal runaway is one of the main causes of semiconductor device failure under electrostatic discharge (ESD) stresses. An experimental method to investigate the failure temperature under such electrical stresses is proposed. By extrapolating the power-to-failure under different stress time versus ambient temperature curves to the temperature axis, an effective failure temperature is extracted which represents the real failure temperature. This temperature is observed to be higher than the temperature at which the semiconductor becomes intrinsic. The latter is conventionally regarded as the critical temperature for thermal failure. These findings suggest that a different thermal-related mechanism is responsible for the ESD-induced damage in semiconductor devices.

The aim of the present study was investigate the association of the severity of emphysema of patients with chronic obstructive pulmonary disease (COPD) with airway inflammation and the COPD-specific comorbidity test (COTE) index. A total of 94 patients with COPD were divided into four groups according to the severity of their emphysema; in each patient, comorbidities were recorded and inflammatory biomarkers, including MMP-9 and TIMP-1 were determined in circulating blood. The unbalanced proportion of MMP-9 and its inhibitor, TIMP-1, led to the airway inflammation and lung remodeling in the patients with COPD. A total of 80.85% of the patients had emphysema of different degrees. The quantity of male patients and the smoking index in the three emphysema groups were significantly higher than those in the non-emphysema group (F=7.67 and 5.42, P3 comorbidities, a COTE index of ≥4 and cardiovascular disease as well as coronary heart disease (t=6.40, 2.53, 3.65 and 2.90, P

We present an ESD P-direction STI diode fabricated in an advanced bulk FinFET technology. The impact on process and design parameters are evaluated in detail. With design optimization, the ESD P-direction STI diode achieves 46% and 16% performance improvement for It2/C and It2/Area relative to the C-direction design.

Silicon nitride (SiN) metal-insulator-metal capacitors (MIMCAPs) are components of most GaAs and GaN integrated circuits and integrated passive devices (IPD). To analyze the dielectric breakdown mechanisms and predict the lifetime of SiN MIMCAPs under electrostatic discharge (ESD) conditions, characteristics of MIMCAPs with different dimensions (dielectric thickness and area) and various ambient temperatures under ESD stresses are investigated. Measurements are conducted using the Barth 4002 transmission line pulse (TLP) system and the Signatone S1060 heating module. Then, the breakdown voltage variation of MIMCAPs with respect to dimensions and temperatures under different types of transmission line pulsing (TLP) stresses is discussed. Furthermore, with the transformative version of power law employed, the lifetime (time dependent dielectric breakdown, TDDB) of MIMCAPs is analyzed.

Background/aim: This study performed typing of chronic obstructive pulmonary disease (COPD) using high-resolution computedtomography (HRCT) to determine the association with smoking, matrix metalloproteinases, and common comorbidities.Materials and methods: The study enrolled 94 hospitalized patients. Participants were divided into a group of 69 current and formersmokers (group A) and a group of 25 that had never smoked (group B). Patients were also divided into 3 categories according to thedegree of emphysema and bronchial wall thickness using HRCT to determine the association with levels of matrix metalloproteinase 9(MMP-9) and TIMP-1, as well as associated comorbidities. These three categories were: type A - no or mild emphysema, with or withoutbronchial wall thickening; type E - emphysema without bronchial wall thickening; and type M - both emphysema and bronchial wallthickening.Results: The low attenuation area (LAA) scores in group A patients were higher than those in group B (t = 2.86, P < 0.01); correlationanalysis showed that smoking was associated with a decline of the forced expiratory volume in 1 s and forced vital capacity ratio (FEV1/FVC%) and higher LAA scores in patients with COPD (F = 4.46, F = 8.20, P < 0.05). The levels of MMP-9 in group A were higherthan those in group B (t = 3.65, P < 0.01). Among COPD patients with more than 3 comorbidities, there were statistically significantdifferences in both the smoking group and the nonsmoking group (chi-square = 12.08, P < 0.01). When compared to type A patients,who had coincident cardiovascular diseases in the smoking group, patients of type M and E showed statistically significant differences(F = 2.42 and 2.12, P < 0.05).Conclusion: Emphysema was more severe in smokers. Metalloproteinase levels in smokers were higher than those in nonsmokers.Moreover, comorbidities were more severe in smokers.

Background MicroRNAs (miRNAs) are short, noncoding RNAs that inhibit the expression of target genes that play roles in tumorigenesis. MiR-21, miR-31, and miR-184 are oncogenic miRNAs for head and neck squamous cell carcinoma (HNSCC). Factor-inhibiting hypoxia (FIH)-inducible factor is known to inactivate hypoxia-induced downstream effectors and is involved in HNSCC suppression. This study investigates whether miR-21, miR-31, and miR-184 target FIH in HNSCC. Methods Reporter assays, Western blot analysis, quantitative reverse transcriptase-polymerase chain reaction (PCR) analysis, and phenotypic assays were used to prove that miR-21, miR-31, and miR-184 directly target FIH. Clinicopathological implications of the gene expression were also analyzed. Results MiR-21, miR-31, and miR-184 directly bind to various sites in the 3′ untranslated region (UTR) of FIH transcript, and this binding is associated with decreased FIH protein expression in HNSCC cells. Treatment with the precursors of these miRNAs increases the proliferation and migration of HNSCC cells. Concomitant treatment with precursors repressed FIH and enhanced oncogenicity most profoundly. Upregulation of miR-21, miR-31, and miR-184 expression is found in more than 80% of HNSCC tumors and 72% of tumors have concordant upregulation of these 3 oncogenic miRNAs. The highest expression of these miRNAs is present in T4b and stage IVB tumors. Downregulation of FIH mRNA expression is noted in 69% of HNSCC tumors, and in tumors exhibiting high expression of these miRNAs, the FIH mRNA expression is consistently downregulated. Conclusion This study provides novel clues indicating that miR-21, miR-31, and miR-184 co-target FIH tumor suppressor during pathogenesis in the vast majority of HNSCC. © 2014 Wiley Periodicals, Inc. Head Neck, 2015

This paper reviews the physical mechanisms and compact modeling approaches of two physical damages in MOS devices induced by electrostatic discharge (ESD) stresses; namely gate oxide breakdown and thermal failures. Theories underlying the failure mechanism are discussed and compact models that can be used to monitor ESD induced gate oxide breakdown and thermal failure are developed. Related work reported in the literature is discussed, and benchmarking of measurement data versus simulation results are included in support of the modeling work.

This chapter presents the design of CMOS UWB tunable sub-nanosecond impulse and monocycle-pulse BPSK transmitters. The UWB impulse transmitter produces positive and negative tunable impulse signals corresponding to the high- and low-level modulation signals, respectively. The positive and negative impulse signals have amplitudes of 0.8 and 0.6 V with tunable pulse widths from 100 to 300 ps, respectively. The UWB monocycle-pulse transmitter produces monocycle pulse signals of opposite polarities having peak-to-peak amplitudes of about 0.6–0.8 V and tunable pulse widths between 100 and 300 ps. This chapter also covers the design of the CMOS impulse generator and BPSK modulator used in the UWB impulse and monocycle-pulse transmitters. The impulse generator can generate 0.95–1.05 V peak-to-peak Gaussian-type impulse signal with 100–300 ps tunable pulse duration. Moreover, this chapter includes the design of a CMOS monocycle pulse generator, which can produce 0.7–0.75 V peak-to-peak monocycle pulse with 140–350-ps tunable pulse duration.

This paper considers lending to finance projects in a setting where repayment enforcement appears impossible. The loan was illegal and thus legally unenforceable. Creditors were incapable of applying private coercion to force repayment. Borrowers lacked both collateral and reputation capital. Project cash flows were unobservable. The projects were the acquisition of Imperial administrative posts by scholars in nineteenth century Qing China. The lending mechanism was the “trusted-assistant loan.” Our model of trusted-assistant lending shows that it is a renegotiation-proof implementation of efficient state dependent financing. Empirical analysis of officials’ diaries and bank records shows that the employment of trusted-assistant lending and the performance of trusted-assistant loans conforms roughly with the model’s predictions.

Electrostatic discharge (ESD) devices based on diodes and silicon controlled rectifier for RF I/O protection are evaluated on both ESD and RF performance. Varying from the architecture, layout design and metal interconnection, candidate devices show different parasitic capacitance, ESD efficiency, and turn on speed. Potential solution for further RF I/O application is verified.

Transient characteristics of vertical GaN diodes fabricated on bulk GaN substrates are investigated. When forward biasing the diodes using discrete pulses, the results yield quasi-static I-V curves with two different on-resistances and two turn-on stages. Transient waveforms measured at different voltages are then used to explain the observed behavior and underlying physics. A relatively large overshoot voltage is also observed at the very beginning of the transient voltage waveform, indicating that a relatively long time is required to transition the GaN diode from the high to low resistance state.

In this paper, characteristics of electrostatic discharge (ESD) protection devices operating under ESD stress and various ambient temperatures are investigated. The devices considered are a P +/NW diode and several silicon controlled rectifiers (SCRs) including Lateral SCR (LSCR), Modified Lateral SCR (MLSCR), No Snapback SCR (NS-SCR), Low Voltage Triggering SCR (LVTSCR), and P-Substrate Triggered SCR (PSTSCR) fabricated in a 0.35 μm BCD (Bipolar-CMOS-DMOS) technology. Measurements are conducted using the Barth 4002 transmission line pulse (TLP) tester and the Signatone S1060 heating module, and the TLP I–V characteristics are analyzed in details. TCAD simulation is carried out and underlying physical mechanisms related to the effect of temperature on key ESD parameters are provided.

Design trade-offs of a novel structure embedded with a silicon controlled rectifier and dual-diode (DD-SCR) for high speed I/O applications are presented. A metal-bounded DD-SCR exhibiting a high failure current (It2), small on-state resistance (Ron), low voltage overshoot and low parasitic capacitance is introduced as an optimal device for such applications in advanced CMOS processes. Comprehensive characterizations including capacitance and current vs. voltage measured using transmission line pulsing (TLP) and very-fast TLP (VFTLP) are undertaken to demonstrate the DD-SCR performance.

A novel power-clamp assisted complementary MOSFET (PCACMOS), modified from traditional gate-coupled complementary MOSFET (GCCMOS), is proposed for high robust ESD (Electrostatic discharge) protection application. The power-clamp achieves by RC-NMOS and designs by Spice simulation. The comprehensive performance of the protection schemes are evaluated by the figure of merit (FOM). Compared with traditional gate-coupled MOSFET (GCCMOS) protection scheme, the power-clamp assisted complementary MOSFET (PCACMOS) protection scheme has a similar turn-on speed but higher FOM.

A novel gate-suppression technique derived from source-pumping technique is proposed for Electrostatic Discharge (ESD) protection application. By employing the complementary SCR structure, an improved source-pumping and the gate-suppression scheme are able to extend ESD window and endure a high level of ESD impact without additional layout area cost. The fast rise time TLP test revealed the gate-suppression technique provide more effective protection than the source-pumping technique.

Experiments with ZnO Metal-Oxide-Semiconductor （MOS） under different circumstances were made to get four different I-V curves. There were four conditions: dark, and tests with the green, blue, ultraviolet LED light. According to references, three parameters B，VB0and Nbarrcould be acquired by fitting lines of the I-V curves using MATLAB and LabVIEW. From their definitions, B, VB0and Nbarrindicate photoelectric properties of ZnO cooperatively under concrete conditions. VB0,grain boundary potential, is parameter of extrinsic properties of ZnO determined by both ZnO and testing conditions. So VB0is critical to control the photoelectric properties of ZnO. A smaller VB0, the stronger the photoelectric response of ZnO and the lager the efficiency of photoelectric conversion. Besides, this theory can be expanded to test the photoelectric properties of the other semiconductor materials. And I-V curves can direct the application of these materials efficiently.

A novel Substrate-Engineered Gate-Grounded NMOS (GGNMOS) structure with very low trigger voltage is proposed to protect the ultra-thin gate oxide effectively in nanoscaled integrated circuits. This device is designed and verified in a 65 nm CMOS process. With increased substrate resistance and pumped triggering current provided by power bus controlled PMOS, this structure features a significantly reduced trigger voltage of 2.8 V and an enhanced uniform conduction of multi-fingers. The failure current can be improved by 23.5% compared with traditional GGNMOS.

The current saturation behaviors of Dual Direction Silicon Controlled Rectifier (DDSCR) and N+ Modified Dual Direction SCR (NMDDSCR) are investigated under transmission line pulse (TLP) stress, compared with Unidirectional SCR (USCR). DDSCR and NMDDSCR are more prone to saturation current state due to different ESD discharge paths, which are verified by TCAD simulation. The saturation current behavior should be suppressed for better ESD effectiveness and robustness. By increasing the lengths of N+ and P+ diffusion area, the saturation current can be suppressed effectively.

The merged and compact MOS-triggered SCR devices have been compared and investigated in a 0.13 μm CMOS process. From experimental results, the turn-on time of compact MOS-triggered SCR has been improved from ∼7.2 ns of merged MOS-triggered SCR to ∼4 ns. Compared to merged MOS-triggered SCR devices, the compact MOS-triggered SCR devices can achieve a lower trigger voltage, a faster turn-on speed, a lower on-resistance, a lower clamping voltage and a higher failure current.

New fully integrated single-chip impulse ultra-wideband (UWB) transmitter front-ends, integrating tunable impulse or monocycle pulse generator with bi-phase shift keying (BPSK) modulator, has been developed using a standard low-cost 0.18-μm CMOS process. The monocycle pulse generator component produces 0.7–0.75 V peak-to-peak monocycle pulse with 140–350 ps tunable pulse duration. The impulse generator generates 0.95–1.05 V peak-to-peak Gaussian-type impulse signal with 100–300 ps tunable pulse duration. The BPSK modulator controls the pulse generator to generate positive or negative pulse signal depending on the “1” or “0” digital data information. The pulse signals produced by the developed transmitters are useful for various UWB applications, especially those requiring the capability of changing ranges and resolutions using only a single system. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1609–1614, 2010; Published online in Wiley InterScience (www.interscience. wiley.com). DOI 10.1002/mop.25250

A single-chip broadband CMOS receiver front-end, integrating a low-noise amplifier (LNA), a correlator, and a template pulse generator, was investigated in nonsinusoidal time-domain environment for possible use as an impulse-type ultra-wideband (UWB) receiver front-end. Particularly, the CMOS LNA and the multiplier making up the core component of the correlator were designed, fabricated, and tested to verify operation in the UWB range. Time-domain results of the integrated CMOS receiver front-end demonstrate its workability as a receiver for nonsinusoidal UWB applications. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2590–2595, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24682

A novel millimeter-wave cavity resonator, completely compatible with commercial CMOS fabrication techniques, has been designed and fabricated in a 0.25-mum CMOS process and tested. The resonator employs a capacitively loaded cavity topology effectively implemented using the CMOS multimetal-layer and via-hole structure. The CMOS capacitively loaded cavity resonator, including two coupling apertures and microstrip feed lines, occupies an area of 2 mmtimes1.4 mmtimes6.28 mum, which is much smaller than the cavity resonator designed without a capacitive load at the same resonant frequency. It resonates at 30 GHz with a corresponding insertion loss of 2 dB and unloaded quality factor of 22.2. The resonant-frequency reduction is approximately 50%, as compared to that without the capacitive load. The design and performance of a new CMOS coupling aperture, which is useful as a coupling mechanism and a vertical interconnect for highly dense millimeter-wave CMOS RF integrated circuits (RFICs) are also presented. The developed low-loss and compact CMOS cavity resonator can be used to realize various millimeter-wave on-chip passive components such as wideband bandpass filters and diplexers and is suitable for direct integration with other CMOS circuits on a single chip. It is attractive for CMOS RFIC design at millimeter-wave frequencies

A novel low-cost low-power fully integrated tunable transmit module composed of a tunable CMOS monocycle pulse generator and compact uniplanar antenna was designed, built, and tested for ultra-wideband (UWB) impulse systems. The CMOS tunable pulse generator integrates a tuning delay circuit, square-wave generator, impulse-forming circuit, and pulse-shaping circuit in a single chip using a standard low-cost 0.25-mum CMOS process. It can generate a monocycle pulse and Gaussian-type impulse (without the pulse-shaping circuitry) signals with tunable pulse duration. A compact uniplanar UWB antenna was also developed and integrated directly with the CMOS pulse generator chip to form the complete integrated tunable UWB transmit module. Measured results show that the CMOS tunable pulse generator can produce a 0.3-0.6-V peak-to-peak monocycle pulse with 140-350-ps tunable pulse duration and a 0.5-1.3-V peak-to-peak impulse signal with 100-300-ps tunable pulse-duration, and the uniplanar antenna has less than a 18-dB return loss and is suitable for transmitting/receiving UWB time-domain impulse signals covering the entire UWB bandwidth of 3.1-10.6 GHz. Good agreement between measured and calculated performance is also achieved. The UWB transmit module was experimentally characterized and its performance is verified. This UWB module finds applications in various time-domain UWB systems including wireless communications and radar

Device-to-Device (D2D) communication assisted with relay transmission could efficiently optimize the system performance when D2D users are too far away from each other. In this paper, considering the individual QoS requirements, we propose a cross-layer relay selection algorithm which combines channel state information (CSI) at physical layer with queue state information (QSI) of buffer for each relay node at data link layer. Then we deduce the relay selection rule based on the CSI and QSI. Our method could make up for the problem that traditional relay selection schemes fail to consider the limited buffer capacity of relays. Simulation results illustrate that the cross-layer relay selection strategy can obtain a substantial system throughput gain. Meanwhile the algorithm leads to a decrease in average transmission time delay and packet error probability compared with the traditional ones.

An improved low-voltage-triggered silicon-controlled rectifier is proposed for on-chip electrostatic discharge (ESD) protection in a 65-nm radio frequency CMOS. The experimental results show that it has a very low intrinsic capacitance of 18 fF at zero bias, a low and tunable trigger voltage in the range of 2.2-4.5 V, a low leakage current of 0.3 nA, and a low overshoot voltage under very fast ESD pulse. It achieves a 1.9-A failure current with only 50×9-μm2 layout area.

Low-voltage-triggering silicon-controlled rectifier (LVTSCR) having a gate structure can offer a low trigger voltage in electrostatic discharge (ESD) applications. To avoid the threat of latch-up, the lateral width of LVTSCR is often stretched to obtain a relatively high holding voltage. The resulting lateral dimension increase, however, enlarges the size of LVTSCR. In this letter, a new method to increase the holding voltage of LVTSCR is developed. It is based on adding a floating-n-well region in the LVTSCR and can increase the holding voltage without requiring additional layout area. Furthermore, with this new LVTSCR, it is possible to implement an ESD protection operation within a very small window of 1 V.

The diode-triggered silicon-controlled rectifier (DTSCR) is frequently used for low-voltage electrostatic discharge (ESD) protection applications, but such a device can exhibit two snapbacks and consequently can possess an undesirable large trigger voltage. This letter investigates the mechanism underlying the DTSCR's multiple triggering. An improved DTSCR for reducing the second trigger voltage and increasing the ESD safe margin is proposed and verified in a 65-nm complementary metal-oxide-semiconductor process. The improved DTSCR's turn-on characteristic is also discussed.

A novel capacitance coupling complementary dual-direction silicon-controlled rectifier (SCR) (CCCDSCR) for high-voltage electrostatic discharge protection is proposed and verified in 0.5-μm BCD process. The trigger voltage of CCCDSCR can be adjusted by coupling capacitance to meet different protection requirements. Compared with traditional lateral double-diffusion NMOS, LDSCR, stacked field-oxide device, and stacked low-voltage-triggering SCR devices, the CCCDSCR has appropriate low trigger voltage of 27.3 V, high holding voltage of 24.3 V, and highest figure of merit (FOM) according to our defined FOM.

Development of UWB CMOS transmitters using carrier and impulse techniques is presented. The carrier transmitter designed using a 0.18-µm CMOS process adopts a double-stage switching to enhance RF-power efficiency and reduce dc-power consumption and circuit complexity. Measurement results show that the generated UWB signal has variable 10-dB signal bandwidths from 0.5 to 4 GHz and tunable central frequency covering the entire UWB frequency range of 3.1 to 10.6 GHz. The impulse transmitter designed using a 0.25-µm CMOS process can generate and transmit both monocycle pulses from 140 to 350 ps and impulses from 100 to 300 ps.

Typical SCR with stripe layout style is modified into segmented one in order to tune the SCR's holding voltage for the ESD protection in different operation voltage domain. SCRs with different segmented style and ratio were made, and according to TLP test results, the most proper one for high voltage ESD protection is selected among them. By delicate layout design and choosing the right segmentation pattern and ratio, the holding voltage of the SCR is obviously lifted to a high level of over 30 V, a high enough value to obtain latch-up immunity.

A new compact, low-cost uniplanar impulse generator using coplanar waveguide structure has been designed, built, and tested. This uniplanar circuit consists of three functions: initial impulse generation, impulse amplification, and impulse compression, which are realized by a step-recovery diode and two-stage GaAs MESFET circuits, respectively. The impulse response has an amplitude of 2.3 V and a half-power pulse width of 115 pS. It has larger amplitude and narrower pulse width than the impulse generated by the SRD circuit alone. © 2003 Wiley Periodicals, Inc. Microwave Opt Technol Lett 39: 470–472, 2003

Oral squamous cell carcinoma (OSCC) is prevalent worldwide, and survival in OSCC has not improved significantly in the last few decades. MicroRNAs have an important regulatory role in oral carcinogenesis. This study investigated the prognostic implications of miR-196 expression and the rs11614913 genotype of the miR-196a2 gene in OSCC. The clinicopathologic implications of miR-196 in OSCC were investigated using expression assays and genotyping, and the functional role of miR-196 in OSCC pathogenesis was investigated using exogenous expression and knockdown. miR-196 was up-regulated in OSCC tissue relative to control mucosa. High expression of miR-196a, but not miR-196b, was associated with tumor recurrence, nodal metastasis, and mortality. Plasma miR-196a levels could be used to distinguish patients from controls with a separating power of 0.75. Multivariate analysis showed that both high miR-196a expression and TT genotype were independent predictors for poor survival in OSCC. The risk of mortality was greatest for patients with high miR-196a level and positive node status. Expression of miR-196 enhanced oncogenesis of OSCC cells, while inhibition of miR-196 expression attenuated such effects. High miR-196a expression in tumor tissue and the presence of the TT variant of miR-196a2 gene indicate worse survival in OSCC.

New fully integrated single-chip impulse ultra-wideband (UWB) transmitter front-ends, integrating tunable impulse or monocycle-pulse generator with bi-phase shift-keying (BPSK) modulator, have been developed using a standard low-cost 0.18-µm CMOS process. The monocycle pulse generator component produces 0.7 – 0.75 V peak-to-peak monocycle pulse with 140 – 350 ps tunable pulse duration. The impulse generator generates 0.95 – 1.05 V peak-to-peak Gaussian-type impulse signal with 100 – 300 ps tunable pulse duration. The BPSK modulator controls the pulse generator to generate positive or negative pulse signal depending on the “1” or “0” digital data information. The pulse signals produced by the developed transmitters are useful for various UWB applications, especially those requiring the capability of changing ranges and resolutions using only a single system.

Three types of MOS-triggered SCR structures: Merged MOS-triggered SCR, compact MOS-triggered SCR and boundary-MOS-triggered SCR devices have been fabricated and compared in 0.13µm CMOS process for on-chip ESD protection. TLP testing results show boundary-MOS-triggered SCR structures can achieve adjustable and lower switching voltage, smaller turn-on resistance, faster turn-on speed, the best ESD robustness and sufficient latch-up immunity compared with other MOS-triggered SCRs.

Transmission Line Pulse (TLP) curve of high voltage SCR-LDMOS (SCR embedded in LDMOS) is measured under various repetitious TLP stress to evaluate its Electrostatic Discharge (ESD) protection capability. Results show that trigger voltage has walk-in behavior. TCAD simulation indicates its mechanism involved is explained by a base push-out effect dominated melt filament growth, that turns a robust ESD clamp into a fragile device susceptible to trigger voltage collapse.

A capacitance coupling complementation silicon controlled rectifies (CCCSCR) for electrostatic discharge (ESD) protection application is proposed and verified in 0.5µm BCD process. Compared with traditional complementation silicon controlled rectifies (CSCR), the CCCSCR has a lower trigger voltage. The coupling capacitance, as a tunable trigger of SCR, can meet different protection application demands. And the CCCSCR can fulfill all dual direction ESD stress mode protection, including I/O-VSS, I/O-VDD and VDD-VSS.

There are few good evaluation methods to evaluate CDM ESD protection performance such as device turn-on speed, etc. A new current-waveform-based method to evaluate the turn-on speed of an ESD protection device is proposed. The method uses two Transmission-Line Pulse (TLP) Tester to investigate the turn-on characteristics of SCR and related devices. Both intrinsic and normalized turn-on conditions are defined for protection devices to study the different factors that affect the turn-on characteristic under various conditions. The turn-on of both forwardly and reversely working of devices is measured for the CDM model including positive and negative currents. From the experimental results, it is concluded that NMLSCR's performance is superior to PMLSCR in turn-on speed; MLSCR requires higher It1 to be turned on; and the turn-on speed of a PMLSCR decreases significantly with small increases in pulse amplitude under intrinsic working condition while NMLSCR and LSCR do not exhibit such property.

A novel substrate-trigger GGNMOS structure with increasing the substrate resistance and pumping substrate trigger current using the VDD bus line controlled PMOS is proposed and verified in 65nm CMOS process. The trigger voltage can be significantly reduced to ㌬3V to safely protect the ultrathin gate oxide. The proposed structure has lower overshoot voltage which is helpful to protect the ultrathin gate. The uniform conducting between multi-fingers has greatly enhanced and the failure current can effectively improved by 23.5%