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The electrocardiogram (ECG) is one of the most extensively employed signals used to diagnose and predict cardiovascular diseases (CVDs). In recent years, several deep learning (DL) models have been proposed to improve detection accuracy. Among these, deep neural networks (DNNs) are the most popular, wherein the features are extracted automatically. Despite the increment in classification accuracy, DL models require exorbitant computational resources and power. This causes the mapping of DNNs to be slow; in addition, the mapping is challenging for a wearable device. Embedded systems have constrained power and memory resources. Therefore full-precision DNNs are not easily deployable on devices. To make the neural network faster and more power-efficient, spiking neural networks (SNNs) have been introduced for fewer operations and less complex hardware resources. However, the conventional SNN has low accuracy and high computational cost. Therefore, this paper proposes a new binarized SNN which modifies the synaptic weights of SNN constraining it to be binary (+1 and -1). In the simulation results, this paper compares the DL models and SNNs and evaluates which model is optimal for ECG classification. Although there is a slight compromise in accuracy, the latter proves to be energy-efficient.

Image processing is one of the major techniques that are used for computer vision. Nowadays, researchers are using machine learning and deep learning for the aforementioned task. In recent years, digit recognition tasks, i.e., automatic meter recognition approach using electric or water meters, have been studied several times. However, two major issues arise when we talk about previous studies: first, the use of the deep learning technique, which includes a large number of parameters that increase the computational cost and consume more power; and second, recent studies are limited to the detection of digits and not storing or providing detected digits to a database or mobile applications. This paper proposes a system that can detect the digital number of meter readings using a lightweight deep neural network (DNN) for low power consumption and send those digits to an Android mobile application in real-time to store them and make life easy. The proposed lightweight DNN is computationally inexpensive and exhibits accuracy similar to those of conventional DNNs.

In this paper, a negative high voltage DC-DC converter using a new cross-coupled charge pump structure has been proposed, which can solve the shoot-through current problem of the conventional charge pump by using a four clock phase scheme. Also, by switching the power supply to each stage based on the supply voltage, a variable voltage gain can be obtained. A complete analysis of the interaction between the power efficiency, area, and frequency have been presented. The proposed negative charge pump is designed to deliver 40μA with a widesupply range from 2.5V to 5.5V using 0.18μm high voltage LDMOS technology.

Electrocardiogram (ECG) classification has become an essential task of modern day wearable devices, and can be used to detect cardiovascular diseases. State-of-the-art Artificial Intelligence (AI)-based ECG classifiers have been designed using various artificial neural networks (ANNs). Despite their high accuracy, ANNs require significant computational resources and power. Herein, three different ANNs have been compared: multilayer perceptron (MLP), convolutional neural network (CNN), and spiking neural network (SNN) only for the ECG classification. The ANN model has been developed in Python and Theano, trained on a central processing unit (CPU) platform, and deployed on a PYNQ-Z2 FPGA board to validate the model using a Jupyter notebook. Meanwhile, the hardware accelerator is designed with Overlay, which is a hardware library on PYNQ. For classification, the MIT-BIH dataset obtained from the Physionet library is used. The resulting ANN system can accurately classify four ECG types: normal, atrial premature contraction, left bundle branch block, and premature ventricular contraction. The performance of the ECG classifier models is evaluated based on accuracy and power. Among the three AI algorithms, the SNN requires the lowest power consumption of 0.226 W on-chip, followed by MLP (1.677 W), and CNN (2.266 W). However, the highest accuracy is achieved by the CNN (95%), followed by MLP (76%) and SNN (90%).

In this paper, we proposed a nano-power tunable bump circuit. It incorporates a novel source-degenerated transconductor using pseudo-resistor as source resistor to control the width of the bump. The presented circuit is simulated in Cadence using 180nm CMOS process under 1.8V power supply. The results show that the transconductance is tuned with pseudo-resistor and the bump circuit can operate with wide voltage range from 0.3V to 1.8V. Also, this circuit is compact and only dissipates 16.7nW power which makes it perfect for large-scale machine learning applications such as classifier and support vector machine.

Recent advances in the field of AI have proved that deep neural networks perform and recognize arrhythmia better than cardiologists when trained with a large chunk of data. However, despite the better performance, deep neural networks demand more resources. Therefore, in this paper, a new deep neural network using low resources has been proposed while maintaining high performance, and it is enhanced with a depthwise separable convolution layer for Electrocardiogram (ECG) classification. The algorithm is performed on the Physikalisch-Technische Bundesanstalt (PTB) diagnostic dataset taken from Physionet consisting of two classes: Myocardial Infarction (MI) and Normal (N). Our simulation results show that the proposed lightweight DNN provides high performance with almost the same accuracy as conventional SquezeNets.

Multi-threshold null convention logic (MTNCL) is a commonly used asynchronous paradigm for designing low power NCL circuits. Traditionally, MTNCL circuits implemented using complementary metal oxide semiconductor (CMOS) technique that tends to occupy a large area. To address this limitation, a gate diffusion input (GDI) methodology is introduced for implementing MTNCL circuits. This GDI technique enables complex logic to be implemented using only two transistors that helps to reduce area utilization. In this paper, a novel approach to implement MTNCL designs based GDI methodology is proposed. The proposed approach has been verified by implementing TH23 MTNCL gate. Comparing to the conventional CMOS implementation, the proposed approach shows a 45% reduction in the area overhead.

Graphical Processing Units (GPUs) are always criticized for high power consumption due to its massive performance that it can deliver. While GPUs are getting into the mobile market, more power constraints are established. In this work, we evaluate the power gating techniques for GPU cache arrays. The leakage power in active mode is measured at 2.28 µW whereas is sleep mode leakage power is measured at 0.61 µW (26.7% of active mode leakage) and 0.034 µW at off mode (1.5% of active mode leakage) at 1.0V power supply using 45nm standard CMOS process.

Cardiovascular diseases (CVDs) are the number one cause of death today. Therefore, the early detection of arrhythmia is very important for cardiac patients. This paper proposes the heartbeat classification algorithm using the electrocardiogram(ECG) signals. An ECG is a 1D signal that is the result of recording the electrical activity of the heart using an electrode. In this paper, a single-layer Tensorflow LSTM model has been proposed to classify a biological time-series consisting of normal and abnormal heartbeats. The method was evaluated using the publicly available Physio net's MIT-BIH Arrhythmia dataset. The dataset has been divided into training and testing data. As a result, the classifier achieved a 95% average accuracy. Compared with the other CNN and RNN models used for the heartbeat classification, the simulation result shows the proposed algorithm has higher accuracy.

Most of the existing hand detection methods rely on the contour shape of hand after skin color segmentation. Such contour shape based computations, however, are not only susceptible to noise and other skin color segments but also inherently sequential and difficult to efficiently parallelize. In this paper, we implement and accelerate our in-house distance image based approach using CPU-GPU heterogeneous computing. Using emerging CPU-GPU heterogeneous computing technology, we achieved 5.0 times speed-up for 320x240 images, and 17.5 times for 640x480 images and our experiment demonstrates that our proposed distance image based hand detection is robust and fast, reaching up to 97.32% palm detection rate, 80.4% of which have more than 3 fingers detected on commodity processors.

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

This paper presents a low power and small area temperature sensor with interlaced hysteresis delay cells (IHDCs) instead of using inverter-based buffers. IHDC consumes lower power and occupies smaller silicon area than inverter-based buffers. A pulse width which is proportionate to temperature is produced by the proposed temperature-to-pulse generator. Two different delay lines and an XOR gate are employed to detect pulse width for temperature measurement. Temperature dependent and thermal insensitive delay lines are used as the two different delay lines. The output of the temperature-to-pulse generator is converted to digital output by a time-to-digital converter. This temperature sensor is simulated with 0.18um CMOS technology and 1.8V supply voltage, and it shows a good linearity with lower power consumption compared to conventional ones. The proposed temperature sensor consumes 1.185 mW.

The clothing materials are ubiquitous part of our everyday life for thousands of years. However, despite this they have largely not been considered as an input surface in human device interactions, but that is until more recently as today's developments of wearable sensors, that are small and flexible in nature, have open this platform. The clothing materials' shape-changing nature enables the users to perform gestures (e.g., bend or stretch) not possible when compared to the interaction methods of flat touchscreens of mobile devices. In addition, the clothing-based interfaces by default have the unique advantage of being placed anywhere on the body and always being with the wearers and their devices. In this paper, we validate the use of clothing-based wearable sensors to support interacting with mobile devices and present some challenges to be overcome for clothing-based interfaces to be adopted more widely.

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. 4×4 multipliers have been designed in a 45nm predictive technology using the proposed SG-SCL gates and pipeline structure and using the conventional MTNCL (Safe SECRII architecture), and they have been compared in terms of speed, power consumption, energy and size. The simulation results show that the proposed design reduces 60% energy, 54% leakage power and 25% area compared to the MTNCL (Safe SECRII architecture) design.

Null Convection Logic is a well-known paradigm for designing asynchronous logic circuits. The conventional CMOS-based NCL designs suffers larger area overhead and power consumption. A low power design technique called Gate Diffusion Input (GDI) has been adopted to overcome this limitation. In GDI technology, voltage swing exhibits significant voltage drop across the circuit. Therefore, not suitable for designing large combinational circuits. A novel HYBRID (CMOS+GDI) design is proposed in this work to efficiently address this issue. The HYBRID design utilizes both CMOS and GDI technology to reduce the number of transistor and power dissipation when compared to CMOS NCL circuits. The proposed approach is implemented in NCL Ripple Carry Adder (RCA) and simulated in Cadence Virtuoso for verification.

3D heterogeneous processor (commonly termed as 3DHP) integrating multiple processor (such as CPU/GPU) and DRAM dies vertically interconnected by a massive number of Through-Silicon Vias (TSVs) is expected to address the limited bandwidth, high latency and energy consumption of off-chip DRAM. However, spatial and temporal variability due to hotspots in on-chip thermal gradient may result in wide bit error rate variation in DRAM dies. A multi-path BCH decoder has been recently proposed to efficiently address this issue. In this paper, a novel parallel decoding approach for the Multi-Stage BCH decoder is proposed and validated. The proposed approach efficiently leverages the multiple decoding paths to decode multiple words and minimizes the overall decoding latency.

This paper proposes presents a low power and high-speed four-quadrant analog multiplier in the current mode based on dual translinear loops using 32nm CMOS and 32nm CNTFET technologies to investigate and compare the performance differences of the analog circuits on CNTFET technology and CMOS 32nm technology nodes. All the simulations were performed using hspice with 32nm CMOS from PTM library and 32nm CNTFET from Stanford University technologies at the same power supply level. CNTFET based multiplier shows a wider linearity over considerable range of outputs (−10 μA to +10μA) while the CMOS based multiplier shows (−7μA to +7μA) and the 3db frequency of the CNTFET based multiplier is 110GHz while the 3dB frequency of the CMOS based multiplier is only 2.45GHz.

This paper presents a UHF RFID Reader designed for recognition and tracking in IoT domain. It is built by NI USRP software radio platform and NI LabVIEW with flexible physical/MAC layer parameters, which can be modified easily and monitored clearly from front panel of this Reader compared to commercial RFID Reader. Queried random number sequence from a commercial Tag can be detected within half meter using this UHF Reader. All designs of this Reader are based on EPC Gen-2 RFID protocol, any further research based on this Reader can be easily connected and tested with commercial Tags.

Any real architecture designed only in the CNFET technology as a hopeful substitution of the silicon CMOSFET has not been developed because of shortage of self-assembly CNFET technology for designing complex CNFET structures. Therefore, for designing the real architecture in the current self-assembly CNFET technology, the development of a simple CNFET circuit structure forming all the digital function is required. This paper proposes a simple CNFET circuit structure using back-gate voltages to design the real digital architecture and to overcome the high fabrication cost of CNFETs and manufacturing variability and imperfection of CNFET technology. The function of the proposed CNFET cell is determined by the back-gate voltages, and the determined function is the same as NAND or NOR gate function. The simulation results present that the propagation delay time of the ISCAS85 circuits in a 32nm Stanford CNFET technology deploying the proposed CNFET cells is reduced by over 42% compared to the conventional CNFET cell in ultra-low voltage (0.4V).

This paper presents an area efficient 3-tap speculative Decision Feedback Equalizer (DFE) with a novel current-integrating summer for data self correction in standard CMOS 180nm technology node. The conventional first-tap speculative half-rate DFE is composed of four different paths, which have exactly same hardware. In this paper, a novel area efficient DFE is proposed where the four summers are reduced to two. By using switched-capacitors to separate the first speculative tap, two parallel paths for speculation can be driven by a single summer. The proposed DFE consumes 17.4 mW with 1.8V supply when equalizing 4Gb/s data passed over a channel with 28 dB loss at 2GHz.

Ultra low-power design and energy harvesting applications require digital systems to operate under extremely low voltages approaching the point of balance between dynamic and static power consumption which is attained in the sub-threshold operation mode. Delay variations are extremely large in this mode. Therefore, in this paper, a new low-power logic design methodology using asynchronous NCL circuits is proposed to reduce power consumption and not to be affected by various technology variations in nanoscale MOSFET technology. The proposed NCL is evaluated using various benchmark circuits at 0.4V supply voltage, which are designed using 45nm MOSFET predictive technology model. The simulation results are compared to those of conventional synchrouns logic circuits in terms of power consumption and speed.

This paper presents the impact of time dependent dielectric breakdown (TDDB, also called as gate oxide breakdown) failure on nanoscale digital CMOS Circuits. Recently, TDDB for ultra-thin gate oxides has been considered as one of the critical reliability issues which can lead to performance degradation or logic failures in nanoscale CMOS devices. Also, leakage power in the standby mode can be increased significantly. In this paper, TDDB aging effects on large CMOS digital circuits in the 45nm technology are analyzed. Simulation results show that TDDB effect on MOSFET circuits can result in more significant increase of power consumption compared to delay increase.

This paper proposes a new input pattern generator for minimal leakage power in the nanometer CMOS technology considering all the leakage current components (sub-threshold leakage, gate tunneling leakage, band-to-band tunneling leakage). Using the accurate macro-model, a heuristic algorithm is developed to generate a input pattern for the minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The simulation result shows that our method"s accuracy is within a 5% difference of the Hspice simulation results. In addition, the simulation time of our method is far faster than that of the Hspice simulation.

Ubiquitous network and wireless sensor networks is being applied in various fields. Located at target areas, node of wireless sensor network uses batteries as a power source. Batteries have a limited energy in sensor network applications. Also, before use, the battery must be charged and It is difficult to replace the battery. Therefore, energy harvesting technology is being researched and being developed for long life of sensor node. Especially, sola energy is being extensively researched. because that can have great amounts of energy than other environmental energy in a short time. In this study, we tested battery charging and recharging, operation of sensor node using Solar Cell. Also, monitoring data gathering and voltage Analysis showed energy harvesting time of Sola Cell battery for sensor node and operation of sensor node.

Accurate performance-degradation monitoring of nanometer MOSFET digital circuits is one of the most critical issues in adaptive design techniques for overcoming the performance degradation due to aging phenomena such as negative bias temperature instability (NBTI) and hot carrier injection (HCI). Therefore, this paper proposes new on-chip aging sensor circuits which deploy a threshold voltage detector for monitoring the performance degradation of an aged MOSFET. The new aging sensor circuits measure the threshold voltage difference between a NBTI/HCI stressed MOSFET device and a NBTI/HCI unstressed MOSFET device using an inverter chain and a phase comparator and digitalize the phase difference induced by the threshold voltage difference. The proposed sensor circuits achieve a direct correlation between the threshold voltage degradation and the phase difference (a phase difference resolution of 1 ns per 0.01 V threshold voltage shift). Also, the circuits are almost independent of temperature variation due to symmetrical circuit structures. A 45 nm CMOS technology and predictive NBTI/HCI models have been used to implement and evaluate the proposed circuits. The implemented layout size is 18.58 x 7.97 μm2; the post-layout power consumption is 18.57 μW during NBTI/HCI stress mode and 30.86 μW during NBTI/HCI measurement mode on average.

This article describes a novel technique for analysing the effects of supply voltage noise on circuit delay for VLSI circuits. Scattering parameters are used to model the supply voltage variation in the frequency domain and to reduce the original power grid and simulation time. The interconnections of the power grid are modelled by RLC passive elements, constant voltage and time-varying current sources. A fast and accurate MOSFET modelling method for a static timing analyser is proposed based on the power grid analysis. A MOSFET logic is modelled in three different regions during transition, and the maximum delay is formulated as a constrained non-linear optimisation problem by considering the power supply noise (inclusive of the IR-drop and the Ldi/dt drop). The proposed technique has been applied to ISCAS85 benchmark circuits redesigned in 45 nm technology. The results are compared to Hspice; they show that the error is within 5% of the Hspice simulation results.

A novel power gating (PG) structure using only low-threshold-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed to extend the PG to an ultralow-voltage region ( ~ 0.3 V). The proposed structure deploys series-connected low-V th footers with two virtual ground ports and selectively chooses the logic cells for connecting them to each virtual ground port according to the delay criticality. Furthermore, additional circuitry is designed to reduce not only the subthreshold leakage current but also the gate-tunneling leakage and to reduce the wake-up time and rush current compared to the conventional PG. The total PG switch size of the proposed PG structure including the additional circuits is less than the conventional one. The simulation results are compared to those of other well-known circuit schemes and show that, in the ultralow-voltage region, the other high-V th-based PG schemes cannot be used due to the impractical delay increase and long wake-up time, whereas the proposed PG structure keeps the balance among the critical PG issues. The proposed PG is evaluated using inverter chains and ISCAS85 benchmark circuits at 0.6-V supply voltage, which are designed using 45-nm complementary metal-oxide-semiconductor predictive technology model.

This paper proposes a novel design method to minimize the leakage power during standby mode using a novel adaptive supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The process, voltage, and temperature (PVT) variations are monitored and controlled independently by their own dedicated systems. The minimum level of V DD and the optimum body-bias voltage are generated for different temperature and process conditions adaptively using a lookup table method based on the PVT monitoring and controlling systems. The power supply variations is accurately compensated adaptively through the monitoring circuits based on the propagation delay change of the inverter chains. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power at least by 500 times for ISCAS'85 benchmark circuits designed using 32-nm CMOS technology comparing to the case where the method is not applied.

This paper presents a novel statistical characterization for accurate timing and a new probabilistic-based analysis for estimating the leakage power in partially depleted silicon-on-insulator (PD-SOI) circuits in 100-nm BSIMSOI3.2 technology. This paper shows that the accuracy of modeling the leakage current in PD-SOI complementary metal-oxide-semiconductor (CMOS) circuits is improved by considering the interactions between the subthreshold leakage and the gate tunneling leakage, the stacking effect, the history effect, and the fan-out effect, along with a new input-independent method for estimating the leakage power based on a probabilistic approach. The proposed timing and leakage power estimate algorithms are implemented in MATLAB, HSPICE, and C. The proposed methodology is applied to ISCAS85 benchmarks, and the results show that the error is within 5%, compared with random simulation results.

This paper presents a fast statistical static timing and leakage power analysis in Partially-Depleted Silicon-On-Insulator (PD-SOI) CMOS circuits in BSIMSOI3.2 100 nm technology. The proposed timing analysis considers floating body effect on the propagation delay for more accurate timing analysis in PD-SOI CMOS circuits. The accuracy of modeling the leakage power in PD-SOI CMOS circuits is improved by considering the interactions between the subthreshold leakage and the gate tunneling leakage, the stacking effect, the history effect, and the fanout effect. The proposed timing and leakage power analysis algorithms are implemented in Matlab, Hspice, and C language. The proposed methodology is applied to ISCAS85 benchmarks, and the results show that the error is within 5% compared with random simulation results.

This paper proposes a novel design method to minimize the leakage power during standby mode using a novel optimal supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The minimum level of VDD is generated for different temperature and process conditions adaptively using a look-up-table method. The subthreshold current as well as gate-tunneling and band-to-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power by 1000 times on average for ISCAS85 benchmark circuits designed using 32nm CMOS technology comparing to the case where the method is not applied.

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 M~725 MHz with a multipli-cation range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

This paper presents a feasibility study of a central pattern generator-based analog controller for an autonomous robot. The operation of a neuronal circuit formed of electronic neurons based on Hindmarsh-Rose neuron dynamics and first order chemical synapses is modeled. The controller is based on a standard [email protected] CMOS process with 2V supply voltage. In order to achieve low power consumption, CMOS subthreshold circuit techniques are used. The controller generates an excellent replica of the walking motor program and allows switching between walking in different directions in response to different command inputs. The simulated power consumption is 4.8mW and die size including I/O pads is 2.2mm by 2.2mm. Simulation results demonstrate that the proposed design can generate adaptive walking motor programs to control the legs of autonomous robots.

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32㎚ predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440㎒ output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40M~725㎒ with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

This paper proposes a novel ultra-low voltage and high speed Schmitt trigger circuit designed in silicon-on-insulator (SOI) technology. The proposed circuit is designed using dynamic threshold MOS (DTMOS) technique and multi-threshold voltage CMOS (MT-CMOS) technique to reduce power consumption and accomplish high speed operation. The experiment shows the proposed Schmitt trigger circuit consumes 4.68µW at 0.7V power supply voltage and the circuit demonstrates the maximum switching speed of 170psec.

GPU (Graphics Processing Unit) is emerging as a key 3D/2D graphics and parallel workload accelerator in various SoC applications. As semiconductor fabrication technology continues to scale, chips (especially those with extremely high transistor counts such as processors) are becoming increasingly vulnerable to faults that could produce unwanted errors in computing. The most severe problem is Silent Data Corruption (SDC) because this fault insidiously generates erroneous outputs without being detected. This paper discusses the characterization of SDC vulnerability of GPU on various GPGPU (General Purpose computing on GPU) workloads.

Hand detection plays an important role in Human Computer Interaction (HCI). Most of the existing hand detection methods rely on the contour shape of hand after skin color segmentation. Such contour shape based approaches, however, are easily distorted by noises and other skin color segments. In this paper, we present a distance image based approach using CPU-GPU heterogeneous computing. Our experiments demonstrate that our proposed distance image based hand detection is robust and fast, reaching up to 97.32% palm detection rate where 80.36% of cases have more than 3 fingers detected on commodity processors. We also achieved 5.0 times speed-up for 320×240 images, and 17.5 times for 640×480 images.

Internet of Everything (IoE), embedded with microcontrollers and wireless technologies onto a single system on a chip (SoC), are able to be connected with other devices in the cloud. Wearable sensors and RFID are core technologies in IoE. Energy efficiency and miniaturization are the two most critical technical challenges for the hardware implementation of microelectronic systems enabling Internet of Everything. Low-power smart systems on a chip are the key enabling solutions. In this paper, we outline the key hardware components and design challenges of BSN.

In this work, an efficient hardware architecture of modulo 2n + 1 squarer is proposed and validated. The proposed modulo 2n + 1 squarer use novel compressor designs and sparse tree adders as primitive building blocks for fast low-power operations in three major functional modules including partial products generation module, partial products reduction module and final stage addition module. The resulting modulo 2n + 1 squarer has been implemented in standard CMOS (Complementary Metal-Oxide Semiconductor) cell technology and compared both qualitatively and quantitatively with the existing hardware implementations. The unit gate model analysis and the experimental results show that the proposed implementation is faster and consume less power than existing hardware implementations.

The delay-insensitive Null Convention Logic (NCL) as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level topologies of conventional NCL gates have weakness of logic speed, area overhead or wire complexity. Therefore, this paper proposes a new NCL gates designed at transistor level for high-speed, low area overhead. A 4×4 multiplier using the proposed NCL gates has been compared to the multiplier using conventional NCL gates in terms of delay, area and energy consumption.

In nanometer technology, accurate circuit aging prediction of MOSFET digital circuits caused by aging phenominon is one of the most critical issues for more reliable adaptive tuning system design. This paper proposes a new on-chip aging sensor circuit to predit and detect a circuit failure caused by BTI and HCI aging effects on digital circuits. The proposed circuit is based on timing warning windows to warn against a guardband violation of sequential circuits, and generates three warning bits right before circuit failures occur.