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An electroactive passivation for high-voltage diodes with bevel termination has been investigated based on diamond-like carbon (DLC) films. Variations of the DLC properties, i.e., conductivity and geometry, have been investigated by experiments and numerical simulations to the purpose of gaining an insight on their influence on the diode leakage current and breakdown voltage. The role played by the DLC/Si interface has been investigated by characterizing metal-DLC-Si devices. Both Boron and Nitrogen doping have been investigated and a TCAD setup has been provided accounting for the main transport features of the DLC material with different doping configurations. A significant polarization effect has been observed in the DLC material, which improves the DLC performance as a passivation material. High-voltage diodes have been characterized and simulated with different DLC layers on top of the bevel termination in order to identify the role played by conductivity and polarization on the blocking state. The correlation of leakage current and voltage breakdown with the DLC doping and thickness is provided and explained by the TCAD simulation results.

Diamond-Like Carbon (DLC) is well established material for the passivation of high voltage negative beveled power diode. In our previous works, the conduction mechanism of the DLC has been carefully described through the characterization and the physical modeling of Metal-Insulator-Semiconductor (MIS) structures. In addition, the effects on the breakdown voltage and leakage current have been clarified comparing the available experiments with numerical simulations. However, the role played by the DLC on the breakdown voltage temperature dependence is still lacking. In this work, it has been investigated assuming a release of the trapped charges with increasing temperatures.

A simulation study on the impact of interface traps and strain on the ${I}$ – ${V}$ characteristics of co-optimized p- and n-type tunnel FETs (TFETs) realized on the same InAs/Al0.05Ga0.95Sb technology platform is carried out, using a full-quantum ballistic simulator. In order to capture the effect of interface/border traps on the device electrostatics consistently with carrier degeneracy and ballistic transport, the classical Shockley-Read–Hall theory has been properly generalized. The effect of an experimental ${D}_{\mathrm {it}}$ distribution of a high- ${k}$ gate stacks on InAs has been investigated. Unfortunately, traps induce a significant reduction of the ON-state current. However, it turns out that localized strain at the source/channel heterojunction caused by lattice mismatch is able to induce for the n-type TFET, a performance enhancement with respect to the ideal device even in the presence of traps. On the contrary, for the p-type one, a current degradation $\simeq 18$ % is observed.

A simulation study exploring the possibility of performance improvements for GaSb/InAs nanowire TFETs under appropriate stress conditions is carried out. It is demonstrated that biaxial tensile strain induces a remarkable enhancement of the on-state current thanks to bandgap reduction; however, a degradation of the ambipolar behavior is observed as well. Some stress intensity values and device geometry configurations are investigated. The best simulated device can achieve an on/off current ratio of about 3 × 10 7 with I ON ≈ 0.33 mA/ μ m at V DD = 0.3 V.

A TCAD-based approach has been used to investigate the leakage current and breakdown regime of vertical GaN/AlGaN/Si structures at different ambient temperatures. TCAD modeling has been used to assess possible mechanisms of the forward-bias leakage current. A good agreement with experimental data has been obtained by implementing both trap-assisted and Poole–Frenkel conduction mechanisms into the deeper buffer layers, indicating that conduction is dominated by electron injection from silicon into a continuum of states at a given energy offset in the transition layer, which might be associated with conductive dislocation defects. The latter mechanisms have been proven to anticipate the onset of breakdown at high temperatures.

We present and thoroughly compare band-structures computed with density functional theory, tight-binding, k · p and non-parabolic effective mass models. Parameter sets for the non-parabolic Γ , the L and X valleys and intervalley bandgaps are extracted for bulk InAs, GaAs and InGaAs. We then consider quantum-wells with thickness ranging from 3 nm to 10 nm and the bandgap dependence on film thickness is compared with experiments for In 0.53 Ga 0.47 As quantum-wells. The impact of the band-structure on the drain current of nanoscale MOSFETs is simulated with ballistic transport models, the results provide a rigorous assessment of III–V semiconductor band structure calculation methods and calibrated band parameters for device simulations.

The interplay between electrical stress and ionizing radiation effects is experimentally investigated in Si-based Tunnel Field Effect Transistors (TFETs). In particular, the impact of bias conditions on the performance degradation is discussed. We found that the electrical stress effects in TFETs could not be ignored in radiation tests, since they can possibly overwhelm the radiation-induced degradation. Under this circumstance, the worst-case bias condition for studying radiation effects is not straightforward to be determined when there is an interplay between electrical stress and ionizing radiation effects.

The Graphene-Base Heterojunction Transistor (GBHT) is a novel device concept with a high potential for analog high-frequency RF operation, in which the current is due to both thermionic emission and tunneling. In this paper we study through numerical simulations the influence of previously uninvestigated aspects of Si- and Ge-based GBHTs—namely, crystallographic orientation and doping density values—on the device performance; a comparison with an aggressively scaled HBT structure is then reported. The simulations are carried out with an in-house developed code based on a 1-D quantum transport model within the effective mass approximation and the assumptions of ballistic transport with non-parabolic corrections and ideal semiconductor–graphene interface. We show that crystallographic orientation has a negligible effect on the GBHT performance. The doping density values in the GBHT emitter and collector regions can be tailored to maximize the device performance: the Si device shows better overall performance than the Ge one, yielding a peak cut-off frequency f T higher than 4 THz together with an intrinsic voltage gain above 10, or even higher f T at the cost of a lower gain. The Si-based GBHT can potentially outperform the SiGe HBT by a 2.8 higher f T . For a Si-based GBHT with a circular active region of diameter 50–100 nm, a theoretical balanced value for f T and f max above 2 THz can be achieved, provided the base parasitics are carefully minimized.

A dual-metal-gate (DMG) tunnel FET (TFET) integrating a heavily-doped pocket within the channel is optimized through TCAD simulations by considering quantization-induced bandgap widening. First, the performance penalty due to the reduced tunneling probability is estimated and next, device design options to minimize the negative impact of quantization on the DMG-TFET performance are assessed.

A simulation study on the impact of interface traps (ITs) and strain on the I/V characteristics of co-optimized n- and p-type tunnel field-effect transistors (TFETs) realized on the same InAs/Al 0.05 Ga 0.95 Sb technology platform is carried out using a full-quantum simulator. In order to capture the effect of interface/border traps on the device electrostatics in a way consistent with the ballistic approach, the classical Shockley-Read-Hall theory has been properly generalized. Traps induce a significant reduction on the ON-current; however, the inclusion of a uniform strain induces a remarkable current enhancement able to completely recover the current degradation.

A simulation study of the graphene base heterojunction transistor (GBHT) is presented based on a novel realistic graphene–Si interface model, calibrated on the experimental graphene–Si Schottky diodes, whose current–voltage-temperature characteristics are well reproduced. The GBHT simulations predict $f_{T}$ in the tens-of-gigahertz range and confirm the need for an improved quality of the graphene interface for the terahertz operation to be reached.

The impact of strain and semiconductor/oxide interface traps (ITs) on the turn-on characteristics of a 10x10 nm^2 nanowire (NW) Al0.05Ga0.95Sb/InAs heterojunction n-type tunnel field-effect transistor (TFETs) is carefully investigated using a full-quantum simulator. In order to capture the effect of traps on the device electrostatics in a way consistent with the ballistic approach, the SRH theory has been properly generalized. Our results indicate that the presence of a relatively high IT density can cause a huge current reduction that cannot be recovered exploiting strain. In fact, biaxial tensile strain induces a remarkable current enhancement due to bandgap reduction and tunnel energy alignment at the heterojunction; however, a huge degradation of the ambipolar behavior is also observed.

The interaction between strain and border traps in short-channel InGaAs NW MOSFETs is investigated through full-quantum 3D simulations based on a k·p Hamiltonian. Traps induce a sizable degradation of the ON-current, which can be recovered through the application of a suitable strain, provided the quantization effects, which increase by scaling the NW lateral size, do not become too large.

A TCAD-based approach is proposed to investigate the most relevant transport mechanisms of diamond-like carbon (DLC) films at different biases and ambient temperatures. Starting from the band structure and boundary conditions of a metal-insulator-metal (MIM) device, the most relevant trap levels have been determined against experiments along with the Poole-Frenkel conduction effect. The affinity of the DLC under study has been extracted from experiments on the corresponding metal-insulator-semiconductor (MIS) diode. A clear polarization effect has been found in the measured C-V curves at different frequencies. The latter has been modeled in the TCAD tool via the Debye equation leading to a nice agreement with experiments.

A simulation study of the graphene base transistor is presented based on the most recent experimental results involving a novel double-layer emitter-to-base insulator made of TmSiO and TiO2. The simulations are based on a 1-D quantum transport model with the effective mass approximation, and reproduce well the experiments both in terms of current levels and common-base current gain $\alpha $ . Performance projections are then investigated: with transparent graphene, the cutoff frequency is predicted to increase from 1 to 100 MHz by reducing the thickness of TmSiO from 1 to 0.5 nm. In order to go beyond this limit toward the terahertz range, a material with a lower barrier height than TmSiO should be considered. A technological breakthrough boosting the graphene interface quality is also needed in order to obtain acceptable values of $\alpha $ , which are still low.

In this paper we review the evolution of Microelectronics and its transformation into Nanoelectronics, following the predictions of Moore’s law, and some of the issues related with this evolution. Next, we discuss the requirements of device modeling and the solutions proposed throughout the years to address the physical effects related with an extreme device miniaturization, such as hot-electron effects, band splitting into multiple sub-bands, quasi-ballistic transport and electron tunneling. The most important physical models are shortly highlighted, and a few simulation results of heterojunction TFETs are reported and discussed.

We compare through numerical simulations a Si GBHT and a SiGe HBT: the f T limit of GBHTs is predicted to be more than twice as high as for HBTs assuming a transparent graphene/Si interface; if a more realistic interface model extrapolated from existing experiments is used, the f T limit drops by about two orders of magnitude.

Four molding-compound composites with different silica micro-filler size and concentration have been measured on top of dedicated IC test structures. The leakage current of charge sensors has been monitored under different high-voltage stress during charging/discharging transients occurring in the mold. Physical insight of space charge distribution at high electric field and temperature has been obtained by TCAD analysis. The role played by the encapsulation composition on the device-package interaction has been investigated via TCAD simulations of the HTRB test of a Single-RESURF LDMOS.

A simple analytical model of thin-body In 0.53 Ga 0.47 As-on-InP MOSFET low-field electron mobility suitable for integration in Technology-CAD (TCAD) tools is presented. Phonon, Coulomb and surface roughness scattering are accounted for. In order to characterize the phonon scattering contribution, an expression for the device effective thickness is derived from 1-D Schroedinger-Poisson simulations. The model is validated through comparison with experimental C G -V gs and I d -V gs curves collected on transistors with body thicknesses down to 5 nm.

The effects of electrical stress and ionizing radiation on the characteristics of Si-based TFETs were investigated experimentally. We found that the electrical stress effects in TFETs could not be ignored in radiation tests, since they can possibly overwhelm the radiation-induced degradation. Under this circumstance, a lower gate voltage under which the electrical stress effects were suppressed induced a stronger radiation-induced degradation in threshold voltage shift and interface traps accumulation.

A 2D TCAD-based approach is proposed to investigate the leakage current and breakdown regime of GaN/AlGaN/Si structures at different ambient temperatures. Deep-level traps originated by Carbon doping, impact-ionization generation and thermally activated Poole-Frenkel conduction have been modeled to assess the role of such physical mechanisms on the forward-bias leakage current. A good agreement with experimental data has been obtained by implementing conduction and valence mini-bands within the deeper transition layer created by conductive dislocation defects or by superlattice structures. A 2D isolation device has been investigated up to breakdown and, for the first time to our knowledge, we prove with 2D TCAD simulation that in GaN based devices both impact-ionization and Poole-Frenkel conduction effects must be taken into account to correctly match experimental data.

The paper reports the radiation response of TFETs due to the gate oxide and BOX separately, by means of the introduction of three setups of bias during irradiation. The dependency of shift of the threshold voltage due to the interface traps and shifts of the characteristics on bias during irradiation is investigated. Due to the particular doping structures of TFETs, the holes trapping in BOX is mainly induced under the P+ source region rather under the channel, which is inclined to induce the increase of the threshold voltage and the voltage at which band-to-band tunneling occurs. Under this circumstance, the degradation under unbiased case is even worse than under ON biased situation.

We develop a semianalytical model for monolayer graphene field-effect transistors in the ballistic limit. Two types of devices are considered: in the first device, the source and drain regions are doped by charge transfer with Schottky contacts, while, in the second device, the source and drain regions are doped electrostatically by a back gate. The model captures two important effects that influence the operation of both devices: (i) the finite density of states in the source and drain regions, which limits the number of states available for transport and can be responsible for negative output differential resistance effects, and (ii) quantum tunneling across the potential steps at the source-channel and drain-channel interfaces. By comparison with a self-consistent non-equilibrium Green's function solver, we show that our model provides very accurate results for both types of devices, in the bias region of quasi-saturation as well as in that of negative differential resistance., Comment: 10 pages, 14 figures

Total ionizing dose (TID) effects in Si-based tunnel finite element transfers (FETs) were investigated for the first time. Under 10-keV X-ray irradiation environment, along with the increase in total dose, a shift of the transfer characteristics and an increase in the interface trap density could be observed. After irradiation at 1 Mrad (SiO 2 ) (and higher dose), the threshold voltage and the band-to-band tunneling conduction were only modestly affected, despite the thick buried oxide (140 nm). In contrast, under the same bias and irradiation environment, a FDSOI nMOSFET fabricated with a similar process presented a more severe degradation, suggesting the robustness of TFETs against TID effects. The underlying mechanism was explored through device simulation and ascribed to be due to the peculiarity of the doping structures of TFETs.

In this work the effect of high-k gate dielectrics on the power-speed performance of SL-FETs realized with the InGaAs/InAlAs and InGaAs/InP material pairs is investigated by numerical simulations. The analysis shows that the InGaAs/InP pair, in association with Al 2 O 3 as the gate dielectric, provides the most promising results for high-performance applications, i.e. an on-state current approaching 2 mA/μm and an intrinsic delay lower than 0.16 ps at a supply voltage of 0.4 V. The average subthreshold swing SS is much lower than 60 mV/dec over six current decades and the point slope SS ≈ 20mV/dec. These results outperform the ITRS requirements projected to year 2022 in terms of both static and dynamic power dissipation, and make the proposed device well suited for high-performance and low-power applications at the same time.

Effect of transverse quantization on the broken vs. staggered band lineup of InAs/Al(x)Ga(1-x)Sb TFETs is investigated, showing that cross-sections up to 10nm lead to staggered configurations for any value of the Al mole fraction x. Device performance is optimized as a function of cross-sectional size, Al content and possible source/channel underlap, while ensuring low standby power (LSTP) or low operating power (LOP) compatible off-current levels. Guidelines are provided and an “optimal” design is proposed which provides a minimum sub-threshold slope (SS) of 7.2 mV/dec along with a maximum on-state current (Ion) of 175μA/μm.

The working principles of the hot-electron graphene base transistor (GBT) for analog terahertz operation have been investigated by means of a self-consistent Schrodinger-Polsson solver code. Its regions of operation are defined and discussed. With the help of a small-signal model, it is shown that the cutoff frequency does not depend on the quantum capacitance of the graphene layer, which on the contrary severely affects the intrinsic voltage gain, and that terahertz operation is possible.

In this paper, we model the electrical properties of a junctionless (JL) ultrathin-body silicon-on-insulator field-effect transistor (SOI-FET), which has been proposed as a possible alternative to the junction-based SOI-FET. The model is based on improved depletion approximation, which provides a very accurate solution of Poisson's equation and allows for the computation of the substrate, as well as the Si-body lower- and upper-surface potentials by an iterative procedure, which accounts for the back-oxide (BOX) charge and thickness and the potential drop within the substrate. The drain current is then computed versus gate, drain, and substrate voltages via integral expression and validated by comparison with technology computer-aided design simulation results. Analytical models of the field-effect-transistor threshold voltage and subthreshold slope are worked out against the substrate voltage, highlighting the effect of the substrate doping and BOX thickness on the aforementioned parameters. In essence, this work provides the physical background for better understanding of the JL SOI-FET and its assessment for logic applications.

In this work we investigate the achievable device performance of steep-slope nanowire FETs based on the filtering of the high-energy electrons via a superlattice heterostructure in the source extension. Four material pairs are investigated for the superlattice (SL), with the aim to identify the most promising ones with respect to the typical FET evaluation metrics. We found that the InGaAs-InAlAs pair can provide an inverse subthreshold slope SS = 13 mV/dec and an on-state current ION = 4.5 mA/μm@VDD = 0.4V. These results outperform the ITRS requirements for the 21 nm technology node.