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We regret that a tribute, which was submitted with the original manuscript by the authors, in honor of Prof. Shuichi Miyazaki was unfortunately omitted during the publication process.

Process-induced and environmental fluctuations play an important role in the design process for modern high-performance integrated circuits. The conventional principle of considering the verification of worst-case requirements reduces the performance that can potentially be achieved by circuits and technology. This paper presents a new mechanism that permits the compensation of random independent delay fluctuations due to environmental factors. It shows that it is significantly possible to reduce the latency time of a circuit even for a moderate length of pipeline stages.

In the paper, an analytical model for ground bounce noise evaluation taking into account the interdependence between IDD switching current and VDD noise voltage is presented. The model shows the discrepancies from general accepted assumption of independence between the two variables. The main conclusion is that noise calculations using the independence assumption cause an overestimation of the noise levels. The results are verified through realistic simulations and for different technology nodes and accurate analysis of two canonical circuits.

Shape memory alloys (SMA) are good candidates for solid state dampers because of their large recoverable strain and hysteresis. In this work, experimental analysis and modeling of the thermomechanical behavior for two SMAs is done. The SMA models are developed and included in a finite element simulation environment (ANSYS). Using these developing tools, a complete damping solution for a family house is outlined. The paper presents the design and optimization methodology for the dampers, analyzes their performance, and quantifies the relevant physical effects from the experimental measurements. The simulation results show that the SMA dampers are capable of reducing the maximum oscillation amplitude induced by “El Centro” accelerations by a factor 2 and that they dissipate 50% of the energy transmitted to the structure. Furthermore, SMA dampers constitute a passive, unsupervised damping solution appropriate for family houses.

The behavior of shape memory alloys (SMA) allows their use as a passive smart material. In particular, the existence of a hysteretic cycle in the domain of the elementary coordinates strain-stress-temperature (σ, E, T) suggests its application for damping in mechanical and/or in civil engineering. We are working in the application of SMA as dampers for earthquakes in small houses as family homes. For dampers installed in the inner porticos of the house, the suggested SMA is the CuAlBe and, eventually, the NiTi. At room temperature the used SMA wires induces forces situated between 2-3kN/wire. The properties related with the damping applications for CuAlBe and NiTi, i.e., the SMA creep and the self-heating will be presented, together with some other minor stress and temperature effects on NiTi modifying the hysteretic behavior.

The evolution of the integrated circuit technology during the last 3 decades has been based on an increasing accuracy of the manufacturing process. With thisprinciple and by using a quality control at the end of the production line (Test Technology) the semiconductor industry has reached very high productivity levels. However, with technology reaching criticalsizes ( < 65 nm) the manufacturing controlis startingto failand new design principles have to be introduced to be able to produce functional chips from low quality components. In this article two scenarios partially addressing the problem with gradual introduction of redundancy are considered: the scenario of the era at the end of the CMOS Moore's Law and the expected next scenario of nanoelectronic technology using new emergent devices. In the paper techniques for the design of robust electronic systems in spite of the low quality of components are presented for the two scenarios.

Efficient prediction of the substrate noise generated by large digital sections is currently a major challenge in System-on-a-Chip design. A macromodel to accurately and efficiently predict the substrate noise generated by digital standard cells is presented. The macromodel is generated from identification of the physical elements relevant to noise generation. Techniques to directly or indirectly compute the values of the elements in the cell macromodel are proposed. Using this macromodel, prediction of the noise generated by large digital sections can be easily done following a methodology based on high-level logic simulation. As a first step to validation, the macromodel accuracy is demonstrated in some circuits consisting of a reduced number of gates.

The continuous shrinking of process geometries increases variability and demands for conservative margins that have a negative impact on performance. With conventional clocks, the cycle period has to be defined to accommodate the worst-case variations during the lifetime of the circuit. Elastic Clocks arise as a new paradigm to reduce the margins without sacrificing robustness. Their cycle-by-cycle adaptation to static and dynamic variability enables the use of reduced margins that only need to cover the differential variability of the circuit delays with regard to the elastic period. Given the substantial spatio-temporal correlation within every die, a significant reduction in the margins required to cover process variability, voltage and temperature fluctuations and aging can be achieved.

Shape Memory Alloys (SMA) show particular properties associated to their martensitic transformation between metastable phases. Their use in dampers requires a deep knowledge of the SMA behavior and its coherence with the application requirements. In earthquakes engineering standard conditions require that, after several years or decades at rest, an excellent performance is necessary for one or two minutes, i.e., nearly 200 working oscillations. When the target is the damping of stayed cables in bridges under the wind or rain actions, a larger number of oscillations is expected per each working day. This contribution analyzes the fatigue behavior of a CuAlBe alloy (appropriate for earthquakes) and discusses the results of some available experiments on a NiTi alloy for their eventual application to stayed cables..

The particular properties of Shape Memory Alloys associated to their thermoelastic martensitic transformation with hysteresis permits applications of SMA as a damper via the conversion of the work absorbed in each cycle in heat. The guaranteed behavior requires the appropriateness of SMA for the complete requirements of the application. This work shows two complementary aspects of the SMA application in Civil Engineering, the first of them, the SMA dampers in earthquake damping of a family house. The second aspect relates an elementary approach to the damping of stayed cables in bridges, using some data from the Iroise Bridge. The application in the first case needs long time constancy of properties and then around 200 cycles during an earthquake. In the second case, the fatigue life of SMA imposes that only small strains in the alloy can be accepted. Finally, it is emphasized the importance of working conditions, including temperature and time.

Voltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing two effects: a degradation of performances mainly impacting gate delays and a noisy contamination of the quiescent levels of the logic that drives the node. Both effects are presented together, in this paper, showing than both are a cause of errors in modern and future digital circuits. The paper groups both error mechanisms and shows how the global error rate is related with the voltage deviation and the period of the clock of the digital system.

This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits. The analysis here considered gives the timing violation error probability as a new design quality factor in front of conventional techniques that assume the full perfection of the circuit. The evaluation of the error bound can be useful for new design paradigms where retry and self-recovering techniques are being applied to the design of high performance processors. The method here described allows to evaluate the performance of these techniques by means of calculating the expected error probability in terms of power supply distribution quality.

Several nanoelectronic devices have been already proved. However, no architecture which makes use of them provides a feasible opportunity to build a medium/large system. Nanoarchitecture proposals only solve a small part or the problems needed to achieve a real design. In this paper we review the two main approaches to nanoarchitectures showing some of their shortcomings. Taking into account these limitations, we propose and analyze a cell architecture that overcomes most of them. This architecture combines nanodevices with MOS technology to define a new architecture able to take advantage of both of them in a structure feasible for practical implementation. Using the cell structure we build 2 and 3-input NAND gates showing their error probabilities. Finally, we outline a method to further improve the structure's tolerance by taking advantage of interferences among nanodevices

This work presents an experimental investigation about the relation between specific characteristics of a digital circuit (clock frequency and architecture) and the substrate noise spectrum that it generates. Both the discrete impulse train term and the continuous term of the substrate noise spectrum are investigated. The results indicate that the continuous term sets an upper bound to the substrate noise reduction that may be obtained by changing the digital frequency or by staggering the simultaneous activity of the circuit, two techniques that have been proposed in the literature to reduce substrate noise.

Technology advances tend to reduce minimum dimensions and source voltages to maintain scaling rules. Both scaling trends make noise more critical, reduce yield and increase device parameter fluctuations. This paper presents a statistical model that permits the study of noise and parameter deviations on gates. Using this model stochastic resonance (SR) is studied both in single devices and arrays for subthreshold and suprathreshold input signals. The SR is measured by the signal-to-noise ratio (SNR) in the time domain and a modified SNR is proposed to take into account all the effects induced by noise in gates. With this measure subthreshold and suprathreshold SR is reviewed. Finally, a discussion of the possibility of considering noise a part of the electronic circuits is presented, suggesting that it could be a solution to some of the emerging problems in future nanotechnologies.

The application of Shape Memory Alloys (SMA) in mechanical engineering (ME) or in civil engineering (CE) requires the tuning of the physical properties with each particular need. When the target involves dampers for quakes in CE the number of full working cycles is relatively small (i.e. 200) but the application requires guaranteed behavior after several years of inactivity. On the contrary some devices in ME may need relatively high frequencies operating for a long period of time. In this work the mesoscopic effects in the SMA are quantified to ensure guaranteed behavior in the frame of dampers for CE applications. For instance, the actions of accumulated deformation in cycling and the changes induced by external temperature (i.e., summer-winter) are evaluated. Also, the perturbations induced by diffusive (induced by phase metastability, i.e. produced by microscopic interactions) are considered. In particular, the phase coexistence effects are visualized in Cu-based and partially in NiTi alloys. The practical creep induced by cycling and the coexistence actions are decisive in damping applications.

The particular properties of shape memory alloys (SMAs) are related to a martensitic transformation between metastable phases. Their applicability to dampers in civil engineering requires a fully guaranteed behaviour of the SMAs both on mesoscopic and atomic levels. The first one relates the thermomechanical properties (fracture, number of working cycles, summer-winter temperature effects and, for instance, self-heating associated with latent heat and the frictional work converted on heat) and the second one, the actions on the phase transition of the thermodynamic forces (temperature and stress). The properties of the CuAlBe alloy are explained and the characteristics of the NiTi alloy are outlined. By establishing an appropriate model the SMA dampers are introduced inside a structure and, via the ANSYS software, the dynamic response of the free and of the damped structure are obtained by simulation under the action of acceleration from the earthquakes available in the literatu re. As a conclusion, the conditions for the appropriateness of the dampers are given.

GEOGRAPHICAL DISTRIBUTION AND HOST PLANTS OF THE CACTUS MOTH, CACTOBLASTIS CACTORUM (BERG) IN PUERTO RICO AND THE UNITED STATES VIRGIN ISLANDS

The predicted deterioration of the component quality, due to the shrinking of components to near atomic scale, threatens the effectiveness and the applicability of conventional digital system design methodologies in the giga and tera-scale integration era. Three aggression sources support the previous statement: i) the increasing device parameter variability induced by the extreme reduction of the critical feature sizes and the intrinsic nature of new devices; ii) the intense and practically unpredictable internal noise; and iii) the large number of physical defects. This paper provides a detailed analysis of the noise and parameter variations effects on a basic processing gate. We derive formulas to calculate the expected value and the variance of the gate output under the effects of noise, threshold, and gain fluctuations. Using these expressions we also derive a cost-performance equation that evaluates the gate error probability from its parameter variability, noise, power, and area or redundance. The proposed model is generic for any computing gate in the current digital paradigm. To illustrate the model applicability we calculate the error probability curve for a 90 nm CMOS inverter showing that for this technology the noise is the main limiting factor. A tradeoff analysis of area-power-redundancy-reliability for nanogates is performed indicating that the use of nanoscale individual elements for fabricating gates in deep-nanoscale technologies may not be a viable option. The results clearly suggest that the use of redundant structures is necessary and that averaging structures with mid-high redundancy factors may constitute a reasonable solution for building reliable nanoscale gates.