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A poly-Si nanowire (NW) thin-film transistor configured with the double-gated scheme was fabricated and characterized. The fabrication process features the clever use of selective plasma etching to form a rectangular NW underneath a hard mask. In this paper, we show that replacing the original ion-implanted poly-Si with in situ doped poly-Si for the source/drain significantly enhances the device performance, including steeper subthreshold swing (SS), larger on/off current ratio, and reduced series resistance. In particular, the SS is improved to a record-breaking low value of 73 mV/dec, which, to the best of our knowledge, is the most ideal ever reported for a poly-Si based device. The new NW transistors with such excellent switching properties are highly promising for reducing power consumption and operational voltage in practical circuit applications.

A new method is proposed and demonstrated to fabricate planar thin-film transistors and trigated nanowire (NW) devices simultaneously on the same panel. By using an oxide-nitride-oxide stack as the gate dielectric, the NW devices could also serve as nonvolatile Si-oxide-nitride-oxide-Si (SONOS) memory devices. Our results indicate that the combination of trigate and NW channels help to improve the device performance in terms of steppers subthreshold swing and reduced threshold voltage. Improvement in programming and erasing efficiency of the nonvolatile SONOS memory devices is also demonstrated with the trigated NW structure.

Several types of poly-Si nanowire (NW) thin-film transistors (TFTs) with multiple-gated (MG) configuration were demonstrated and characterized. These devices were fabricated with simple methods without resorting to costly lithographic tools and processes. The fabricated trigated devices show a low subthreshold swing (SS) of around 100 mV/dec and on/off current ratio higher than 108. These results clearly indicate the effectiveness of MG scheme in enhancing the device performance. Furthermore, a multiple-channel scheme was demonstrated to further increase the drive current without compromising device performance. Finally, the impact of MG on the variation of NWTFT characteristics is investigated with a clever method that allows the fabrication of test structures with identical NW channel but different gate configurations. The results clearly show that the variation could be reduced by increasing the portion of NW channel surface that is modulated by the gate.

A new method is proposed and successfully demonstrated for the fabrication of polycrystalline silicon (poly-Si) nanowire (NW) transistors with rectangular-shaped NW channels and two independent gates. The two independently controllable gates allow higher flexibility in device operation and provide a unique insight into the conduction mechanism of the NW device. Our results indicate that dramatic performance enhancement is feasible when the thickness of the NW channel is sufficiently thin, and the two conduction channels in the NW structure are operating simultaneously.

A novel Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain (FID) extension is proposed and demonstrated. In the new device configuration, a metal field-plate (or sub-gate) lying on the passivation oxide is employed to induce a sheet of carriers in a channel offset region located between the silicided drain and the active channel region underneath the main gate. The new device thus allows ambipolar device operation by simply switching the polarity of the bias applied to the field plate. In contrast to the conventional SBTFT that suffers from high GIDL (gate-induced drain leakage)-like off-state leakage current, the new SBTFT with FID is essentially free from the GIDL-like leakage current. In addition, unlike the conventional SBTFT that suffers from low on-off current ratio, the new device exhibits high on/off current ratio up to 10/sup 6/ for both n- and p-channel modes of operation. Moreover, the implantless feature and the ambipolar capability of the new device also result in extra low mask count for CMOS process integration. These excellent device characteristics, coupled with its simple processing, make the new device very promising for future large-area electronic applications.

In this letter, a novel thin-film transistor with a self-aligned field-induced-drain (SAFID) structure is reported for the first time. The new SAFID TFT features a self-aligned sidewall spacer located on top of the drain offset region to set its effective length, and a bottom gate (or field plate) situated under the drain offset region to electrically induce the field-induced-drain (FID). So, unlike the conventional off-set-gated TFTs with their effective FID length set by two separate photolithographic masking layers, the new SAFID is totally immune to photomasking misalignment errors, while enjoying the low off-state leakage as well as high turn-on characteristics inherent in the FID structure. Polycrystalline silicon TFTs with the new SAFID structure have been successfully fabricated with significant improvement in the on/off current ratio.

Si nanowire (NW) SONOS devices have recently been demonstrated as a good candidate for high-density non-volatile memory application [1][2]. Owing to the high surface-to-volume ratio of the NW channel, the programming and erasing (P/E) operation of the device could be performed at a lower voltage and much faster speed over the planar counterpart [2]. However, the fabrication of NW devices typically requires advanced lithographic tools and/or complicated process flow. These are not compatible with the manufacturing of flat-panel products where the device feature size is generally several microns or larger. In this work, we propose a simple and cost-effective approach to integrate planar poly-Si thin-film transistors (TFTs) and tri-gated poly-Si NW SONOS devices without resorting to advanced lithographic tools. Greatly enhanced P/E speed with the use of NW structure is clearly demonstrated.

A simple method for fabricating poly-Si nanowire (NW) TFT with multiple gates is proposed and characterized. In this structure, NW is formed mainly using both anisotropic and highly selective isotropic plasma etching. It is found that when the size of NW is scaled down, double-gated operation provides more improvement. Furthermore, by utilizing this unique independent double-gated configuration, the function of threshold voltage modulation is investigated.

Multilayer titanium photonic crystals are fabricated with the mature integrated circuit (IC) technology, which is similar to the Damascene interconnect process. The photonic crystals that we created have the face-centered-tetragonal lattice symmetry. In each layer, the feature size, height and the spacing of the titanium rods is 100 nm, 200 nm and 300 nm, respectively. To our knowledge, this is at the first time that the three-dimensional titanium photonic crystals are realized successfully with 100-nm line width. The reflectance spectra of three- and four-layer titanium photonic crystals are measured with the Fourier-transform infrared spectroscopy and simulated with the three-dimensional finite different time domain method. Through both the experimental observation and the calculation verification, the characterization of the photonic band gap is demonstrated at near-infrared wavelengths and the optical behavior of titanium photonic crystals is discussed for incident light waves of s- and p-polarization. Moreover, the absorption spectra are derived from the reflectance and transmittance spectra due to the law of conservation of energy. It is found that absorption near the photonic band edge is modified and enhanced in a narrow bandwidth because of the well-known recycling-energy mechanism. The large band gap can suppress black body radiation in the mid-infrared range and recycle energy into the near infrared. According to Kirchoff's law, the absorptance of a body equals its emissivity. Thus, the multilayer titanium photonic crystals would be applied as an efficient near-infrared light source with a narrow bandwidth, and produced on a mass scale with the standard IC technology.