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Channel emulator is an important tool to evaluate communication system performance at the physical link, and network levels. In this paper, a new discrete 3D non-stationary geometry-based stochastic model (GBSM) for UAV to vehicle (U2V) channels is proposed, which considers 3D scattering space, 3D trajectory, and 3D antenna array. And a tailed channel emulator is developed on a field programmable gate array (FPGA) platform. All channel parameters, i.e., the power, delay, and phase are calculated by FPGA hardware for the first time instead of software or pre-storage method. Meanwhile, a Greedy CORDIC-based exponential calculation method for generating massive complex sinusoids is designed and implemented. The latency is reduced by 50% than traditional CORDIC method. By further utilizing the compact architecture with time division scheme, the hardware resource is significantly reduced from 16.51% to 7.55% for 16-bit data width. Meanwhile, the fixed-point output statistical properties are also derived for quantitatively validation. Finally, the U2V channel under the campus scenario is reproduced by the proposed emulator. The generated results demonstrate that the statistical properties are consistent well with the theoretical and ray tracing ones, which verifies the correctness of both proposed channel model and emulator.

This work explores hardware-oriented optimizations for the CORDIC (COordinate Rotation Digital Computer) algorithm investigating the power-efficiency improvements employing N-point Fast Fourier Transform (FFT) hardware architectures. We introduced three hardware-oriented optimizations for the CORDIC: (a) improving the signal extension, (b) removing the angle accumulation and (c) eliminating the redundancies in the iterations, both unnecessary when processing the FFT processing. Fully sequential FFT architectures of 32, 64, 128, and 256 points were synthesized employing ST 65 nm standard cell libraries. The results show up to 38% of power savings on average when using our best CORDIC optimization proposal to the FFT architecture comparing to the explicit multiply-based butterfly version. Moreover, when combining our best CORDIC optimization with the clock-gating technique, the power savings rises to 78.5% on average for N-point FFT.

This paper proposes a low-complexity method and architecture to compute the logarithm of complex numbers based on coordinate rotation digital computer (CORDIC). Our method takes advantage of the vector mode of circular CORDIC and hyperbolic CORDIC, which only needs shift-add operations in its hardware implementation. Our architecture has lower design complexity and higher performance compared with conventional architectures. Through software simulation, we show that this method can achieve high precision for logarithm computation, reaching the relative error of 10−7. Finally, we design and implement an example circuit under TSMC 28nm CMOS technology. According to the synthesis report, our architecture has smaller area, lower power consumption, higher precision and wider operation range compared with the alternative architectures.

Microwave interferometry has been used extensively for plasma diagnostics in tokamak for real-time electron density measurements. Real-time density measurement is an indispensable part of advanced tokamaks, as it can be used as feedback to control the plasma operation. In this article, we report the development of the phase extraction method in a heterodyne interferometer for real-time density estimation using a field-programmable gate array (FPGA). FPGA provides parallel processing, minimum control delay, more efficient processing architecture, and jitter-free synchronization between different control layers. Digital CORDIC algorithm is used for the estimation of the phase between two arms of the interferometer. A LabVIEW program is developed for the FPGA target and host controller to acquire the data and estimate electron density in real time, which can be used for feedback purpose by regulating the amount of gas injection using piezoelectric valve that requires a high voltage (~100 V) for about 1 ms. The delay in generating the feedback signal is proportional to the sampling speed (100 kHz) of the analog signal. In this work, line-averaged electron density measurement using digital signal processing (DSP) and LabVIEW-FPGA technology is presented. The developed interferometer and data acquisition (DAQ) system installed on ADITYA-U tokamak can measure the electron density in the range of $1 \times 10^{18} - 1 \times 10^{20}\,\,\text{m}^{-3}$ . The algorithm used for the estimation of phase difference is validated using a conventional arctan method. The developed reconfigurable FPGA-based DAQ system uses low power, has a reconfigurable hardware structure for fast real-time signal processing, and can be easily upgraded.

In this work, we proposed a novel Coordinate Rotation DIgital Computer (CORDIC) rotator algorithm that converges faster by performing radix-2,4 and 16 CORDIC iterations while maintaining the scale factor implicitly constant. A mixed-radix is used to achieve convergence faster to reduce the computational latency of the CORDIC algorithm. The main concern of the higher radix CORDIC algorithm is the compensation of a variable scale factor. To solve this problem, the Taylor series approximation of sine and cosine is proposed for a higher radix CORDIC algorithm to achieve the scaling-free rotation of the two-dimensional vector. The scaling-free rotation of the proposed CORDIC algorithm removes the read-only memory (ROM) needed to store scale factor of higher radix CORDIC algorithm. Further, the proposed CORDIC algorithm is designed in rotation mode and optimized by removing the Z datapath for the digital signal processing (DSP) applications for which the angle of rotation is known in advance. Finally, the multipath delay commutator (MDC) fast Fourier transform (FFT) algorithm is implemented with the proposed CORDIC algorithm based rotator on FPGA. The proposed design is compared with existing designs. In a comparison between the radix-16 CORDIC rotator based FFT implementation and our proposed implementation, it has been found out that implementation proposed in this article has used 17% fewer resources.

The universality of computerized signal handling (DSP) has made expanding request to create territory effective and precise structures in completing numerous nonlinear math tasks. One such design is CORDIC unit which has numerous applications in the field of DSP including actualizing changes dependent on Fourier premise. This paper offers structure of CORDIC, inserted with a pipelined unit that has exclusively negligible scope of adders and shifters. It tends to be applied in pivot mode as appropriately as vectoring mode. The reason for the arrangement is to get a pipelined CORDIC unit keeping up the format of valid calculation. Preparing and discussion structures work CORDIC in round organize contraption and in both of pivot or vectoring modes.

In this study, a hardware design that is micro-sized and capable of parallel processing is proposed for the solution of the most basic engineering problem required to control a serial robot manipulator. The proposed hardware design is in the form of FPGA-based digital circuit and has been realized in two different ways, serial and parallel. Forward kinematics problem solution of a 7-joint serial robot manipulator was used for the testing of the designed hardware. In order to the test results to be more objective, the same components were used for multiplication, division and trigonometric calculations in both series and parallel designs. IP-Core is used for multiplication and division operations, and Cordic algorithm is used for trigonometric calculations. The analysis of the results was carried out comparatively in terms of circuit size and solution time. As a result of the experiments, it has been clearly seen that though parallel architecture is more costly than serial architecture, it creates a difference of up to ten times in terms of time.

Central pattern generators (CPGs) are dedicated neural circuits which can generate rhythmic motor patterns even in absence of sensory input with extraordinary robustness and flexibility. In this paper, a biologically realistic model of a respiratory CPG with four neurons is implemented on a reconfigurable Field-Programmable Gate Array (FPGA) system. Considering the limitations of hardware resources, we first propose a modified respiratory CPG model with Coordinate Rotation Digital Computer (CORDIC) algorithm to save limited resources and reduce complexity. And then, all the multipliers are replaced with a method which is appropriate and effective for hardware implementation to avoid the use of the area-intensive multipliers. The implementation results show that rhythmic oscillations are successfully generated by the respiratory CPG network and the resource utilization is greatly reduced, which shows the potential for building large-scale spiking neural networks. The proposed high-performance and real-time implementation of the respiratory CPG network on the FPGA system can speed up the process to gain new insights into the respiratory network and can also be developed into applications for respiratory rhythm generation and modulation.

This paper briefly introduces the basic principle of the CORDIC algorithm, gives the specific design and implementation method of the general CORDIC soft core in the project based on the background application of Space-borne payload processing. The actual application shows that the design method can be used to process the signals that the conventional design method needs a lot of resources to achieve under the more demanding requirements of the hardware and software platform Application scenario.

This paper proposes a new variant of the projection approximation subspace tracking (PAST) algorithm with multiple deflation (MD) and its efficient hardware architecture. It extends the PAST with deflation (PAST-d) algorithm by performing multiple deflations at each step and relies on a recently introduced variable forgetting factor, and variable regularized PAST algorithm to improve the overall convergence rate, steady-state error, and numerical properties. It shares the same simple hardware structure of the PAST-d algorithm in pipeline realization but offering a more flexible tradeoff between complexity and performance. Moreover, methods for estimating the eigenvalues and the dimension of the signal subspace are proposed. Novel simplifications of the proposed variable forgetting factor (VFF) and variable regularization (VR) PAST-MD algorithm are also developed to avoid the expensive cubic root and division operations involved to facilitate its hardware implementation. Moreover, a combined data-regularization update is introduced to avoid the additional QR decomposition (QRD) update associated with the regularization, at the expense of very slight performance degradation. A novel pipelined hardware implementation of the simplified VFF-VR-PAST-MD algorithm based on the QRD and the COordinate Rotation DIgital Computer (CORDIC) is also proposed and implemented in Xilinx field programmable gate array (FPGA). Thanks to the proposed “root- and division- free” schemes, our proposed architecture can achieve around 20.2% higher working speed and save 1.9% lookup tables (LUTs), 1.8% slice register, and 22.8% digital signal processors (DSPs) over conventional implementation of the proposed architecture. Compared to the previous work, which is based on PAST-d algorithm, the proposed QRD-based algorithms offer better performance and a more flexible tradeoff between hardware resources and performance.

Transform model estimation (TME) is a geometric operation, widely utilized in real-time imaging systems. Considering the massive computational load of matrix algebra-based TME realizations, most of the imaging systems resort to highly paralleled software-platform-based TME execution, which is power-intensive and expensive. Due to low-speed and power intensiveness, existing hardware for TME is not capable enough to meet the requirements of real-time systems. In this article, a hardware-realizable method of three-degree-of-freedom TME is formulated encompassing both the conventional CORDIC and the proposed modified CORDIC. The novelties of the proposed TME method and the corresponding architecture are that its latency sublinearly varies with the precision and the total computation time (CT) is almost independent of the input image sizes. The performance of prototype 16-bit fixed-point TME architecture (realized using VHDL in Xilinx Vivado 18.2) is compared with the software-counterpart. The proposed TME hardware is utilized along with other standard hardware modules to realize image registration (IR) operation. The proposed IR architecture achieves, on average, 60% reduction in total CT, $1.61 \times $ increase in maximum operating frequency with a comparable accuracy, only at the cost of 23% increase in power consumption with respect to other existing IR hardware.

We present a CORDIC (Coordinate Rotation Digital Computer)-based method to compute the logarithm function with base 2 and validate this method by software simulation and hardware implementation. Technically, we overcome the limitation of traditional hyperbolic CORDIC and transform it based on the idea of generalized hyperbolic CORDIC so that it can be used to compute $log_{2}x\;(x\;\epsilon \;[1,2))$ . The proposed method requires only simple shift-and-add operations and has a great tradeoff between precision (or speed) and area. In MATLAB, we provide different precisions corresponding to the iterations of the transformed CORDIC for user needs. Using a pipelined structure and setting the number of iterations to be 16 (the average relative error is $2.09\times 10^{-6}$ ), we implement an example hardware circuit. Synthesized under the SMIC 65nm CMOS technology, the circuit has an area of 24100 $\mu m^{2}$ and computation time of 11.1 ns, which can save 31.04% area and improve 6.92% computation speed averagely compared with existing methods.

Digital communication plays a vital role in today’s communication system in this electronic world. However, the applications of digital communication are limited due to the requirements of antenna ...

Coordinate rotation digital computer (CORDIC) is widely used in digital signal processing (DSP) to calculate functions. One of the elegant ways to accelerate CORDIC is employment of the redundant binary signed-digit (BSD) number systems, so-called BSD-CORDIC. This paper aims to achieve efficient BSD-CORDIC structures for generic/specific initial angles. First, three generic BSD-CORDIC algorithms are optimized by exploiting a suitable data gating technique as well as appropriate BSD encodings. The synthesis results demonstrate that for generic CORDIC, the proposed BSD-CORDIC schemes enhance the existing ones in terms of speed, power consumption, and area overhead. Second, the look-ahead BSD-CORDIC is proposed as a special case of BSD-CORDIC with specific initial angles. We also show that for the applications like fast Fourier transform (FFT), where the initial angles are known in advance, the proposed look-ahead BSD-CORDIC with the posibit-negabit encoding, as our best presenting structure, noticeably improves speed, power consumption, and area overhead.

The fast Fourier transform (FFT) is an algorithm widely used to compute the discrete Fourier transform (DFT) in real-time digital signal processing. High-performance with fewer resources is highly desirable for any real-time application. Our proposed work presents the implementation of the radix-2 decimation-in-frequency (R2DIF) FFT algorithm based on the modified feed-forward double-path delay commutator (DDC) architecture on FPGA device. Need for a complex multiplier to carry out the multiplication of complex twiddle factors and large memory to store the twiddle factors are the main concerns for FFT implementation. Propose work aims to address these issues. In this work, a high-performance radix-16 COordinate Rotational DIgital Computer (CORDIC) algorithm based rotator is proposed to carry out the complex twiddle factor multiplication. Further, CORDIC needs only rotational angles to carry out complex multiplication, which reduces the need for large memory to store the twiddle factors. To compute the total rotation for n-bit precision, our proposed radix-16 CORDIC algorithm takes n/4 iteration as compared to n iteration of the radix-2 CORDIC algorithm. Our proposed architecture of the radix-2 decimation-in-frequency (R2DIF) algorithm is implemented on a Virtex−7 series FPGA. Further, the detailed comparison is presented between our proposed FFT implementation and other recently proposed FFT implementations. Experimental results suggest that proposed implementation has less latency and hardware utilization as compared to recently proposed implementations.

In this article, a high-throughput, high-accuracy, area-efficient, and energy-efficient digital outphasing modulator (OPM) is proposed for millimeter-wave transmitters. This digital OPM is entirely based on the fixed-point unrolled and pipelined radix-2 COordinate Rotation Digital Computer (CORDIC) algorithm, which is suitable for outphasing transmitters based on both IQ and phase modulation architectures. The outphasing angle is calculated by a mixture of single-CORDIC and double-CORDIC algorithm, which significantly reduces the critical path delay. Due to architectural advantages, its error performance, sampling rate, power efficiency, and area efficiency are improved. According to FPGA implementation measurements, this architecture enables a 12-bit OPM to achieve error vector magnitude (EVM) of 0.062% and peak sampling rate of 0.74 GSample/s. According to the postlayout spice-level simulation in 65-nm CMOS, a high-throughput version can work at a peak data rate of 1.85 GSample/s at 1-V supply. A low-power version reduces the area consumption to only 0.088 mm2, consuming 28.1 pJ/Sample at 0.78 GSample/s at 0.8-V supply. The proposed high-throughput OPM with the minimized area is expected to further open up an application area of energy-efficient low-cost millimeter-wave transmitters.

The Coordinate Rotation Digital Computer algorithm (CORDIC) is a simple mechanism to compute a set of elementary functions, such as trigonometric functions, using fixed-point devices. It is widely adopted, also in applications running in harsh environments such as space, where radiation is a cause of errors in nanoelectronic devices. A single event upset in a configuration bit of a Field Programmable Gate Array (FPGA) can completely change the behavior of the implemented circuit, so it is important to detect and reconfigure the FPGA when this happens. Dual modular redundancy is the typical method to detect errors in electronic circuits, but it has an important overhead in area and power consumption and it does not provide any additional functionality apart from the activation of the FPGA reconfiguration trigger in presence of error. This paper presents two ad-hoc techniques to protect the Digital Direct Synthesizer with CORDIC when it is implemented into an FPGA, with limited overhead in terms of area and power consumption when compared with the traditional solution. The first solution slightly increases the percentage of undetected errors, about 11%, reducing to almost half the area overhead of the circuit. The second solution introduces a trade-off between the percentage of error detection and the precision of the trigonometric output of the CORDIC by means of a polymorphic structure with lower area resources than the existing solutions. This last proposal allows the system to increase the precision of the digital synthesis signal under absence of errors or to activate the error protection in scenarios with external disturbances such as radiation.

CORDIC algorithm is used for low-cost hardware implementation to calculate transcendental functions. This paper proposes a low-latency high-precision architecture for the computation of hyperbolic functions sinhx and coshx based on an improved CORDIC algorithm, that is, the QH-CORDIC. The principle, structure, and range of convergence of the QH-CORDIC are discussed, and the hardware circuit architecture of functions sinhx and coshx using the QH-CORDIC is plotted in this paper. The proposed architecture is implemented using an FPGA device, showing that it has 75% and 50% latency overhead over the two latest prior works. In the synthesis using TSMC 65 nm standard cell library, ASIC implementation results show that the proposed architecture is also superior to the two latest prior works in terms of total time (latency × period), ATP (area × total time), total energy (power × total time), energy efficiency (total energy/efficient bits), and area efficiency (efficient bits/area/total time). Comparison of related works indicates that it is much more favorable for the proposed architecture to perform high-precision floating-point computations on functions sinhx and coshx than the LUT method, stochastic computing, and other CORDIC algorithms.

This poster presents a 32-bit Reduced Instruction Set Computer five (RISC-V) microprocessor with a COordinate Rotation DIgital Computer (CORDIC) algorithm accelerator. The implemented core processor is the VexRiscv CPU, an RV32IM variant of the RISC-V ISA processor. Within the VexRiscv core, the CORDIC accelerator was connected directly to the Execute stage. The core was placed in Briey System-on-Chip (SoC) and was synthesized on Field Programmable Gate Array (FPGA) and on Application Specific Integrated Chip (ASIC) level with the cell logic of ROHM- 180nm technology

The SoftMax activation function is a normalized exponential function that is usually used as an activation function of the last layer of a fully connected neural network. The number of neurons in this layer represents the number of classes. The SoftMax activation function is used to normalize the network outputs to a probability distribution over predicted output classes. In this paper, a multi-rate input SoftMax activation function has been designed and built on FPGA. The unit can read 4 or 2 consecutive inputs or one input, every predefined number of cycles. A ROM design has been utilized to determine the exponential part of the function, while the Coordinate Rotation Digital Computer (CORDIC) reciprocal algorithm has been used to calculate the reciprocal of the sum of the input exponential. Hardware multipliers have been used to calculate the SoftMax output. Unit optimization is achieved by pipelining on the input and output stages. The unit can be configured and controlled by an ARM microcontroller as a complete System-on-Chip (SoC) built on Field Programmable Gate Array (FPGA).

An efficient way of obtaining trigonometric, hyperbolic, linear, and logarithmic is provided by the CORDIC algorithm. In this algorithm bit shifting operation replaces multiplication and iterative addition will result in accurate values of such trigonometric functions. Not only it is saving the area but also improves the throughput. This algorithm has become a widely researched area in the field of vector rotated DSP applications. This paper explores the basic CORDIC algorithm and implements it on FPGA using VHDL coding. Uniqueness in the proposed CORDIC algorithm is that 4-bit input will cover all the values of angle in four quadrants having a resolution of 22.5°. Using recent technology, we can have to utilize more hardware in order to achieve speed constraints. A serial iterative CORDIC uses less hardware with more latency so, here to have high throughput parallel iterative hardware is used. But The bit-parallel variable shift shifters require high fan-in. As FPGA provides both flexibility as well as speed it is much better choice for implementing CORDIC algorithm. The proposed CORDIC algorithm is simulated on Vivado 2019.2 and implemented on the Xilinx Spartan 3E board. The simulation results which are shown below verify the authenticity and validity of the designed CORDIC algorithm.

The authors have proposed a robust linearisation method for determining the angles of sinusoidal signals generated by gratings. This scheme solves the problem of non-linear subdivision by compensating sinusoidal signal. The conventional coordinate rotation digital computer (CORDIC) algorithm is optimised by double-rotation iteration, and the calculation accuracy of arcsine and arccosine functions is improved. A pipeline preprocessing circuit based on the CORDIC is designed for the signal compensation and digital subdivision. The two processes are implemented on a field-programmable gate array chip, which exhibits a wide input range and good dynamic response. A theoretical analysis using stable signals from a function generator verifies that the subdivision system achieves the ideal subdivision effect. The subdivision system is further applied to an angle-measuring device for a 16,384-line circular grating. The results of subdivision exhibit good linearity for the grating moire signal. Compared to the angular measurement by a laser interferometer within the three grating lines, the angle-measurement accuracy of ±0.000138° (0.5″) and the relative error is ±0.63% over a travel angle of three grating lines. Notably, the measurement error of the subdivision system is only half of that in a similar commercial product (MicroE system).

In this brief, a silicon-on-thin-BOX (SOTB) implementation of single-precision floating-point fast-Fourier-transform (FFT) twiddle factor (TF) is presented. The architecture of the proposed TF is developed based on the adaptive method of the coordinate rotation digital computer (CORDIC) algorithm. The 65-nm SOTB technology was chosen because of its ultra-low-power advantage. Furthermore, the back-gate bias technique can be applied on an SOTB chip to adjust the operation for high-performance or low-power requirement. The layout of the SOTB 65-nm TF core is about 22869 gate-count on the die area of 86721 $ \mu \text {m}^{2}$ . The measurement results show that the core reached its highest operating frequency of 55 MHz at the 1.2-V supply voltage (VDD) with the forward back-gate bias (FBB) ≥ 1.5 V. The power and energy consumptions at this point were 1.54 mW and 27.91 pJ/cycle, respectively. The lowest operating VDD was at 0.5 V with the FBB ≥ 0.5 V. In the standby mode, when the clock-gating technique was deployed, the leakage current can be reduced to 0.4 nA at the 0.4 V VDD and −2.5-V reverse back-gate bias (RBB).

Fast Fourier transform (FFT) is a significant technique in the digital signal processing (DSP). The intrinsic weak point of the primary designs of FFT was the use of multipliers. CORDIC is the most prevalent method to replace the multipliers of FFTs. In order to enhance the speed of CORDIC, redundant binary signed-digit (BSD) encodings can be utilized, so-called BSD-CORDIC. The main goal of this paper is to improve the efficiency of BSD-CORDIC-based FFT. The redundant improved composed (RIC) CORDIC is proposed as a novel BSD-CORDIC. The main idea behind the RIC CORDIC lies in prior determination of the required iterations in such a way that the maximum number of iterations is reduced, which results in speedup and decrease in hardware resources. Also, some of the iterations still can be skipped, which leads to further reduction in the power consumption. The synthesis results demonstrate that the FFT based on the RIC BSD-CORDIC enhances speed, power consumption, and area overhead.

A common approach to model kinematics for robot manipulators uses functions such as sin(), cos() and atan(),however, the rational trigonometry allows to exclude the use of these transcendental functions. Most of the computing processing to control a manipulator is dedicated to solving its kinematics, therefore, reduce the complexity of kinematic equations leads to a more compact and efficient model. In this paper, we propose a geometric analysis to solve the kinematics of robot manipulator of up to three degrees of freedom, avoiding the use of transcendental functions in the kinematic equations. We present three kinematic models for the mechanism positions and theirimplementations in an FPGA. The experimental results show that our proposed models: 1) use less logic elements compared with an implementation based on parallel CORDIC and 2) has lower latency respect with iterative CORDIC implementation.

This paper presents a high-speed ASIC implementation of the tanh activation function (AF) for artificial neural network. The proposed architecture for tanh AF is designed using a highspeed cascade Coordinate Rotation DIgital Computer (CORDIC) to implement hyperbolic and division functions. CORDIC processing is accelerated by fixing the angle of rotation and removing parameters related to the direction of rotation. The proposed architecture was coded in Verilog hardware description language and synthesized by Synopsys Design Compiler using a 90-nm CMOS standard cell library. The implementation results show an improved area-delay product compared to the existing architectures.

As the existing complex number Nth root computation methods are relatively discrete, we propose a general method and architecture based on coordinate rotation digital computer (CORDIC) to compute arbitrary complex number Nth root for the first time. Our method performs the tasks of computing complex modulus, complex phase angle, real Nth root, sine function and cosine function, which can be implemented by circular CORDIC, linear CORDIC and hyperbolic CORDIC. Based on these CORDICs, our proposed architecture can not only improve the hardware efficiency just through shift-add operations, but also flexibly adjust the precision and the input range of complex number Nth root. To prove its feasibility, we conduct a software simulation and implement an example circuit in hardware. Under the TSMC 28nm CMOS technology, we synthesize it and get the report that it has the area of 6561μm2 and the power of 3.95mW at the frequency of 1.5GHz.

Advanced Driver Assistance System (ADAS) and Artificial Intelligent (AI) are the important issue in recent years, autonomous car plays an important role in whole ADAS. To detect the environment surround the car, the sensor might be sensitive and immediate. LiDAR (Light Detection and Ranging) uses Laser to get the reflectivity from the surrounding objects. For clustering the objects with point cloud, the density of the point cloud still sparse, making the cluster result completely, we implement a system combines LiDAR and multi-view image, the depth image is generated by multi-view can help us to cluster the object in point cloud clearly. In addition, we use CORDIC (Coordinate Rotation Digital Computer) EEAS (Extended Elementary Angle Set) architecture to decode the package data that collected from Velodyne HDL-64E. By using the flow of digital chip design, we reduce the power consumption and accelerate the speed. The proposed system achieves 91.09% accuracy and the processing time is 0.757 second.

In this paper, a discrete non-stationary multiple-input multiple output (MIMO) channel model based on the sum of linear frequency modulation (SoLFM) method is proposed. The new model is suitable for generating non-stationary fading with continuous phase and accurate Doppler frequency. In order to implement the proposed model with large-scale antennas by field-programmable gate array (FPGA) platform, an efficient coordinate rotation digital computer (CORDIC) method is proposed. By introducing a full parallel pipeline architecture, rotation factor state, and domain folding technique, the new generator can significantly reduce the hardware resource usage and meet the requirement of large-scale channel emulation. The measurement and analyze results show that the statistical properties, i.e., the probability density function (PDF) and autocorrelation function (ACF) of generated channels provide a good agreement to the theoretical ones.

The human brain usually generates brain wave signals used for medical research to study the state of the human body. Most common diseases like seizures, insomnia, or other diseases such as brain tumors can be diagnosed using brain wave signals captured with a device's help. Apart from these, nowadays, many devices are invented that operates with brain signals for people with disabilities. And now, in this paper, we will use brain signals for authenticating high-security devices using a network since secondary damage cannot be caused in brain wave signals like generated in a fingerprint, iris, face, etc. Brain wave serves as high-security biometric data. However, brain signals can also be hacked once captured by a malicious personality [14]. Here we will encrypt Brain wave signal with an advanced FFT architecture that incorporates the Cordic system in it. His method enhances high-security transmission of Brain signals over the network for authenticating a high-security device.

With different constraint length (K), time scale, and code rate, modified MAP (maximum a posteriori) decoder architecture using folding technique, which has a linear life time chart, is developed, and dedicated turbo codes will be placed in a network-on-chip for various wireless applications. Folded techniques mitigated the number of latches used in interleaving and deinterleaving unit by adopting forward and backward resource utilizing method to M-2, where M is the number of rows and end-to-end delay get reduced to 2M. By replacing conventional full adder by high speed adder using 2 x 1 multiplexer to calculate the forward state metrics and reverse state metrics will minimize the power consumption utilization in an effective manner. In s similar way, CORDIC (Coordinated ROtation DIgital Computer) algorithm is used to calculate the LLR value and confer a highly precise value with less computational complexity by means of only shifting and adding methods.

In present, this era is based on 5G and advance computer vision; computer vision at present there is lots of mobile user are increase due to that there is need of fast processing unit which is able to represent video or audio data on any mobile usage in very less time. As we know in any processor, ALU unit is there which will perform the arithmetic operation but now days for all trigonometry-based calculation, there is need of CORDIC processor. Most of the computer vision algorithms need the computation consisting of two steps—namely arithmetic computation and trigonometric computation. The complexity is mostly by the trigonometric computations, which generate a need for separate algorithms which perform the entire trigonometric task. In this work, one well-known algorithm called Coordinate Rotation Digital Computer (CORDIC), alternatively known as digit by digit technique, and Volder’s calculation has been addressed. In this, a novel processing strategy is utilized which is particularly reasonable for understanding the trigonometric connections associated with plane organize revolution and change from rectangular to polar directions. CORDIC calculation is additionally appropriate for square root, logarithmic, exponent capacity, and for computer-based computations.

Aiming at the problem that SPLL (Software Phase Locked Loop) operation is slow and CORDIC (Coordinate Rotation Digital Computer) algorithm is susceptible to interference, an AC voltage phase and amplitude detection system based on SPLL and CORDIC is proposed. Using DSP (Digital Signal Processor) to run code of SPLL algorithm and FPGA (Field Programmable Gate Array) to run CORDIC algorithm circuit, the phase and amplitude of three phase AC voltage obtained by two chips are processed in DSP to improve the detection accuracy of phase and amplitude, thereby improving the control accuracy of parallel algorithm of auxiliary inverters for rail vehicles, and the phased-locked time is reduced.

This work proposes a Red Green Blue (RGB) image encryption and decryption digital system which uses random number sequence generators as core and also provides its internal architectural layout. SC-CNN (State Controlled Cellular Neural Network) based chaotic system which stands optimal in generating multi-scroll chaotic generators is inculcated in this system. The hyperbolic tangent function used in state equations of the chaotic generator is implemented via CORDIC (Coordinate Rotational Digital Computer) algorithm, which is an efficient algorithm to compute various trigonometric and hyperbolic functions. The above techniques are combined together to give hardware credibility to the scheme described. The randomness and the level of encryption are analyzed and validated with the help of multiple test inputs and corresponding encrypted outputs. The complete encryption and decryption flows are simulated using Xilinx Vivado 2019.1 and realized on FPGA (Field programmable gate array), Zynq 7 board, as the chosen device.

Vagus nerve stimulation, an emerging technology for the treatment of many neurological diseases, is considered an alternative to medical treatment and surgical treatment. This paper introduces the circuit implementation of the SVM (Support Vector Machine) module in the neural signal monitoring chip classifier. The support vector machine module includes an exponential function operation unit and a scaling unit. The exponential function operation circuit is designed based on the coordinate rotation digital calculation method (CORDIC). In order to reduce the amount of computation, some of unimportant or redundant features are removed from the complete feature set by selecting the patient’s EEG (electroencephalogram) signal path. In addition, the decision function is transformed to optimize the transmission path of the data. Finally, the indicators for evaluating this system are given by the simulation results.

Shifters usually play an important role in all the operations in VLSI computer systems. For example, barrel shifter is a fundamental block of many computing systems due to its operational operation that it can shift and rotate various multiple bits in one cycle. The barrel shifter can also be replaced for arithmetic and the logical shifters as it uses the rotation of the data. It also provides both the shifting of right and left arithmetically and logically. The design is purely MUX-based, and therefore, designing a MUX for low power to use it as a repetitive block in the barrel shifter will improve its efficiency. In this paper, an 8-bit barrel shifter using multiplexers (MUX) is implemented and is designed in cadence tool for demonstrating in power and its functional operations. The paper analyzes and optimizes the area and power of the barrel Shifter in 180 nm technologies. Cadence Virtuoso tool is used for implementing the block.

In ultrasonic phased array nondestructive testing system, CORDIC is used to optimize the algorithm of key function calculation or data processing in ultrasonic phased array instrument. This paper focuses on the research of ultrasonic phased array FPGA signal processing technology based on CORDIC algorithm, focusing on the ultrasonic echo orthogonal demodulation technology, dynamic FIR filtering technology, time gain control technology. It can reduce the hardware complexity of ultrasonic phased array instrument system, speed up the detection speed and improve the detection accuracy. After the system comprehensive test, the ultrasonic phased array system designed in this paper meets the requirements of industrial application.

As we know, the world today is based on 5G and 3D technology, where everyone needs a fast processing unit for mobile applications. CORDIC is an approach that is capable of performing trigonometric calculations in a fraction of time. As for the old processing unit, they have only a computing unit which contains only ALU, but which is not sufficient for the rapid processing of the trigonometric function, so that the CORDIC algorithm is converted into a CORDIC processor which is capable of fast processing. In this paper, we conducted a comparative detailed study of the previous existing CORDIC algorithm and the CORDIC processing unit. In this we also did a comparative analysis of the system level and a comparative assessment based entirely on algorithm and structure level, primarily based on the parameters.

Deep neural network (DNN) is an important technology in the field of artificial intelligence. The softmax layer is one of the key component layers for completing multi-classifcation tasks. The softmax layer contains a large number of exponents and division operations, which causes it to consume a lot of hardware resources in FPGA implementation. This paper presents an efficient FPGA implementation of the softmax layer. For the exponential operation of the softmax layer, the mathematical transformation better than the Coordinate Rotation Digital Computer (CORDIC) algorithm is used to convert to subtraction and 2 exponential operation. The division is converted into a subtraction and shift operation, and added the highest non-zero bit detection processing before the operation to greatly reduce the cycle of the division operation. Experimenting with our softmax architecture on Xilinx ZCU102, the results show that the FPGA implementation of softmax layer can attain the precision of magnitude 10-6 and greatly accelerate the calculation of the softmax layer.

In the artificial neural networks, tanh (hyperbolic tangent) and sigmoid functions are widely used as activation functions. Past methods to compute them may have shortcomings such as low precision or inflexible architecture that is difficult to expand, so we propose a CORDIC-based architecture to implement sigmoid and tanh functions, which has adjustable precision and flexible scalability. It just needs shift-add-or-subtract operations to compute high-accuracy results and is easy to expand the input range through scaling the negative iterations of CORDIC without changing the original architecture. We adopt the control variable method to explore the accuracy distribution through software simulation. A specific case (ARCH. (1, 15, 18), RMSE: 10−6) is designed and synthesized under the TSMC 40nm CMOS technology, the report shows that it has the area of 36512.78μm2 and power of 12.35mW at the frequency of 1GHz. The maximum work frequency can reach 1.5GHz, which is better than the state-of-the-art methods.

The development of radar technology has always been a hot issue. In recent years, due to the popularization of Advanced Driver Assistance Systems (ADAS), such as autonomous driving system and collision avoidance system, the requirements for radar technology are increasing rapidly. Through the radar system and the digital signal processing, we can get the object's information, such as range, velocity and angle. This paper will focus on the DOA (Direction of Arrival) which is called angle detection in general. The MUSIC (MUltiple SIgnal Classification) algorithm is a kind of super resolution algorithm for angle searching. In MUSIC algorithm, EVD (Eigenvalue Decomposition) has the most computation load. Therefore, we use cyclic Jacobi method to implement EVD processor, which can achieve hardware simplification. In order to reduce the latency, this paper propose using the neural network model to calculate the values of arctangent, sine and cosine function instead of using the traditional CORDIC (Coordinate Rotation Digital Computer) method. The proposed NN-based Cyclic Jacobi EVD processor was operated at 250 MHz in TSMC 90 nm CMOS technology. The total latency of the system is 1.25 us, and the total gate counts are 104.401k.

This paper presents an FPGA implementation of Field Oriented Control (FOC) method with high switching frequency for 3-phase machine drives. A common architecture has been constructed for both BrushLess DC motors (BLDC) and Permanent Magnet Synchronous Motors (PMSM). For this purpose, the controller module has been implemented by using a hardware efficient algorithm, namely, Coordinate Rotation Digital Computer (CORDIC). The result of this implementation has been compared with the literature, and we claim that this paper’s FPGA design has better performance in terms of area and speed with respect to other FPGA-based FOC designs.

Square Root Unscented Kalman Filter (SRUKF) provides a practical solution for highly nonlinear and critical applications such as Simultaneous Localization and Mapping (SLAM). It improves the stability of the system, at the same time enhancing the numerical accuracy for hardware platform. It is less computationally demanding than the Unscented Kalman Filter (UKF), however, the hardware development process remains a complex task with high resource utilization. This paper presents a Householder CORDIC based low complexity architecture design for SRUKF targeting the highly nonlinear SLAM application. A hardware-software co-design methodology is proposed and implemented on Zynq-7000 XC7Z020 FPGA. Synthesis results show that the architecture saves 91% of DSP cores and is 20% faster than the state-of-the-art UKF architecture. The proposed SRUKF is also highly stable and achieve 78% and 10% greater accuracy than EKF SLAM and UKF SLAM respectively.

An efficient ASIC-based hardware design of activation function (AF) in neural networks faces the challenge of offering functional configurability and limited chip area. Therefore an area-efficient configurable architecture for an AF is imperative to fully harness the parallel processing capacity of an ASIC in contrast to a general-purpose processor. To address this, we propose a configurable AF based on the shift-and-add algorithm, collectively known as Co-ordinate Rotation Digital Computer(CORDIC) algorithm. The proposed versatile configurable activation function is designed using CORDIC architecture and implements both tan hyperbolic and sigmoid function. The derived model is synthesized and verified at 45nm technology. Further, in order to address leakage issues at lower technology nodes, we exploit the power-gating technique for the proposed AF based on CORDIC architecture. Our circuit design is extracted in cadence virtuoso and simulated for all physical parameters. With respect to the state-of-the-art, our design architecture shows improvement by 29% in area, 42% in power dissipation and 20% in latency. The used power gating technique saves 30% static power with minimal area overhead. The Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that mean and σ deviation are 180.73µW and 51.7µW respectively which is 60% of the state-of-the-art.

The hardware realization of fast fourier transform (FFT) consists of complex arithmetic operations such as multiply and accumulate. The key idea of this paper is to implement the 8-point Radix-2 DIT (Decimation In Time) FFT. In the FFT algroithm the twiddle factor generation by traditional method of generating sine and cos is replaced by the CORDIC algorithm for trigonometric functions. For the multiply and accumulate unit, different multipliers were used namely CORDIC multiplier, Single precision floating point multiplier. The adder blocks used in the implementation are linear adders such as Ripple Carry Adder (RCA) and parallel prefix adders such as Kogge-Stone Adder (KSA). Different combinations of multipliers and adders are used in the implementation of FFT, using VHDL in VIVADO 2016.2 version and programmed it in Xilinx ZYNQ FPGA board. The FFT implementation using single precision floating point multiplier incorporated with CORDIC multiplier and koggestone adder gives better delay performance compared to other combinations. In terms of area the combination of CORDIC multiplier with Ripple carry adder performs best.