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Exploring the CORDIC Algorithm and Clock-Gating for Power-Efficient Fast Fourier Transform Hardware Architectures
- Source :
- Journal of Integrated Circuits and Systems. 16:1-11
- Publication Year :
- 2021
- Publisher :
- Journal of Integrated Circuits and Systems, 2021.
-
Abstract
- This work explores hardware-oriented optimizations for the CORDIC (COordinate Rotation Digital Computer) algorithm investigating the power-efficiency improvements employing N-point Fast Fourier Transform (FFT) hardware architectures. We introduced three hardware-oriented optimizations for the CORDIC: (a) improving the signal extension, (b) removing the angle accumulation and (c) eliminating the redundancies in the iterations, both unnecessary when processing the FFT processing. Fully sequential FFT architectures of 32, 64, 128, and 256 points were synthesized employing ST 65 nm standard cell libraries. The results show up to 38% of power savings on average when using our best CORDIC optimization proposal to the FFT architecture comparing to the explicit multiply-based butterfly version. Moreover, when combining our best CORDIC optimization with the clock-gating technique, the power savings rises to 78.5% on average for N-point FFT.
Details
- ISSN :
- 18720234 and 18071953
- Volume :
- 16
- Database :
- OpenAIRE
- Journal :
- Journal of Integrated Circuits and Systems
- Accession number :
- edsair.doi...........d5444d03a16e7aabfd61e941d04aa691
- Full Text :
- https://doi.org/10.29292/jics.v16i2.226