Search

To proceed the miniaturization of electronic devices new materials and new device designs are needed. A promising candidate for future gate dielectrics are ternary rare earth oxides which exhibit permittivities up to 40. Such amorphous oxides (e.g. GdScO3 and LaLuO3) were introduced in silicon based MOSFETs and showed good performance according electron and hole mobility or steep subthreshold slopes down to 65 mV/dec [1-3]. They are also used in SiGe or Ge based devices with the same good performance [4]. The ternary rare earth oxides GdScO3 (GSO) and LaLuO3 (LLO) are deposited epitaxial and amorphous by PLD on α-GaN deposited by MOVPE on sapphire (Al2O3) substrates c.f. Hardtdegen et al. [5] and Y2O3 deposited on Si(111) by molecular beam epitaxy analogous to the approach of Tarnawska et al. [6] at different temperatures. Depending on the growth temperatures and the substratethe amorphous, orthorhombic, hexagonal or cubic phase is formed. On GaN GSO grows hexagonal proofed by a Θ-2Θ scan exhibiting beside the peaks of GaN and sapphire two peaks corresponding to the reflections of (0002) and (0004) hexagonal GSO (Figure 1). Furthermore the hexagonal structure was confirmed by TEM and the lattice constants determined from the diffraction pattern are a=0.36 nm and c=0.58 nm. The layers were electrical characterized by CV measurements using Al pads as top electrode. CET plots were made with different layer thicknesses and the permittivity (k) was extracted from inverses of the slope of the fitted lines. The k of hexagonal GSO on GaN is 27. Furthermore GSO was grown on Y2O3. Depending on the thickness of Y2O3 GSO grows hexagonal on 1 nm layers and cubic on 7 nm layers. Hexagonal GSO and cubic GSO deposited on Y2O3 on Si exhibit a k of 24 and 14, respectively. LLO was grown on GaN and exhibits a hexagonal structure at a growth temperature of 600°C and cubic structure at 900 °C The transition temperature seems to be 860 °C at which the cubic and the hexagonal crystal structure both are present. The rocking curve displays a FWHM of 0.15° for the hexagonal and the cubic structure. The lattice constants measured by XRD of the hexagonal and the cubic crystal structure are a=0.375 nm, c=0.612 nm and a=1.086 nm, respectively. Also on the Y2O3 LLO grows epitaxial. At low temperatures the hexagonal structure and high temperatures the cubic structure forms, too. The lattice constants determined by XRD and TEM are a=0.375 nm and c=0.612 nm for the hexagonal structure and a=1.086 nm for the cubic structure. LLO exhibits a k of 26 and 23 for hexagonal LLO and cubic LLO on Y2O3on Si, respectively. Finally we will present our recent results about GSO and LLO deposited by PLD especially the crystal structure and the electrical properties. Therefore we will show the dependence of the material properties to the growth conditions. References 1. E. Durgun Özben, J.M.J.L., A. Nichau, M. Schnee, S. Lenk, A. Besmehn, K. K. Bourdelle, and J.S. Q. T. Zhao, and S. Mantl, Integration of LaLuO3( k∼30) as High- k Dielectric on Strained and Unstrained SOI MOSFETs With a Replacement Gate Process. IEEE ELECTRON DEVICE LETTERS,, 2011. 32: p. 15-17. 2. Lopes, J.M.J., et al., Amorphous ternary rare-earth gate oxides for future integration in MOSFETs. Microelectronic Engineering, 2009. 86(7-9): p. 1646-1649. 3. Roeckerath, M., et al., Gadolinium scandate as an alternative gate dielectric in field effect transistors on conventional and strained silicon. Applied Physics A, 2009. 94(3): p. 521-524. 4. Minamisawa, R.A., et al., High mobility strained Si0.5Ge0.5/SSOI short channel field effect transistors with TiN/GdScO3 gate stack. Microelectronic Engineering, 2011. 88(9): p. 2955-2958. 5. Hardtdegen, H., et al., Uniform III-nitride growth in single wafer horizontal MOVPE reactors. physica status solidi (a), 2005. 202(5): p. 744-748. 6. Tarnawska, L., et al., Single crystalline Sc2O3/Y2O3 heterostructures as novel engineered buffer approach for GaN integration on Si (111). Journal of Applied Physics, 2010. 108(6): p. 063502. Figure 1

Al diffusion into gate stack leads to EOT reduction.Process reduces the EOT at low temperature (400?C) and is suitable for replacement gate processes.Extensive interface studies support the electrical measurements.Reactions are in agreement with thermodynamical considerations. The continued device scaling demands the reduction of the equivalent oxide thickness (EOT) below 1nm. For HfO2-based gate stacks, the interfacial SiO2 limits the EOT scaling. A low EOT can only be achieved if the interfacial layer (IL) is reduced to its physical limit of ~4i?. Such thin EOT are achievable if redox reactions within the gate stack are employed in order to reduce SiO2. This study reports on the use of an Al layer in combination with a TiN metal electrode to reduce the IL and achieve lowest EOT values. The lowest EOT achieved was 4.6i?. However, the scavenging process was found to strongly depend on the thermal budget after Al deposition. The presented process adapts a standard metal-inserted poly-Si flow (MIPS) prior to Al deposition, but may also be an option to control IL regrowth.

In this work, we address the following question: Where do the resistive switching processes take place in memristive thin-film devices of the single crystalline model material Fe-doped SrTiO3? We compare resistive switching induced by the tip of the atomic force microscope on the bare thin-film surface with the switching properties observed in memristive devices with Pt top electrode. In order to close the gap between these two approaches, we combine conductive-tip atomic force microscopy with a delamination technique to remove the top electrode of Fe-doped SrTiO3 metal-insulator-metal (MIM) structures to gain insight into the active switching interface with nanoscale lateral resolution. This enables us to prove the coexistence of a filamentary and area-dependent switching process with opposite switching polarities in the same sample. The spatially resolved analysis by transmission electron microscopy and photoelectron spectromicroscopy gives us some hints that the two switching types take place in device regions with different defect density and significant stoichiometry difference.

This work presents as-grown textured ZnO:Al films by rf magnetron sputtering initiated by pre-treatment of glass substrate with mixed argon and oxygen ions. A 650 nm thick of this film exhibits surface texture features with lateral size around 500 nm; the resistivity is below 5 × 10 −4 Ω · cm and the transparency in the near-infrared spectral range is high (> 80% at 1000 nm). Microcrystalline silicon thin film solar cells grown on the textured glass exhibit excellent light trapping effect with a short circuit current density of 18.2 mA/cm².

This paper investigates laser scribing of a-Si:H layers from the film side with a ns pulsed UV laser for thin-film solar modules. We compared the contact resistance for several scribing methods and find that a low contact resistance is only achieved for double scribing methods (i.e. scribing the same line twice). Furthermore, we find that for such double scribing methods the alignment between the laser spots of the first and second sub-scribes is critical for good-quality contacts. In order to analyze these results in more detail, we examined the morphology and chemical composition at the surface of the laser lines using scanning electron microscopy, X-ray photoelectron spectroscopy and secondary ion mass spectrometry. From this analysis, we conclude that a good alignment between the first and second scribes results in less re-deposition of silicon in the form of SiO2 on the surface, which explains differences in contact resistance found for the various scribing methods. As a good alignment between the two sub-scribes is difficult to obtain, these double scribing methods are not attractive for industrial application. We developed a new scribing method for which alignment between the two scribes is not critical, and demonstrate that we can obtain high-quality contacts with this method.

The miniaturization of metal-oxide-semiconductor field effect transistors (MOSFETs) is approaching fundamental limits. Novel materials and innovative device structures are needed in order to continue the evolution of complementary metal-oxide-semiconductor (CMOS) technology. High-k dielectrics combined with semiconductors with superior transport properties than Si is an attractive alternative for future CMOS applications. For instance, the use of germanium as a high-mobility channel material is very promising due to intrinsic higher carrier mobilities than Si [1]. However, one of the issues that still remains is the challenge to achieve a high quality interface between Ge and a high-k gate dielectric. Although different methods have been employed for surface passivation prior to the high-k deposition (e.g. thermally grown GeO2 [2]), their use may impede further equivalent oxide thickness (EOT) scaling to values 1nm. Therefore, the search for alternative high-k oxides that could offer stable interfaces with a low density of electrically active defects has become a topic of major interest. Ternary rare earth oxides such as the scandates (LaScO3 or GdScO3) and LaLuO3, were proven to be promising high-k dielectric candidates on silicon. Thin films of these materials keep their amorphous structure up to 1000°C, as measured by X-ray diffraction (not shown). In addition, as summarized in table 1, they offer large optical band gaps (>5 eV) and band offsets to silicon (2-2.5 eV), and have dielectric constants (k) between 23 up to 32 [3]. The integration of these oxides with high mobility substrates such as Ge, SiGe, and strained Si (sSi) also shows great potential [4,5]. Figure 1 illustrates capacitance-voltage (C-V) measurements for a ~4.5 nm thick amorphous LaLuO3 film deposited directly on n-type Ge(100) substrates without any surface passivation layer. C-V curves free of humps and irregularities could be obtained. When comparing curves measured at different frequencies, one can see a dispersion of less than 5% on the accumulation side and a small flatband voltage shift of about 0.2 V between 10 kHz and 1 MHz. Most importantly, an EOT below 1 nm could be achieved with leakage current densities kept below 10 A/cm and Dit levels in the range of 1 to 5x10 eVcm. These and other similar results obtained for scandate films on Ge (not shown) will be discussed taking into account the physico-chemical scenario at the oxide/Ge interface as studied by X-ray photoelectron spectroscopy, transmission electron microscopy and time-of-flight secondary ion mass spectrometry. It will be shown that the formation of a germanate-like interface between the oxide and Ge results in an improvement of the electrical properties.

Terbium scandate (TbScO3) and lanthanum scandate (LaScO3) have been investigated as gate dielectrics for metal-oxide-semiconductor field-effect transistors on both silicon-on-insulator (SOI) and strained SOI (sSOI) substrates. X-ray photoelectron spectroscopy analysis revealed the presence of a silicate at the interface for TbScO3 on Si, whereas a silicate/SiO2-like interface was found for the LaScO3 on Si. A full replacement gate process was developed to fabricate high-kappa/metal gate fully depleted transistors on SOI and sSOI. LaScO3 transistors with a gate length of 2 mu m show excellent characteristics with steep subthreshold slopes of 72 mV/dec, high Ion/Ioff ratios, and electron mobility of 180 cm(2)/V . s for SOI and 375 cm(2)/V . s for sSOI at low field, which is superior to corresponding TbScO3 devices. All sSOI transistors showed 2 times higher electron mobility than SOI reference devices.

We investigated the electrical and structural properties of TbScO3 as an alternative gate dielectric. Rutherford backscattering spectrometry revealed a stoichiometric film while X-ray photo-electron spectroscopy indicated silicate formation at the interface. Capacitance-Voltage measurements resulted in well behaving C-V curves with no hysteresis and a low density of interface trap states in the range of 4x1011 (eVcm2)-1. Fully depleted (FD) SOI and sSOI MOSFETs fabricated with a full replacement gate process show a steep subthreshold slope down to 81 mV/dec and high Ion/Ioff ratios up to 108. Low field electron mobilities of 181 cm2/Vsec for SOI and 350 cm2/Vsec for sSOI, were extracted, which are comparable to MOSFETs with Hf based oxides. Gate induced drain leakage (GIDL) investigations indicate a trap assisted band to band tunneling.

(Si)GeSn is an emerging group IV alloy system offering new exciting properties, with great potential for low power electronics due to the fundamental direct band gap and prospects as high mobility material. In this Article, we present a systematic study of HfO2/TaN high-k/metal gate stacks on (Si)GeSn ternary alloys and low temperature processes for large scale integration of Sn based alloys. Our investigations indicate that SiGeSn ternaries show enhanced thermal stability compared to GeSn binaries, allowing the use of the existing Si technology. Despite the multielemental interface and large Sn content of up to 14 atom %, the HfO2/(Si)GeSn capacitors show small frequency dispersion and stretch-out. The formed TaN/HfO2/(Si)GeSn capacitors present a low leakage current of 2 × 10(-8) A/cm(2) at -1 V and a high breakdown field of ∼8 MV/cm. For large Sn content SiGeSn/GeSn direct band gap heterostructures, process temperatures below 350 °C are required for integration. We developed an atomic vapor deposition process for TaN metal gate on HfO2 high-k dielectric and validated it by resistivity as well as temperature and frequency dependent capacitance-voltage measurements of capacitors on SiGeSn and GeSn. The densities of interface traps are deduced to be in the low 10(12) cm(-2) eV(-1) range and do not depend on the Sn-concentration. The new processes developed here are compatible with (Si)GeSn integration in large scale applications.

Cu/Ge0.3Se0.7/Pt cells were prepared and bipolar resistive switching in Ge0.3Se0.7 films by means of copper ion migration was examined. The cell was switched from the high to the low resistance state at about -50mV, and it was switched back to the high resistance state at about 100mV. The resistance ratio between the high and the low state was up to 200. Up to approximately 104 switching cycles were achieved. Pulse measurements showed that the two resistance states were tuneable by varying the applied voltage and the pulse length. Therefore, it is possible to store more than one bit per cell. The current density is independent of the electrode diameter, indicating that the cell can be scaled down to the range of nanometers. Due to the low switching voltages, non-destructive read out operation, high storage density, and scalability, such cells are promising for future memory applications.

The integration of lanthanum lutetium oxide (LaLuO3) with a n value of 30 is, for the first time, demonstrated on strained and unstrained SOI n/p-MOSFETs as a gate dielectric with a full replacement gate process. The LaLuO3/Si interface showed a very thin silicate/SiO2 interlayer with a Dit level of 4.5 × 1011 (eV · cm2)-1. Fully depleted n/p-MOSFETs with LaLuO3/TiN gate stacks indicated very good performance with steep subthreshold slopes of ~70 mV/dec and high Ion/Ioff ratios. In addition, strained SOI shows enhanced electron mobilities with a factor of 1.7 compared to SOI. Both electron and hole mobilities for LaLuO3 on SOI are similar to the mobilities in reported Hf-based high-κ devices.

Rare earth oxides are promising candidates for future integration into nano-electronics. A key property of these oxides is their ability to form silicates in order to replace the interfacial layer in Si-based complementary metal-oxide field effect transistors. In this work a detailed study of lanthanum lutetium oxide based gate stacks is presented. Special attention is given to the silicate formation at temperatures typical for CMOS processing. The experimental analysis is based on hard x-ray photoemission spectroscopy complemented by standard laboratory experiments as Rutherford backscattering spectrometry and high-resolution transmission electron microscopy. Homogenously distributed La silicate and Lu silicate at the Si interface are proven to form already during gate oxide deposition. During the thermal treatment Si atoms diffuse through the oxide layer towards the TiN metal gate. This mechanism is identified to be promoted via Lu¿O bonds, whereby the diffusion of La was found to be less important., This work was partially supported by the project KZWEI which is funded in line with the technology funding for regional development (ERDF) of the European Union and by funds of the Free State of Saxony.

The chemical reactions at the higher-k LaLuO 3 /Ti 1 N X /poly-Si gate stack interfaces are studied after high temperature treatment. A Ti-rich TiN metal layer degrades the gate stack performance after high temperature annealing. The gate stack containing TiN/LaLuO 3 with a near stoichiometric TiN layer is stable during 1000 °C, 5s anneals. Both electrical and structural characterization methods are employed to explore the thermal stability of the gate stack. Based on these results an integration of TiN/LaLuO 3 in a gatefirst MOSFET process on SOI is shown.

In this contribution, results on the structural and electrical properties of high-κ REScO 3 (RE = La, Gd, Tb, Sm) and LaLuO 3 amorphous thin films are presented. The study reveals that these oxides are potential candidates for future integration in MOSFETs. High dielectric constants up to 30 were measured for amorphous thin films of these materials, as well as low leakage current and low interface trap densities. Very promising results for transistors processed on SOI and sSOI substrates are also shown.

This paper explores a few of the factors relevant to BMP practices and selection as affected by arid climate conditions, and provides a case study where evaporation rather than discharge was the principle detention facility outlet mechanism. It is intended to contribute to discussions on arid regions hydrology that are currently under way, particularly within ASCE’s EWRI Urban Water Resources Research Council, and to stimulate dialogue regarding stormwater management practice in such areas. While BMP solutions seem by definition to have wide extensibility, it is not clear to the authors that BMP solutions are universally effective. Social context and prevailing infrastructure can make accepted practice in BMP technologies in one area inappropriate in another. The case study demonstrates control of discharge totally by evaporation in an arid region where this was preferred, but it is recognized that alternative measures might be preferred in regions where groundwater storage is an option or where evaporative losses are to be avoided. There is already some substance in the literature that reflects this kind of appropriate discrimination of preferred solutions, but there remains a significant need to extend and further develop this understanding.

The resistive switching behavior of devices consisting of aluminum top electrode, molecular layer (rose bengal), and bottom electrode (zinc oxide and indium tin oxide) is examined. By measuring the current versus voltage dependence of these devices for various frequencies and by systematically varying the composition of the device, we show that the switching is an extrinsic effect that is not primarily dependent on the molecular layer. It is shown that the molecular layer is short circuited by filaments of either zinc oxide or aluminum and that the switching effect is due to a thin layer of aluminum oxide at the zinc oxide/aluminum interface. (c) 2006 American Institute of Physics.

Among the different polymorphs of LaLuO3 the hexagonal one is the least explored. Therefore, in this work, hexagonal LaLuO3 is grown and investigated in more detail. Two different growth templates are presented, offering the possibility to stabilize this hexagonal phase: Y2O3 on Si (111) and GaN on Al2O3 (0001). The LaLuO3 layers show smooth surfaces and high crystallinity for both types of templates. Spectroscopic characterization reveals a wide bandgap Eg of 5.6 eV and capacitance voltage measurements display a relative permittivity κ of 26, which makes hexagonal LaLuO3 a promising candidate as a future gate dielectric for devices based on hexagonal semiconductors such as GaN.

GdScO3 was deposited by pulsed laser deposition on two different templates suitable for III-N growth: metalorganic vapour phase epitaxial GaN (0 0 0 1) on sapphire and molecular beam epitaxial Y2O3 on Si (1 1 1). The structure and crystallinity of the layers were determined as well as the band gap and permittivity of the material. It was found that GdScO3 grows epitaxially and crystallizes hexagonally in contrast to the usually found orthorhombic or amorphous phases. A band gap and permittivity κ of 5.2 eV and 24 were found, respectively, making GdScO3 a promising epitaxial gate dielectric for III-N transistor applications.

In this study, the authors present results on the structural, chemical, and electrical characterization of HfO2 thin layers on 300 mm Si wafers. The layers were prepared by atomic layer deposition using a liquid delivery system technology for metal organic precursors, which allows an accurate control of the Hf precursor. After optimization of the deposition process with an alkylamide precursor for Hf and ozone chemistry, the growth of the SiOx interfacial layer between the HfO2 layer and the Si substrate could be minimized using TiN as metal gate. In addition, the authors studied the effect of Al2O3 interfacial layers on the properties of metal-oxide-semiconductor capacitor resulting in a positive flat band voltage shift of up to ∼300 mV according to the layer thickness. Gate stacks with equivalent oxide thicknesses around 1.1 nm showed leakage current densities as low as 1.1×10−2 A/cm2 at VFB of 1 V. In addition, the capacitance-voltage curves for thin HfO2 layers indicated a negligible hysteresis, below...

We demonstrate the integration of TbScO3, LaScO3, and LaLuO3 as alternative gate oxides for fully depleted silicon on insulator (SOI) and strained SOI metal-oxide-semiconductor field-effect transistors (MOSFETs) with equivalent oxide thicknesses of 2.8, 2.4, and 1.55 nm, respectively. Silicate formation at the high-kappa/Si interface was studied by x-ray photoelectron spectroscopy. Electrical investigations revealed good transistor performance with these novel gate oxides with permittivities in the range of 26-32 and TiN as a metal gate. Steep inverse subthreshold slopes of 72 mV/dec, high I-on/I-off ratios over 10(8), and a low density of interface states of approximate to 5 X 1011 (eV cm(2))(-1) were achieved. MOSFETs on SOI substrates show good low field electron mobilities of 180, 183, and 188 cm(2)/V s for all investigated oxides. For devices on strained SOI the electron mobility was improved by a factor of 2. The measured mobilities are close to those of devices with HfO2 as gate dielectric, while offering better electrostatic control due to their higher permittivities. (c) 2011 American Vacuum Society. [DOI: 10.1116/1.3533760]