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A spectrum of emerging applications including edge artificial intelligence advocate the precompute-and-search scheme with embedded small-size content addressable memory (CAM) for its hardware efficiency instead of repetitive arithmetic operations. However, integration of the CAM macros that are conventionally implemented with full custom analog circuits renders design-space exploration and optimization to be difficult at system level. As an alternative, a complete design flow for compiling ternary CAM on chip using foundry-supplied digital standard cells is introduced in this paper. Based on novel CAM architecture and logic design, we leverage guided placement and routing with mainstream EDA tools for exploiting the inherent structure regularity of CAM-cell arrays in layout. An analytical model is also presented which allows us for a systematic investigation on the energy reduction by adapting our design to various pre-search structures. Validated on a post-layout 32W64 ternary CAM in 28nm, our parallel-matching scheme performs at 2.6GHz with 0.42fJ/bit/search, and the (8-bit) pre-search scheme achieves 0.19fJ/bit/search at 1.1GHz, both under the 0.9V supply voltage. In addition to flexibility for tradeoffs between the search throughput and energy, our all-digital CAM design enables voltage scaling aggressively down to 0.45V with a minimum energy consumption of 0.06fJ/bit/search at 50MHz.

TCAM is widely used for rule tables in network switches. An efficient update scheme, which requires as few rule moves as possible, is often time-consuming to compute, while the fast computation likely yields a mediocre update scheme. We studied the existing algorithms and found none is satisfactory to the emerging applications. In this paper, we present a simple greedy algorithm, GreedyJump, which achieves fast computation and efficient update scheme at the same time, both with the best-in-class performance. The evaluation qualifies GreedyJump as the default TCAM update algorithm ready for meeting the scalability challenges in various application scenarios.

In the missing item task, two short lists are presented. The test list contains all but one of the items from the study list in a new random order and the task is to report which item from the study list is missing. Murdock and Smith (2005) found that the time to correctly respond with the missing item was independent of the position of the missing item and was also independent of the list length. They argued that these data are difficult to accommodate by models that include a search process but are consistent with models that posit "direct access" such as the power set version of Theory of Distributed Associative Memory (TODAM). If direct access is occurring, redintegration cannot be occurring. Two experiments test the direct access account by determining whether two effects commonly ascribed to redintegration occur in the missing item task. Experiment 1 found a semantic relatedness effect and Experiment 2 found a word frequency effect. The presence of these effects is consistent with a redintegration account. Implications for TODAM and for an explanation based on the Feature Model are discussed. (PsycInfo Database Record (c) 2022 APA, all rights reserved).

Artificial Neural Network (ANN) is a form of computation inspired by the arrangement and purpose of the brain. Pattern Recognition is one of the demanding areas under Artificial Neural Network and pattern association is one of the major tasks through which pattern recognition is realized. Nowadays researchers are taking interest in the combination of evolutionary algorithms and ANN. In the present work, an attempt is being made to analyze the performance of Hopfield Associative Memory with Monte Carlo adaptation rule and evolutionary searching (Genetic Algorithm) for pattern storage and recall. The training pattern set has been taken a set of five Greek alphabet letters as different objects. The aim is to store Patterns with MC adaptation rule and get the best weight matrices for efficient recalling of any given set patterns. The neural networks architectures have been taken up for storing the given set of inputs, for which conventional Hebbian and Monte Carlo adaptation rule is considered. During the mutation process, various mutation probabilities are supposed to be evaluated. The detailed simulated results thus obtained will be presented with the help of tables and graph.

Many advances have been made in developing bio-inspired intelligent systems for performing important tasks like pattern association, which cannot be performed effectively by the conventional computer architectures. This paper presents a novel nonvolatile associative memory based on spintronic synapses utilizing magnetic tunnel junction (MTJ) and carbon nanotube field-effect transistors (CNTFET)-based neurons. MTJs introduce fascinating features like reconfigurability, nonvolatility, and high endurance to the design, while CNTFETs compensate for the flaws of the conventional transistors in deep nanoscale nodes. The comprehensive simulations validate the functionality of the proposed synaptic cell, and neuron, even in the presence of major process variations. The application of the proposed synaptic cell and neuron in the hardware realization of multi-associative memories is also investigated. The simulation results indicate that the proposed hardware-based multi-associative memory performs similar to its ideal software-based counterpart with a less than 5% difference in the successful recall rate. The proposed multi-associative memory can be used as a neural network hardware accelerator alongside a conventional computing system with no need for any extra component, since its input and output are logical ‘0’ and ‘1’.

First, the cerebellar model articulation controller (CMAC), invented in the early 1970s by J S Albus, and the associative memory system (AMS), developed for learning control systems by H Tolle, E Ersu and J Militzer in the early 1980s, are briefly described. The underlying mathematics of the AMS learning or training algorithm is then given with a geometrical interpretation from which its convergence properties may be deduced. These are illustrated for some simple cases. The original algorithm devised by Albus is very simple to compute but is slow to converge, and the second part of the paper investigates various methods of speeding up the algorithm. From an application of these new algorithms to test cases one is strongly recommended for further evaluation. The results reported here are of relevance also to the topical and rapidly growing field of neural computing.

Learning from a few examples (one/few-shot learning) on the fly is a key challenge for on-device machine intelligence. We present the first chip-level demonstration of one-shot learning with Stanford Associative memory for Programmable, Integrated Edge iNtelligence via life-long learning and Search (SAPIENS), a resistive random access memory (RRAM)-based non-volatile associative memory (AM) chip that serves as the backend for memory-augmented neural networks (MANNs). The 64-kb fully integrated RRAM-CMOS AM chip performs long-term feature embedding and retrieval, demonstrated on a 32-way one-shot learning task on the Omniglot dataset. Using only one example per class for 32 unseen classes during on-chip learning, SAPIENS achieves 79% measured inference accuracy on Omniglot, comparable to edge software model accuracy using five-level quantization (82%). It achieves an energy efficiency of 118 GOPS/W at 200 MHz for in-memory L1 distance computation and prediction. Multi-bank measurements on the same chip show that increasing the capacity from three banks (24 kb) to eight banks (64 kb) improves the chip accuracy from 73.5% to 79%, while minimizing the accuracy excursion due to bank-to-bank variability.

In this work, we present a four-transistor-two-resistor (4T2R) ternary content addressable memory (TCAM) bit cell based on the resistive memory (RRAM), comprising the conventional two-transistor-two-resistor (2T2R) cell with two additional comparison transistors. It can effectively amplify the match-line signal ratio (ML-ratio), lower the leakage current of the match cell ( ${I}_{{\mathrm {MATCH}}}$ ), and suppress the read disturbance. The proposed concept is silicon verified using the 180 nm CMOS technology with transition-metal-oxide (TMO) RRAM integrated at the back-end-of-line (BEOL). It achieves a considerable ML-ratio of 1860 and a low ${I}_{{\mathrm {MATCH}}}$ of 11.15 nA on average. In a typical search operation, it shows a negligible ML drop at the match case and a large ML swing range at the mismatch case. The SPICE simulation results further show it can support a long word-length (WDL) of 256 under a clock rate of 100 MHz for search operations, which demonstrates its promise for highly parallel nonvolatile TCAM.

An associative memory is an artificial neural network model designed to store and recall input-output patterns pairs by association. A new method for obtaining two associative memories +M and -M is presented in this article, which uses a framework focused on two new binary operations boxplus and boxminus, and a unary operation called projection. The conditions to obtaining perfect recovery and the noise boundaries that the memories can tolerate are studied. Memories +M and -M are robust to additive and subtractive noise, respectively, both types converge in one-step and operate in heteroassociative and autoassociative modes. The performance of the proposed memories is tested against other memory models under identical conditions using the gamma binary distance for measuring similarity between binary patterns. The computer simulation results based on the average of 500 trials with the binary set of 26 lowercase letters of 7x7 pixel size, showed that the proposed memories in autoassociative mode exhibited a gamma binary distance of above .8, .75 and .7 by distorting up to 10 pixels by additive, subtractive, and mixed noise, respectively, which implied that the recovered images had a high similarity. In absence of noise the performance was excellent, i.e., the 100% of the recovered images were identical.

A tristate-nanoelectromechanical-switch-based ternary content-addressable memory (NEMTCAM) is proposed for the first time. In the proposed unit NEMTCAM cell, a single nanoelectromechanical (NEM) memory switch replaces two static random access memory cells. Due to the monolithic 3-D (M3D) integration and nonvolatile property of NEM memory switches, the proposed NEMTCAM achieves an 86.3% smaller area, 75.0% lower dynamic power consumption, and a 76.6% higher search speed than conventional ternary content-addressable memory (TCAM) in addition to a negligible static leakage current.

In the present study, quantitative relations between Cognitive Emotion Regulation strategies (CERs) and EEG synchronization levels have been investigated for the first time. For this purpose, spectral coherence (COH), phase locking value and mutual information have been applied to short segments of 62-channel resting state eyes-opened EEG data collected from healthy adults who use contrasting emotion regulation strategies (frequently and rarely use of rumination&distraction, frequently and rarely use of suppression&reappraisal). In tests, the individuals are grouped depending on their self-responses to both emotion regulation questionnaire (ERQ) and cognitive ERQ. Experimental data are downloaded from publicly available data-base, LEMON. Regarding EEG electrode pairs that placed on right and left cortical regions, inter-hemispheric dependency measures are computed for non-overlapped short segments of 2 sec at 2 min duration trials. In addition to full-band EEG analysis, dependency metrics are also obtained for both alpha and beta sub-bands. The contrasting groups are discriminated from each other with respect to the corresponding features using cross-validated adaboost classifiers. High classification accuracies (CA) of 99.44% and 98.33% have been obtained through instant classification driven by full-band COH estimations. Considering regional features that provide the high CA, CERs are found to be highly relevant with associative memory functions and cognition. The new findings may indicate the close relation between neuroplasticity and cognitive skills.

Brain-inspired Hyperdimensional computing (HDC) has shown its effectiveness in low-power/energy designs for edge computing in the Internet of Things (IoT). Due to limited resources available on edge devices, multi-task learning (MTL), which accommodates multiple cognitive tasks in one model, is considered a more efficient deployment of HDC. However, as the number of tasks increases, MTL-based HDC (MTL-HDC) suffers from the huge overhead of associative memory (AM) and performance degradation. This hinders MTL-HDC from the practical realization on edge devices. This article aims to establish an MTL framework for HDC to achieve a flexible and efficient trade-off between memory overhead and performance degradation. For the shared-AM approach, we propose Dimension Ranking for Effective AM Sharing (DREAMS) to effectively merge multiple AMs while preserving as much information of each task as possible. For the independent-AM approach, we propose Dimension Ranking for Independent MEmory Retrieval (DRIMER) to extract and concatenate informative components of AMs while mitigating interferences among tasks. By leveraging both mechanisms, we propose a hybrid framework of Mul ti- Ta sking HDC, called MulTa-HDC. To adapt an MTL-HDC system to an edge device given a memory resource budget, MulTa-HDC utilizes three parameters to flexibly adjust the proportion of the shared AM and independent AMs. The proposed MulTa-HDC is widely evaluated across three common benchmarks under two standard task protocols. The simulation results of ISOLET, UCIHAR, and MNIST datasets demonstrate that the proposed MulTa-HDC outperforms other state-of-the-art compressed HD models, including SparseHD and CompHD, by up to 8.23% in terms of classification accuracy.

Associative memory is a widespread self-learning method in biological livings, which enables the nervous system to remember the relationship between two concurrent events. The significance of rebuilding associative memory at a behavior level is not only to reveal a way of designing a brain-like self-learning neuromorphic system but also to explore a method of comprehending the learning mechanism of a nervous system. In this paper, an associative memory learning at a behavior level is realized that successfully associates concurrent visual and auditory information together (pronunciation and image of digits). The task is achieved by associating the large-scale artificial neural networks (ANNs) together instead of relating multiple analog signals. In this way, the information carried and preprocessed by these ANNs can be associated. A neuron has been designed, named signal intensity encoding neurons (SIENs), to encode the output data of the ANNs into the magnitude and frequency of the analog spiking signals. Then, the spiking signals are correlated together with an associative neural network, implemented with a three-dimensional (3-D) memristor array. Furthermore, the selector devices in the traditional memristor cells limiting the design area have been avoided by our novel memristor weight updating scheme. With the novel SIENs, the 3-D memristive synapse, and the proposed memristor weight updating scheme, the simulation results demonstrate that our proposed associative memory learning method and the corresponding circuit implementations successfully associate the pronunciation and image of digits together, which mimics a human-like associative memory learning behavior.

In traditional neural network integration, people adopt Boosting, Bagging and other methods to integrate traditional neural networks. The integration is complex, time-consuming and laborious, difficult to popularize and apply. This paper is not a continuation of this method, but another integration which is called by us morphological neural network integration (MNNI) or morphological associative memory integration (MAMI). These networks used in MAMI are a network family, with 10 family members, unified in the morphological associative memory framework. Various morphological associative memory networks can be directly used as individual networks to learn and work separately, and then synthesize to draw conclusions. The results of some experiments show that this method is not only feasible in theory, but also effective in practice. It can avoid the complexity of traditional integration method, make the integration structure simple and clear, easy to operate, save time, and therefore is a method of neural network integration with research and application value. The contribution of this paper lies in that: (1) it proposed the concept and method of MNNI and, (2) verified the effectiveness of MNNI through experiments and, (3) it has the characteristics of simplicity, saving time and labor and cost, with a good application prospect and, (4) thus promoting the development of morphological neural networks in theory and practice.

Low-power IC design has become a priority in recent years because of the growing proliferation of portable battery-operated devices, bringing Static Random-Access Memory (SRAM) and Content Addressable Memory (CAM) into play. In today's SoCs, embedded SRAM units have become a necessary component. There is a lack of chips in the current world and to manufacture chips there is the requirement of Electronic Design Automation(EDA) tools that can perform better. In this paper, the main motive is to showcase the performance of open-source tools available currently which can still generate the required output with no cost. In this new era of fast mobile computing, traditional SRAM cell designs are power-demanding and underperforming. Rather than lowering manufacturing costs through high-volume production, specialty memory give cost-effective alternatives through architecture. Specialty memory devices enable the designer to address issues like board area, important timing, data flow bottlenecks, and so on in ways that high-volume regular memory devices cannot. Implementation of memory devices on Cadence environment and open-source environment to check the compatibility and compare the power, area, and delay of both 64-bit SRAM and CAM also analysing and validating the results of both the memory devices in this paper. For SRAM in a cadence environment, the calculated power, area, and slack have improved values, namely 0.145mW, 1104.3um2, and positive slack of 6636. Furthermore, the power for 64-bit CAM in a cadence context is nearly identical to those for an open-source environment ~0.8mW. In an open-source environment, the calculated slack for CAM is 4.74.

By virtue of hardware parallelism, ternary content addressable memory (TCAM) is attractive for low-latency search for packet forwarding in routers for network communications in the upcoming fifth-generation (5G) era. However, the demand for high-density TCAM encounters remarkable costs in silicon area and power consumption. In this work, a 16-kb nonvolatile ternary content addressable memory (nvTCAM) test chip based on resistive memory (ReRAM) is demonstrated in 28-nm process with two techniques to deal with the aforementioned issues. First, the crossbar array with 2-diode-2-ReRAM (2D2R) nvTCAM cell is proposed to realize $>3\times $ improvement in storage density. The back-end-of-line integration of both diode and ReRAM resistor also allows for further 3-D stacking to realize larger storage density. Second, the machine learning concept is exploited to realize intelligent search operation. ${K}$ -means clustering is employed to allocate the entry storage and then the search of destination IP address can be targeted to a specific bank for low power. The evaluation shows >70% reduction in search energy with 2% overhead in silicon area for bank count of four. The test chip also achieves a match delay of 2 ns under nominal operating conditions.

Fast and accurate load parameter identification has a large impact on power systems operation and stability analysis. This article proposes a novel Imitation and Transfer Q-learning (ITQ)-based method to identify parameters of composite constant impedance-current-power (ZIP) and induction motor (IM) load models. Firstly, an imitation learning process is introduced to improve the exploitation and exploration processes. Then, a transfer learning method is employed to overcome the challenge of time-consuming optimization when dealing with new identification tasks. An associative memory is designed to realize dimension reduction, knowledge learning and transfer between different identification tasks. Agents can exploit the optimal knowledge from source tasks to accelerate the search rate in new tasks and improve solution accuracy. A greedy action selection rule is adopted for agents to balance the global and local search. The performance of the proposed ITQ approach has been validated on a 68-bus test system. Simulation results in multi-test cases verify that the proposed method is robust and can estimate load parameters accurately. Comparisons with other methods show that the proposed method has superior convergence rate and stability.

The ternary content addressable memory (TCAM) is widely used in the routing table due to its high lookup performance. However, a large number of transistors would cause the power consumption of TCAM to be considerable. In this brief, a new state-preserved technique, named data retention based TCAM (DR-TCAM), is proposed to reduce the leakage power dissipated in the TCAM memory. According to the continuous feature of mask data, the DR-TCAM can dynamically adapt the power source of mask cells so as to reduce the TCAM leakage power. Particularly, the mask data wouldn’t be destroyed in the DR-TCAM. Based on TSMC 40nm technology, the simulation results show that the DR-TCAM performs better than the state-of-the-art works. Compared to the traditional TCAM design, the DR-TCAM can deliver a TCAM leakage power reduction of 41% for a collection of real routing tables. Besides, the total power reduction is about 12%.

OBJECTIVEMesial temporal lobe epilepsy (MTLE) surgery is associated with a risk of memory decline after surgery, but the effect of the extent and locus of temporal resection on postoperative memory function are controversial. The authors’ aim in this study was to confirm if selective resection is effective in preserving memory function and identify critical areas for specific memory decline after temporal resection.METHODSIn this single-center retrospective study, the authors investigated data from patients who underwent unilateral MTLE surgery between 2005 and 2015. Data from 74 MTLE patients (60.8% of whom were female; mean [SD] age at surgery 32 years [8.91 years] and duration of epilepsy 16 years [9.65 years]) with histologically proven hippocampal sclerosis were included. Forty-two patients underwent left-sided surgery. The resection area was manually delineated on each patient’s postoperative T1-weighted images. Mapping was performed to see if the resected group, compared with the nonresected group, had worse postoperative memory in various memory domains, including verbal item, verbal associative, and figural memory.RESULTSOverall, 95.9% had a favorable epilepsy outcome. In verbal item memory, resection of the left lateral temporal area was related to postoperative decline in immediate and delayed recall scores of word lists. In verbal associative memory, resection of the anterior part of the left hippocampus, left parahippocampal area, and left lateral temporal area was related to postoperative decline in immediate recall scores of word pairs. Resection of the posterior part of the left hippocampus, left parahippocampal area, and left lateral temporal area was related to delayed recall scores of the same task. Similarly, in the figural memory, postoperative decline of immediate recall scores was associated with the resection of the anterior part of the right hippocampus, amygdala, parahippocampal area, and superior temporal area, and decline of delayed recall scores was related to resection of the posterior part of the right hippocampus and parahippocampal area.CONCLUSIONSUsing voxel-based analysis, which accounts for the individual differences in the resection, the authors found a critical region for postoperative memory decline that is not revealed in the region-of-interest or groupwise comparison. Particularly, resection of the hippocampus was related to associative memory. In both verbal and visual memory, resection of the anterior part of the hippocampus was associated with immediate recall, and resection of the posterior part of the hippocampus was associated with delayed recall. Therefore, the authors’ results suggest that selective resection may be effective in preserving postoperative memory decline.

Non-volatile nanoscale memory devices (such as memristors) have promised to overcome the challenges of scalability and leakage currents of CMOS based memory devices. These novel memories can be fabricated in back-end-of-the-line of any CMOS process. Currently, a lot of research is focused on investigating the benefits of memristors for associative memories. These are Content-Addressable Memories (CAM) in which search based data access takes place. Searching for a particular bit in memristor is time consuming while search in CMOS CAM zone is efficient. To combine the speed and ease of search of CMOS memory and the scalability of memristor memory, we present a novel multibit hybrid CMOS-Memristor Associative Memory Cell. The benefits of such memory cells manifest in on-chip caches - the instruction and data cache, Branch Target Buffer, and Translation Lookaside Buffer. To exemplify the benefit of the cell further, we also simulate the MemCAM as the TLB of an ARM processor and obtained upto 50% decrease in miss rates of Data TLB and upto 93% in that of Instruction TLB. Average speedup of 1.16 was also achieved on various benchmark applications of PARCSEC and MiBench suites.

Most conventional memristor-based Pavlov associative memory neural network circuits have been working on realizing the learning and forgetting functions of simultaneous conditioning. However, the time interval between unconditional stimulus and conditional stimulus is a critical variable in classical conditioning. Different unconditional and conditional stimulus intervals evoke associative memory of brains with different rates. For example, learning in simultaneous conditioning is less effective than delay conditioning. Therefore, a memristor-based neural network circuit of delay and simultaneous conditioning is designed. The proposed circuit consists of learning states detection module, voltage control module, and synapse module. Many functions, such as short-delay conditioning learning, long-delay conditioning learning, simultaneous conditioning learning, experience learning, and two types of forgetting are implemented by the circuit. In particular, the so-called experience learning is that learning the forgotten knowledge will be faster than before and learning again will forget more slowly. This function is more bionic. The correctness of the design is demonstrated through simulations using PSPICE.

Artificial intelligence is a promising concept in modern and future societies. Presently, software programs are used but with a bulky computer size and large power consumption. Conversely, hardware systems named neuromorphic systems are suggested, with a compact computer size and low power consumption. An important factor is the number of processing elements that can be integrated. In the present study, three decisive technologies are proposed: (1) amorphous metal oxide semiconductor thin films, one of which, Ga–Sn–O (GTO) thin film, is used. GTO thin film does not contain rare metals and can be deposited by a simple process at room temperature. Here, oxygen-poor and oxygen-rich layers are stacked. GTO memristors are formed at cross points in a crossbar array; (2) analog memristor, in which, continuous and infinite information can be memorized in a single device. Here, the electrical conductance gradually changes when a voltage is applied to the GTO memristor. This is the effect of the drift and diffusion of the oxygen vacancies (Vo); and (3) autonomous local learning, i.e., extra control circuits are not required since a single device autonomously modifies its own electrical characteristic. Finally, a neuromorphic system is assembled using the abovementioned three technologies. The function of the letter recognition is confirmed, which can be regarded as an associative memory, a typical artificial intelligence application.

Bidirectional associative memories (BAMs) pass neural signals forward and backward through the same web of synapses. Earlier BAMs had no hidden neurons and did not use supervised learning. They tuned their synaptic weights with unsupervised Hebbian or competitive learning. Two-layer feedback BAMs always converge to fixed-point equilibria for threshold or threshold-like neurons. Every rectangular connection matrix is bidirectionally stable. These simpler BAMs extend to arbitrary hidden layers with supervised learning if the resulting bidirectional backpropagation algorithm uses the proper layer likelihood in the forward and backward directions. Bidirectional backpropagation lets users run deep classifiers and regressors in reverse as well as forward. Bidirectional training exploits pattern and synaptic information that forward-only running ignores.

Image processing devices plays a vital role in several applications like medical, security, biometric etc. The devices ranges from portable size to larger machines with and without Human Computer Interface possibilities. As the image processing and human computer interface system application requires higher memory requirements, the power and area should be small. Searching of data is a high priority work in image classification. To perform high speed search through hardware Content Addressable Memory is used. But the circuit suffers from higher power consumption, precharging issues and low performance. For longer word length the elimination of precharge is needed. So for high speed applications self-controlled precharge-free CAM (SCPF-CAM) is suitable. A 4T hybrid self controlled pre charge free Content Addressable Memory is proposed in this paper using CMOS 32nm technology. The observation shows that the circuit works at high speed, minimizes the search time and has high performance operation. When compared to the conventional SCPF-CAM, 8T CAM the proposed design reduces the number of transistors. The reduction in area is about approximately 20% and can be used in low power and low energy applications. In Synopsis HSPICE Predictive technology models were used for the implementation in 32nm CMOS technology. The work will be extended in future using FinFET technology where the leakage current can be minimized.

Recent developments in networking include the interest in software‐defined networking, in which OpenFlow switches are in charge of forwarding traffic by matching incoming packets with forwarding rules in their flow tables. Flow tables are commonly implemented in ternary content addressable memories (TCAMs). Typically, this type of memory tends to be extremely expensive and to be power‐hungry devices. The price and power dissipation of TCAM depend on the capacity of the memory. A blind design of memory size can result in dramatic degradation in performance and power efficiency of the entire network. In this study, the authors clarify this impact and show how the optimum value of TCAM capacity is attainable. They also propose a power consumption model for TCAM‐based OpenFlow switches. Simulation results show that the proposed solution reduces the average power consumption by 24% compared to the minimum link on method and by 11.5% compared to the minimum node on (MNO) method and thus power efficiency is better achieved when each memory is supplied by appropriate TCAM size.

Content addressable memory (CAM) is a specialized search engine mostly used for speeding memory lookup in network devices. Despite fast searching, activation of all comparison circuits in every clock cycle costs huge power. Power dissipation is more severe in high capacitive NOR match-line (ML) because of higher precharge activity and multiple transitions in ML. This paper proposes a two-layer ML scheme to reduce power due to frequent ML switching between precharge and evaluation phases. The complementary charging property of P and N matching circuits of NOR cells are utilized with the help of a ML precharge and sensing (MLPS) block to charge up only the matched entry while the mismatched entries are held at pre-discharged levels. Also, charging up the first layer due to mismatch limits the discharge levels of the mismatched second layer. These techniques reduce precharge activity besides lessening evaluate-power. Based on a 45-nm CMOS technology, post-layout analysis of the 64 × 32-bit proposed CAM at 1-V supply shows 56% and 24% reductions in precharge-power over a conventional CAM and a gated-power ML sensing CAM, respectively. In addition, the total ML power saving of approximately 2× is achieved when compared to a high-performance master-slave ML and a local-NOR global-NAND ML based CAMs besides decreased macro area. With the help of a charge-hold and charge-up sensing scheme, the proposed design achieves a match function in only 223.52 ps and dissipates 1.42 fJ/bit/search favouring it to be an efficient energy-delay design among the compared designs.

A complex-valued Hopfield neural network (CHNN) with a multistate activation function is a multistate model of neural associative memory. The weight parameters need a lot of memory resources. Twin-multistate activation functions were introduced to quaternion- and bicomplex-valued Hopfield neural networks. Since their architectures are much more complicated than that of CHNN, the architecture should be simplified. In this work, the number of weight parameters is reduced by bicomplex projection rule for CHNNs, which is given by the decomposition of bicomplex-valued Hopfield neural networks. Computer simulations support that the noise tolerance of CHNN with a bicomplex projection rule is equal to or even better than that of quaternion- and bicomplex-valued Hopfield neural networks. By computer simulations, we find that the projection rule for hyperbolic-valued Hopfield neural networks in synchronous mode maintains a high noise tolerance.

Implementing associative memory experiments with nanoscale memristors is an interesting subject, which can allow robots to mimic human thinking. This paper is concerned with a new emotion model of memristor-based neural network and its circuit implementation. The model has three inputs and two outputs, which can feel happy when it receives good news or feel sad when it receives bad news. Unknown news can be recognized through associative memory, which simulates human emotions. Associative learning and three kinds of forgetting process together make up the full-function emotion model. In addition, the Ag/AgInSbTe/Ta-based model closely related to the actual physical properties of memristors is used to design synaptic structures. The circuits of memristor-based neural networks are also simplified. Furthermore, the new emotion model is able to adjust the changing rate of emotion. The process reflects the fact that humans learn the same thing faster at the second time, compared with the first time. Finally, PSPICE is used to simulate all the circuits of the emotion model. The presented emotion model in this paper offers more possibilities for designing intelligent machines.

Link fault tolerance has been a hotspot in Software-Defined Networking (SDN) for many years. Both proactive and reactive schemes are proposed to guarantee network availability and robustness. However, the former wastes plenty of Ternary Content Addressable Memory (TCAM) and bandwidth resources, while the latter faces long fault recovery time. In this paper, we propose FTLink, an efficient and flexible link fault tolerance scheme in SDN. Firstly, through collecting the current network state information, we pre-generate a set of backup links for each link of the primary path of the flow. We formulate the backup links planning as a multi-objective optimization problem that minimizes the required switch TCAMs and link bandwidths. Combining flow characteristics, we develop a two-step heuristic algorithm, namely planning backup links for each link that transmits elephant flows with the greedy tracing method in step 1 and for each link that transmits mice flows with the bidirectional searching method in step 2, to determine the backup links set. Then, we introduce a global matching table in the controller to maintain the generated backup links and additional flow rules. Once monitoring a faulty link, FTLink looks up the matching table entries and enables the backup links via installing the additional flow rules into the switches to realize flexible fault recovery. Simulations show that FTLink is effective in terms of high-efficiency TCAM and bandwidth usage and produces an acceptable recovery time of less than 30 ms, compared with baseline schemes. The prototype tests under realistic network further confirm the efficiency of FTLink.

Significance Development of computational models of memory is a subject of long-standing interest at the intersection of machine learning and neuroscience. Our main finding is that overparameterized neural networks trained using standard optimization methods provide a simple mechanism for implementing associative memory. Remarkably, this mechanism allows for the storage and retrieval of sequences of examples. This finding also sheds light on inductive biases in overparameterized networks: while there are many functions that can achieve zero training loss in the overparameterized regime, our result shows that increasing depth and width in neural networks leads to maps that are more contractive around training examples, thereby allowing for storage and retrieval of more training examples., Identifying computational mechanisms for memorization and retrieval of data is a long-standing problem at the intersection of machine learning and neuroscience. Our main finding is that standard overparameterized deep neural networks trained using standard optimization methods implement such a mechanism for real-valued data. We provide empirical evidence that 1) overparameterized autoencoders store training samples as attractors and thus iterating the learned map leads to sample recovery, and that 2) the same mechanism allows for encoding sequences of examples and serves as an even more efficient mechanism for memory than autoencoding. Theoretically, we prove that when trained on a single example, autoencoders store the example as an attractor. Lastly, by treating a sequence encoder as a composition of maps, we prove that sequence encoding provides a more efficient mechanism for memory than autoencoding.

Extremely fast pattern recognition capabilities are necessary to find and fit billions of tracks at the hardware trigger level produced every second anticipated at high-luminosity Large Hadron Collider (HL-LHC) running conditions. Associative memory (AM)-based approaches for fast pattern recognition have been proposed as a potential solution to the tracking trigger. However, at the HL-LHC, there is much less time available, and the speed performance must be improved over previous systems while maintaining a comparable number of patterns. The vertically integrated pattern recognition AM (VIPRAM) project aims to achieve the target pattern density and performance goal using 3DIC technology. The first step taken in the VIPRAM work was the development of a 2-D prototype (protoVIPRAM00) in which the AM building blocks were designed to be compatible with the 3-D integration. In this article, we present the results from extensive performance studies of the protoVIPRAM00chip in both realistic HL-LHC and extreme conditions. Results indicate that the chip operates at the design frequency of 100 MHz with perfect correctness in realistic conditions and conclude that the building blocks are ready for 3-D stacking. We also present performance boundary characterization of the chip under extreme conditions. Extremely fast pattern recognition capabilities are necessary to find and fit billions of tracks at the hardware trigger level produced every second anticipated at high luminosity LHC (HL-LHC) running conditions. Associative Memory (AM) based approaches for fast pattern recognition have been proposed as a potential solution to the tracking trigger. However, at the HL-LHC, there is much less time available and speed performance must be improved over previous systems while maintaining a comparable number of patterns. The Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) Project aims to achieve the target pattern density and performance goal using 3DIC technology. The first step taken in the VIPRAM work was the development of a 2D prototype (protoVIPRAM00) in which the associative memory building blocks were designed to be compatible with the 3D integration. In this paper, we present the results from extensive performance studies of the protoVIPRAM00 chip in both realistic HL-LHC and extreme conditions. Results indicate that the chip operates at the design frequency of 100 MHz with perfect correctness in realistic conditions and conclude that the building blocks are ready for 3D stacking. We also present performance boundary characterization of the chip under extreme conditions.

Deep neural networks have achieved excellent performance in the field of image classification. However, even to state-of-the-art deep neural networks, there are still many critical images that are difficult to be classified effectively. Enlightened by the brain function of associative memory, we propose a novel classification optimization method based on deep neural networks to improve image classifiers. Psychologists have studied associative memory for a long time. A popular theory is that ideas and memory are associated together in the mind through experience. By applying this theory to object recognition, our method focuses on using the association among different images of the same category to improve image classifiers based on deep neural networks. The association, which is memorized by the LSTM network in our method, could infer a sequence of associative images and form inner data augmentation effectively. Further, we introduce the LSTM network into an end-to-end deep learning framework to boost the performance of image classifiers. Experiments on four benchmark datasets reveal that our method produces a consistent improvement to the existing powerful classifiers. Moreover, as far as we know, our method achieves the best classification accuracies of 97.3%, 96.0%, and 89.1% on Flower102, Caltech101, and Caltech256 datasets, respectively.

Memristive neuromorphic systems are emerging potential hardware platforms to implement artificial neural networks. Combining features of memristive neuromorphic systems with associative memory, this article proposes an associative-memory-based reconfigurable memristive neuromorphic system. In the proposed system, there are two neural networks: 1) the neural network for computing acceleration and 2) the neural network mimicking associative memory. Then, a case study of the system is presented, which includes an associative memory network to realize apple recognition and a computing acceleration network for iris classification. The associative memory network depends on associative learning to achieve the recognition function. In addition, during the corresponding forgetting process, the connections of the related synaptic circuits are cut off and sent to a synaptic circuit block, realizing variable circuit topology. Further, the synaptic circuits in the block are applied to construct the iris classification network, accomplishing the reconfiguration of the proposed system. The circuit structure of this classification network matches backpropagation (BP) algorithm well. Meanwhile, the network reaches a relatively high classification accuracy after training. In an iteration of the training, all the synaptic circuits that need to change can adjust weights synchronously, which improves training speed.

An implementation of associative memory based on a Hopfield network is described. In the proposed approach, memory addresses are regarded as training vectors of the artificial neural network. The efficiency of memory search is directly associated with solving the overfitting problem. A method for dividing the training and input network vectors into parts, the processing of which requires a smaller number of neurons, is proposed. Results of a series of experiments conducted on Hopfield network models with different numbers of neurons trained with different numbers of vectors and operated under different noise conditions are presented.

Ternary Content-Addressable Memory (TCAM) chips are used to store Forwarding Information Bases (FIB) in modern routers. TCAM provides next-hop lookup for IP packets at the line-rate. However, TCAM is expensive and energy-consuming; in addition, the constant FIB growth may lead to TCAM overflow problem. Yet only a small portion of FIB entries carries the most of network traffic. Thus, FIB caching, namely, installing the most popular entries in a fast memory, e.g., TCAM, may significantly minimize TCAM usage. To date, FIB caching architecture has not been widely deployed in backbone routers due to high cache-miss latency and the lack of an efficient cache replacement strategy. In this work, we leverage the concept of the programmable data plane to design a Programmable FIB Caching Architecture (PFCA) with two levels of cache. We present a pipeline-based algorithm to detect the least popular prefixes in a cache for a victim selection. We tested the prototype of PFCA using real traffic traces and an FIB with more than 599K entries, and showed that PFCA can be implemented using P4 programmable data plane language. Our results show that PFCA achieves 99.8% hit ratio for Level-1 cache with 20K entries and nearly 99.9% hit ratio for Level-2 cache with 40K entries. We also demonstrate that PFCA significantly reduces the number of BGP updates in the cache and thus makes the cache more stable.

Hardware search engines (HSEs) have been drawing significant attention in replacing software search algorithms in order to speed up location access and data association in modern systems. Content addressable memory (CAM) is one of the promising HSEs due to its parallel search accessibility. However, it is subjected to considerable dissipation which becomes severe while accessing many components including cells and associated matchlines (MLs) during every search. Ternary CAM (TCAM) based routing tables, especially employed in network systems for packet classification, has put a challenge to design energy-efficient architectures with high-performance and reliable look-up operation. Precharge-free CAM schemes are preferred solutions over precharge types to accomplish high-speed as well as low-power goals of associative memory design. In order to overcome the drawbacks of precharge based designs and also to improve performance during the search, we introduce a precharge-free ternary content addressable memory (PF-TCAM). The proposed searching approach enhances the rate of search by reducing half of the ML evaluation time as it eliminates precharge phase prior to every search by performing search in HALF clock cycle. A $32\times 16$ -bit proposed macro is designed using 45-nm CMOS technology and post-layout simulations at 1 V supply shows 56% and 63% energy efficiency improvements compared to conventional TCAM and compact TCAM respectively over 25 different search keys despite increasing evaluation speed by 50% with an area overhead of 1 transistor/cell over compact TCAM.

Due to the fully-connected complex structure of Artificial Neural Networks (ANNs), systems based on ANN may consume much computational time, energy and space. Therefore, intense research has been recently centered on changing the topology and design of ANNs to obtain high performance. To explore the influence of network structure on ANNs complex systems topologies have been applied in these networks to have more efficient and less complex structures while they are more similar to biological systems at the same time. In this paper, the methodology and results of some recent papers are summarized and discussed in which the authors investigated the efficacy of random complex networks on the performance of Hopfield associative memory and multi-layer ANNs compared with ANNs with small-world, scale-free and regular structures.

Memory-based reconfigurable computing rose to outperform conventional FPGAs in logic function density, as well as being less impacted by the programmable interconnection. However, the major drawback is that the area and power overheads are significant, and this gets worse in high-density, high-performance Memory-based Computing (MBC) devices. In this brief, we investigate the usage of analog memristive CAMs to improve the area density of MBCs, thus enabling denser memories and smaller power consumption. Simulation results indicate significant area and energy savings, up to $2.2\times $ and $2.6\times $ , respectively, compared to the non-volatile counterparts, at the cost of increasing latency by up to 20%.

Oscillatory neural networks based on insulator to metal transition of VO2 switches are implemented for image recognition. The VO2 oscillators are fabricated on silicon in a CMOS compatible process. A fully-connected network of coupled oscillators is investigated using programmable resistors as coupling elements. In this approach, input of the image information and data processing is performed in the time domain. In particular, tuning the coupling resistors allows to control the phase-relation between the oscillators. This is used to memorize and recognize patterns in an analog circuit. The concept is demonstrated experimentally on a three-VO2 oscillator network, whereas simulations are performed on a larger 9-oscillators circuit.

Static random access memory (SRAM)-based ternary content-addressable memory (TCAM) on field-programmable gate arrays (FPGAs) is used for packet classification in software-defined networking (SDN) and OpenFlow applications. SRAMs implementing TCAM contents constitute the major part of a TCAM design on FPGAs, which are vulnerable to soft errors. The protection of SRAM-based TCAMs against soft errors is challenging without compromising critical path delay and maintaining a high search performance. This brief presents a low-cost and low-response-time technique for the protection of SRAM-based TCAMs. This technique uses simple, single-bit parity for fault detection which has a minimal critical path overhead. This technique exploits the binary-encoded TCAM table maintained in SRAM-based TCAMs for update purposes to implement a low-response-time error-correction mechanism at low cost. The error-correction process is carried out in the background, allowing lookup operations to be performed simultaneously, thus maintaining a high search performance. The proposed technique provides protection against soft errors with a response time of 293 ns, whereas maintaining a search rate of 222 million searches per second on a $1024\times40$ size TCAM on Artix-7 FPGA.

With the rapid growth of the Internet traffic and the intensity of online transactions taking place, it is expected that the current routing needs careful modifications and smart innovations to ensure effective and reliable end-to-end packet delivery. This involves new feature developments for handling traffic with reduced latency to tackle routing scalability issues in a more secure way and to offer new services at cheaper cost. Considering the fact that prices of DRAM (Dynamic Random Access Memory) or TCAM (Ternary Content-Addressable Memory) in legacy routers are not necessarily decreasing at a desired pace, cloud computing can be a great solution to manage the increasing computation and memory complexity of routing functions in a centralized manner with optimized expenses. Such cloud integration to routing is becoming plausible as cloud providers now offer various pricing schemes and provide large-scale computing infrastructure to meet the users’ choice. Focusing on the attributes associated with existing routing cost models and by exploring a hybrid approach to SDN, we compare recent trends in cloud pricing (for both storage and service) to evaluate whether it would be economically beneficial to integrate cloud services with legacy routing for improved cost-efficiency.

Recently, various magnetic non-volatile ternary content-addressable memory (MNV-TCAM) cells that use magnetic tunnel junctions (MTJs) as storage units have been proposed to realize zero standby power. However, they still suffer from low reliability and high power consumption for search operation. In addition, the restrictions on the ordering of the TCAM array required by the using of the priority encoder to resolve the multiple match problem due to the ‘X’ results in large delay and high energy consumption for update operation. To address these issues, the novel MNV-TCAM cell is first proposed, aiming to achieve high-speed, low-power, and high-reliable search operation. In addition to the search data operation, it can realize a search length operation. By exploiting this search length operation, we then present circuit-level design of the MNV-TCAM with a priority-decision in memory technology, which can utilize the length information of matched words sorted in an arbitrary order to decide the highest-priority matched word by performing a three-phase search operation. It implies that the restrictions on the ordering can be eliminated, thus, improving the update speed and energy-efficiency. Finally, hybrid CMOS/MTJ simulations are performed to demonstrate its functionality and evaluate its performance in terms of search reliability, search speed, and search energy consumption.