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In this article, a novel p-GaN high-electron-mobility transistor (HEMT) with a built-in Schottky barrier diode (SBD) is proposed and investigated by TCAD simulation. The anode contact of the integrated SBD is isolated from the ohmic contact of the source electrode by a p-GaN isolation region. The cathode of the SBD is connected to the drain electrode. In the proposed Schottky barrier diode/HEMT (SB-HEMT), a channel under the p-GaN isolation region is turned on during forward conduction to further reduce the specific on-resistance ( $R_{{on},sp}$ ). With a minimum sacrifice on $R_{{on},sp}$ , the reverse on-state voltage, $V_{R-{on}}$ (at a current density of 50 mA/mm), for the SB-HEMT is reduced by 33% (from 2.43 to 1.62 V) when compared with a conventional HEMT (C-HEMT). Compared with the C-HEMT with a separate on-chip SBD (C-HEMT/SBD), the SB-HEMT shows much better trade-off between $V_{R-{on}}$ and $R_{{on},sp}$ . The total switching loss ( $E_{total}$ ) of the proposed SB-HEMT with resistive load is lower than that of the C-HEMT and is reduced by up to 21% when compared with that of the C-HEMT/SBD with different area ratio between the HEMT and SBD regions.

Conventional di/dt and dv / dt control and gate protection techniques for gallium nitride (GaN) power transistors usually employ external controllers, isolation circuits, discrete pull-up, and pull-down resistors. With large number of components, power modules become more complex and may introduce additional parasitic. Gate driver ICs with segmented output stages and dynamic gate driving have been reported previously to be effective in simultaneously suppressing gate ringing and overshoot voltage while maintaining fast switching speed. However, the programming for dynamic gate driving is rather complicated, requiring the user to load a sequence of driving patterns obtained from trial and error ahead of time. This article presents a gate driver IC for E-mode GaN power transistors with seven segmented output stages. More importantly, it offers a simplified programming method for the dynamic gate driving pattern. The optimal gate drive pattern can be defined by simply adjusting one external bias resistor. The proposed method eliminates the complex trial and error digital control, and can potentially promoting the wider acceptance of dynamic gate driving by the industry. The timing resolution for the gate drive pattern can be varied in steps from 0.5 to 5 ns. It can also be used to drive many commercially available GaN power transistors.

Dead-times are necessary in switching output stage to avoid shoot-through current between the high side (HS) and the low side (LS) power transistors. However, excessively long dead-times can lead to unwanted reverse conduction and power loss. Sensing the duration of reverse conductions are especially difficult for high-voltage enhancement mode ( e -mode) gallium nitride (GaN) HEMTs due to their fast switching speed. High-precision sensing circuits are required for dead-time correction as the load current changes and to withstand large voltage swings. Traditional CMOS-based sensing circuits (e.g. standard logic gates) are not suitable for GaN-based converters as they can only handle limited voltage ranges. In addition, severe undershoots (up to -4 V) may damage the sensing circuit. Here, a gate driver IC for e -mode GaN power output stages capable of detecting the presence of reverse conduction with a best resolution of 0.66 ns, a dead-time adjustment resolution of 0.33 ns, and with on-chip closed-loop control is presented. In addition, a novel reverse conduction sensing circuit that can accommodate the large voltage swings at the switching node (SW) is also described.

Conventional insulated gate bipolar transistor (IGBT) current sensing and protection techniques usually employ discrete sensors, such as lossy shunt resistors, and may involve accessing the high-voltage collector load of the IGBT. This would normally present difficulties for integration. This paper presents an IGBT gate driver IC with a collector current sensing circuit and an on-chip CPU for local data processing. This IC is prototyped using a TSMC 0.18 μm 40 V BCD Gen-2 process. The collector current sensing technique is based on the unique Miller plateau relationship between the gate current and collector current ( $I_{C}$ and $I_{G}$ ) for a particular gate resistance ( $R_{G}$ ). It allows a cycle-by-cycle measurement of IC during both turn- on and turn- off transients without any extra discrete components. The temperature variation is compensated internally by the on-chip CPU using polynomial curve fitting. This technique only monitors the low-voltage signal at the gate terminal, without the need to handle any high-voltage signal on the collector/load side. Measurements using a double pulse test setup show an accuracy of ±0.5 A over the current ranges of 1–30 A for turn- on and 1–50 A for turn- off from 25 to 75 °C.

The application of a segmented gate driver (SGD) to detect aging and provide automated compensation for SiC MOSFETs is presented. By dynamically modifying the gate resistance during switching transients, we can stretch the Miller plateau (MP) duration. The MP level is used as an indicator for the health condition of the SiC power MOSFET. A digital control circuit analyzes the aging effect and provides a control signal to an integrated boost converter, which powers the gate drive voltage. In this manner, the gate drive voltage can be adjusted to compensate for changes in the MOSFET performance. The same SGD can also be used to suppress gate ringing to protect the SiC power device against over/undershoot damage. This is of particular importance at elevated gate voltage.

Compact liquid cooled gallium nitride (GaN) intelligent power modules (IPMs) are fabricated using direct bonding methods. A half bridge module with 15 A GaN high electron mobility transistors (HEMTs) is flip-chip bonded on active metal brazed (AMB) substrates using pressureless nanosilver sintering. The AMB substrates are pre-brazed on a copper liquid cooler. The geometries of the AMB substrates and the GaN IPMs are determined based on thermal simulations using finite element analysis (FEA). The prototype GaN IPMs are tested in a buck converter configuration. The module temperatures are below 35 °C for up to 35 W of output power. The proposed process flow offers a simple IPM packaging solution to power semiconductor companies using prefabricated liquid coolers with brazed AMB substrates from automotive parts manufacturers.

To suppress excessive gate voltage swings during switching, a resistance is normally used to limit the charging rate of the gate capacitance (C G ). Modern solutions, such as segmented gate drivers, can be used to dynamically control the gate resistance R G to minimize ringing while maintaining the fast-switching speed of the transistor. The timing or dynamic pattern of the gate resistance is critical in the optimization of the device and circuit performance. Traditionally, this gate drive pattern is obtained via a trial-and-error or iterative procedure. This paper proposes a method to automatically determine the timing intervals by monitoring the gate signal (V GATE ) through slope sensing with analog filter and subsequent mixed-signal processing. The output timing indicator (T SEG ) is then fed back to the segmented gate driver IC to achieve automatic adjustments of the dynamic driving pattern. The proposed system is able to determine the optimum T SEG for dynamic gate driving. For the SiC power MOSFET used in our testing, segmented R G driving between 2.5 and 10 Ω does not hinder the switching speed, while keeping the undershoot of the SiC module to be within 1 V or 5% of the total applied gate voltage.

Intelligent power modules (IPMs) are critical components within electric vehicle (EV) power inverters that require effective liquid cooling. IPM manufacturers are constantly evolving their designs in lockstep with advancements in switching transistor technology to deliver more power with increased efficiency. In particular, the imminent arrival of new IPMs based on wide-bandgap semiconductors poses new thermal challenges due to smaller die areas and increased heat fluxes. The question arises whether the traditional liquid cooling strategies will be sufficient to cool the next generation of EV IPMs as semiconductor technology transitions from Si IGBTs, to SiC MOSFETs and GaN power HEMTs, with progressively decreasing die areas. In this paper, this question is explored through an analytical solution of the heat equation in a representative model of a typical EV IPM heat exchanger (HX). It is shown that there exists a practical thermal limit to traditional EV IPM HXs which must be addressed by IPM and automotive parts manufacturers together. Thermal benchmarking experiments, supported by numerical simulations, of two commercially available IPMs are performed, confirming no violations of the derived thermal limit.

Gate overshoot voltage prevention when driving E-mode GaN-based HEMTs is essential for system reliability and EMI suppression. Active gate drivers have been demonstrated to suppress gate voltage overshoot while maintaining fast turn-on. However, they normally require complex driving patterns that are determined using trial and error approaches. In this paper, an active gate driver with an integrated pattern generator is proposed to simplify the control of the dynamic gate driving strength pattern. For best trade-off between overshoot and transition speed, the gate resistance (or gate driving strength) must remain low but with a large resistance switched in briefly during the turn-on transition period. Switch timing of the driving pattern varies with load conditions and the types of transistor. To simplify the programming of the driving pattern, the gate driving strength can be controlled by changing only one external bias resistor in the proposed design. This in turn sets the bias current of a delay chain to adjust the timing of the gate driving strength pattern. The proposed design aims to create a systematic approach to simplify the selection of the gate driving strength pattern.

GaN power transistors are well suited in high frequency, high temperature and high power-density applications. This paper investigates different gate driver designs for GaN power transistors, including fundamental driving concerns, current commercial products, popular gate driving features, and design trends for the suppression of gate node ringing. Many smart gate drivers offer features such as intelligent on-chip CPU for flexible digital control, adjustable gate voltage levels, multi-stage driving speed for slew-rate control, precise timing control, current sensing capability for close-loop regulations, and active gate driving mode with continuous optimized dead-time. This paper provides an overview to modern gate driver design trends and challenges for GaN power transistors.

Detection of reverse-conduction in GaN-based switched-mode power converters is essential to reduce power loss and to protect the circuit from severe undershoot voltage. In this paper, an active clamping SenseFET circuit is proposed to measure the duration that the low-side GaN HEMT is in reverse-conduction and with protection from the high voltage at the switching node. The output of the SenseFET clamping circuit is processed by a custom designed gate driver IC. This IC is fabricated using TSMC's $0.18\ \boldsymbol{\mu} \mathbf{m}$ BCD GEN2 process for driving e-mode GaN power HEMTs with an on-chip closed-loop dead-time correction circuit. The one-step correction mode can optimize the dead-times for both the turn-on and turn-off edges in one switching cycle for switching frequencies of up to 10 MHz with 0.32 ns precision. This allow the power converters to maintain optimal conversion efficiency over the full output current range.

Tuberculosis (TB) is a continuing major threat to global health and a leading cause of death, particularly in developing countries. In this study, we aimed to identify a specific and sensitive diagnostic biomarker and develop a vaccine to prevent this disease. We investigated membrane proteins to reveal biomarkers in serum and peripheral blood mononuclear cells (PBMCs) obtained from TB patients. We employed Western blotting to evaluate serological immunoglobulin G levels, and Enzyme Linked Immunospot (ELISpot) to assess the antigen-specific cellular interferon-γ secretion from PBMCs after membrane protein stimulation. A total of 219 membrane proteins were identified, 52 exhibited at a higher levels than the 38-kDa prositive control. Of these 18 exhibited reacted ratios above 1, especially Rv1111c (427–981), with a ratios at 3.38. Accuracy and sensitivity were markedly higher for the top two antigen candidates, Rv0232 and Rv1115, after two rounds of ELISpot tests than ESAT-6 in the commercial kit (42.15 and 43.62%, respectively). These two proteins were administered to mice to detect whether they acted as effective antigens in vivo. These data provide a comprehensive view of the membranes involved in humoural and cellular immune responses that may be used as biomarkers for TB and candidates for a vaccine.

In this paper, an integrated smart gate driver IC with segmented output stage topology, programmable sense-FET, current sensing circuits and an on-chip stacked-based CPU for flexible digital control is presented. This IC is fabricated using TSMC's 0.18 μm BCD GEN2 process for driving a d-mode GaN power HEMT in cascode configuration. Using a segmentation technique, this IC can dynamically adjust the gate driving strength during switching transition to achieve slope control and EMI reduction. Programmable sense-FET and current sensing circuit monitor the load current for peak-current regulation. The embedded CPU can update all digital configuration bits on-the-fly. In dynamic driving mode, current spike at turn-on transition is reduced by 83% without sacrificing the switching speed. Current sensing circuit can detect peak current value and response within 5 ns. The pre-stored driving patterns can be loaded to the driving circuit in 1 μs under active driving mode.

Analysis of the radio tracking data from the Pioneer 10/11 spacecraft at distances between about 20–70 AU from the Sun has consistently indicated the presence of a constant acceleration of 8.6× 10−8 cm/s−2 directed towards the Sun. This has been one of the most interesting and intriguing astrophysical problems in the last decade. Currently, an independent research rises from the planetary long-term orbital evolution study and may be helpful to understand the nature of Pioneer Anomaly. Furthermore, calculation shows that the Pioneer data match with the new discovery’s prediction very well.

Space probes now asks for a correction in aeronautic mechanics. Analysis of the radio tracking data from the Pioneer 10/11 spacecraft at distances between about 20–70 AU from the Sun has consistently indicated the presence of a constant acceleration of 8.6× 10−8 cm/s−2 directed towards the Sun. Currently, an independent research rises from the planetary long-term orbital evolution study and may be helpful to understand the nature of Pioneer Anomaly. Furthermore, calculation shows that the Pioneer data match with the new discovery’s prediction very well. Such nova theory will improve spacecraft and space shuttle design, and could enhance the accuracy, ensuring them into the designed orbit prompt.

In this paper, an integrated EDMOS H-bridge that incorporates both segmented output transistors and segmented gate drivers is presented. This fully segmented design approach allows the output resistance of the H-bridge and the output resistance of the gate drivers to be dynamically adjusted. Dynamic adjustment of these parameters allows for the continuous optimization of the power conversion efficiency of the H-bridge over a wide range of output currents. The IC chip is fabricated using TSMC's 0.18 μm BCD Gen-2 process technology. The H-bridge is operated with a 10 V input, 2 V output and a load current between 0.02 A and 4 A. The presented design achieves power conversion efficiency improvements of 32% and 8% at light load current and heavy load current, respectively, when compared to traditional fixed power transistor designs. Furthermore, the dynamically adjustable output resistance of the gate drivers allows for suppression of switching node ringing and conducted EMI (CEMI) by 5.5 dB with no a significant reduction in efficiency.

It is well-known that 'wound excision' is essential in the primary treatment of wounds in war, particularly thorough debridement of the devitalized tissues around the path of a penetrating projectile. Nowadays, the gunshot wounds in peacetime have become prevalent. Instead of the traditional method of 'wound excision' (excision), we used the method of 'incision and drainage' (incision) in the primary surgery of these gunshot wounds of extremities. To determine the treatment effectiveness of these different surgical methods (incision and excision), two groups of dogs were shot in the proximal part of one hind leg with an American M-16 rifle. One group was treated by the method of 'excision'; in the other group 'incision' were performed. No difference in infection rate was noted between the two groups. Similarly, no difference in bacterial count was found between the two groups during the observation period. Also, there was no difference in healing time; the wounds in both groups had healed by 19.2-21.4 days. Microscopic examination revealed a little normal muscle tissue in the necrotic zone of the incision group which might augment the repair process. These results suggest that there are no differences in the effectiveness in preventing infection between the two methods. 'Incision' might be superior to 'excision' for the management of the gunshot wounds of extremities in peacetime, as it involves a simple operation and there are advantages for tissue healing.

Background The leukodystrophies are a group of disorders that selectively involve degeneration of the white matter of the central nervous system. Recent discoveries in genetics have expanded our knowledge of hereditary leukodystrophies. We aimed to investigate the phenotypic spectrum of leukodystrophy genes without selection bias, thereby expanding the genotype–phenotype correlation. Methods 18 patients with adult-onset, undiagnosed leukodystrophy were analysed with focused exome sequencing (SureSelect Focused Exome, Agilent Technologies, Santa Clara CA, USA). Suspected mutations were subsequently confirmed by Sanger sequencing. Findings We made a genetic diagnosis in six cases. Interestingly, in this adult-onset cohort, only one individual was found to have a mutation in an autosomal dominant gene ( CSF1R ) with the remainder with homozygous or compound heterozygous variants in the following autosomal recessive genes: POLR3A, EIF2B5, DARS2, MRPS22 , and TREM2 . No gene was responsible for more than one case, reflecting the extreme clinical and genetic heterogeneity of adult-onset leukodystrophy. These genes are responsible for mitochondrial health, RNA transcription, and microglial signalling. Interpretation Focused exome sequencing is a non-hypothesis driven approach allowing for association of clinical phenotype with otherwise unsuspecting molecular pathways. It is a cost-effective method that should be considered early in the diagnostic process, avoiding time and money spent on other more invasive investigations. This is of paramount importance for the patient in terms of early treatment and appropriate genetic counselling. Funding National Institute for Health Research, Leonard Wolfson Experimental Neurology Centre.