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Phase noise, lock range, lock time, and power consumption are becoming the dominant performance parameters in a charge pump phase locked loop (CP-PLL) especially at high frequencies. Though the PLL is having several blocks, the voltage-controlled oscillator (VCO) is the most impactful block considering the above parameters. Hence, it has been a call for better designing using the MOSFETs of a VCO circuit for an efficient PLL for several decades. In this work a VCO circuit is designed which uses the sleepy stack transistors to reduce the leakage current and later the new VCO is incorporated the PLL. With a wide lock range, this novel PLL architecture promises to offer better phase noise lock time and power consumption. This is possible due to the low leakage current that is produced by the stack transistors in the VCO. To support the above claims, the PLL using current starved stack VCO is designed and simulated in 90 nm CMOS technology. The simulation results shows that the VCO exhibits a phase noise of −78.28 dBc/Hz @1 MHz offset frequency while the PLL incorporating the same VCO has a lock range of 1.3GHz–1.5GHz. The power dissipation of the PLL is 46.05 μW, and the figure of merit (FOM) of the PLL is calculated to be −91.75 dBc/Hz.

In this work, a detailed investigation of RF and linearity analysis of junction-less Gate All Around (JLGAA) MOSFETs through SILVACO TCAD device simulator have been demonstrated. The impact of different metal gate work functions on various RF parameters such as drain current, transconductance (gm), output conductance (gd), gate capacitances (Cgs and Cgd), transconductance generation factor (TGF), cut-off frequency (fT), intrinsic gain(Av) and Gain trans-conductance frequency product (GTFP) are investigated. Furthermore, the impact of different metal gate work functions(ωM) on various linearity parameters such as gm2, gm3, VIP2, VIP3, IIP3, IMD3 were also investigated. It is observed that lower value of metal gate work function is suitable for radio frequency integrated circuit (RFIC) applications.

In today’s world, semiconductor nanowire GAA-MOSFET devices have stimulated a lot of scientific research interest in the field of semiconductor. It has been observed as one of the strong and gifted structure for future generation nano-scaled devices and integrated circuits (ICs). Basically, the term nanotechnology is the key powerhouse of semiconductor device engineering and technology to produce and operate the materials at nano-meter scale (10−9 m or 1 nm) either by top-down approach where the bulk materials are converted to a group of nano particles (atoms) or by bottom-up approach where the single groups of nano particles (atoms) are converted to the bulk materials. Nanowire GAA MOSFET is considered as work horse in semiconductor industry due to great electrostatic controllability over the channel and tight coupling. This review article investigates the different structural designs of nanowire devices using nanotechnology approaches for future device applications.

Short channel effects (SCEs) along with mobility degradation has a great impact on CMOS technology below 100 nm. These effects can be overcome by using gate and channel engineering techniques which will improve mobility of the charge carriers, thus eventually improving drain current and trans-conductance of the device. In this work, the speed of operation for DG MOSFET is improved by reducing the channel length where dual-material gate-stack is deployed to avoid the drain-induced barrier lowering (DIBL) and hot carrier effects. In the presented device, the metal closer to the source and drain has higher and lower work function, respectively which causes a significant decrement in the peak electric field at the drain side and so the SCEs. The carrier mobility is also increased due to enhanced electric field in the channel, near the source, caused by higher work function gate material which, in turn, increases the MOSFET’s driving current. The screening effect reducing SCEs and an increment in the acceleration of the charge carriers in the channel are mainly attributed due to higher and lower threshold voltage found near the source and drain, respectively.

Silicon nanowire (SiNW) structures are the essential foundations of the next generation highly efficient and lowcost electronic devices because of their specific chemical, optical, and electrical properties. In recent decades, the production of pure Si NW arrays with the ability to tune the wire density and dimensions has been intensively studied. This paper demonstrates the performance of silicon nanowire (Si NW) array based cylindrical gate all around (GAA) MOSFET using quantum transport model in lower technology nodes. With an improvement in drain current and lower value of threshold voltage, the proposed structure is proving itself as one of the leaders in GAA MOSFET family. Again the study includes the effect of variation in gate voltage on the electrostatic potential of individual nanowires and the potential developed at the channel-source/drain interface. The improved ON current with superior electrostatic integrity due to silicon pillars is showing the possibility of this device towards future development in CMOS technology. Finally, the article includes the integration of nMOS and pMOS to realize the CMOS inverter for high speed and noise immune characteristics.

This paper presents the effects of manufacturing process variations on the phase-locked loop (PLL) performances like lock time, lock range and phase noise. At higher operating frequencies, due to p...

In a continuous effort to keep the Moore’s law alive in lower technology node without deteriorating the device performance, several device engineering techniques are introduced. These engineering techniques involve channel engineering and gate metal engineering also. Evolution of Multi gate MOSFET devices from conventional planar structure to gate all around (GAA) is continuously going on. With unique design, GAA MOSFET is measured as one of the best devices for better electrostatic control. The threshold voltage of a device depends on the work function of metal gate electrode. This work introduced a linearly modulated work function (5eV-4eV) metal gate along z-axis. This work demonstrates the advantages of work function modulated metal gate on the DC performance characteristics in lower technology nodes. An improved drain current (Id) with lower threshold voltage (Vth) indicates the superiority of the device for future generation applications.

This work is a Raspberry Pi-based prototype that has been built while keeping both the Indian agricultural scenario and hobbyist backyard gardeners in mind. It aims not only to act as a solution to conventional method of growing plants but also to approach along the lines of sustainable development. With our project, we are also aiming to optimize the amount of resources required to grow a plant. The model acts as the brain of the plant by providing directions to the technical implementations of the setup such as an attached pair of wheels and a water pump to act according to the requirement. This prototype could be a possible solution to majority of the urban population planning to have potted plants and greenery in their apartment but with space, time and effort constraints. Further details like implementation, advantages and future are mentioned in the next sections.

Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.72.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX.

In modern SOC design SRAM has become an integral part owing to its capability to form a bridge and overcome the speed mismatch problem between the high speed processor and the low speed data storage devices. Because of the read and write operation of SRAM cell having conflicting transistor sizing requirement, it is very difficult to maintain the transistor size to satisfy both the needs. The destructive nature of read operation enforces a serious thought about SRAM cell data stability. Transistor sizing and cell stability already being a critical problem becomes even more critical when we consider the process and temperature variation. Thus the SRAM should be designed with keeping the process and temperature variation in mind. The random fluctuation in device parameters such as transistor width, length, oxide thickness, oxide capacitance and doping concentration leads to variation in the threshold voltage and other transistor characteristics. The change in these transistor characteristics alters the SRAM cell performance. Hence this should also be taken care of to ensure the cell performance to be in the desired range even in presence of random fluctuation during fabrication process. The various performance measure such as SNM, write SNM, speed and power consumption must be tested under worst process corner as well over a wide temperature range to ensure that they lie in the acceptable range during worst operating condition. Also these parameters must be tested using Monte Carlo simulation to ensure a robust operation in presence of random fluctuation during fabrication process.

In this work, we have analyzed the novelty of the Gate Stack Double Gate (DG) MOSFET with respect to different spacer variations in order to reduce the short channel effect challenges and simultaneously increasing the device performance. Silicon is used as the channel material along with the gate stacked technology for studying the analog performance and Radio Frequency (RF) performance of the device. For gate stacking, two types of oxides are used- one denoting low-K i.e SiO 2 and the other as high-K i.e- HfO 2 . Spacers with various permittivities were used to understand their effects on the performance of the device. The simulation result shows that the use of spacer material affected both the analog and RF behavior of the device significantly. The computer aided design (TCAD) simulations have been carried by SILVACO International.

This paper presents the performance of SRG Tunnel FET biosensor. Here the different device parameters are deliberate to meet the requirement of the technological development. Focus is made on how TFET can be a substitute ahead of CMOS characteristics for biosensor mean and to more enhance the low power design policy to facilitate it for IOT purpose. There is a experimentally demonstration has been done for nanogap cavity A nanogap cavity region. Investigation of the staggered gap hetero junction SRG TFET was done. The results are obtained using Silvaco software.

The modern electronics gadget has influenced tremendously every aspects of life. The demand to add more and more functionality has forced to increase the performance of the processor. To ensure a robust data supply to the processor a high performance, stable and low power SRAM is also of utmost necessity. An indirect read SRAM cell is proposed here which eliminates the read noise insertion to increase the data stability. It also consumes 41% less energy compared to the conventional SRAM cell. The SRAM cell is designed to be written single ended using only one write access transistor. The cell reduces the energy consumption by reducing the short circuit current and also reducing the number of leakage path. The cell also has a high write speed since the storage data node is a floating node and not connected to the ground.

Low voltage operation and low power consumption is of paramount need in integrated circuits which are employed in portable devices. Floating gate MOS (FGMOS) transistor is an analog technique to achieve low power while maintaining performance in various applications such as neural networks, PLL, D/A and A/D converters and memory circuits. This paper deals with various FGMOS techniques with supply voltage $\mathrm{V_{DD}}=220\mathrm{mV}$ operating in sub-threshold region which is very crucial for lowering power dissipation and achieves higher speed compared to CMOS circuits. The proposed work is validated through inverter circuits using TSMC $\mathbf{0.18\mu{m}}$ technology in mentor graphics tool.

Power theft is normally done by two methods that is bypassing or hooking. So to detect it, a system (current measuring and comparing) is proposed in which the household distribution of current is done indirectly from the electric pole to an intermediate distributor box and then to the individual houses. The current is measured periodically in the distributor box and is posted to the server database for each house using GSM/GPRS module. Similarly, for each house electric meter is designed which can measure the value of the current and post the same to the server database periodically using GSM/GPRS module. At the time of the installation of the electric meter the details of the users are stored in the database through a user friendly mobile application including the address, latitude, longitude using mobile GPS and the photograph of the user's house/area. Upon successful comparison between the current values from distributor box and electric meter in the server if we get a marginal difference between the currents then the theft is detected. Finally, the details of the user are shared with the authorized mobile application including the address and photograph of the area. The latitude and longitude are also used to show the area of theft in Google maps. And hence the required steps are taken. The same process is used for hooking but on the individual electric poles.

This paper presents the performance of non-uniformed doped double gate (DG) MOSFET with different spacer variations with an aim to analysis the effects of short channel and various performance metrics. In this work we have taken silicon as the channel material with non-uniform doping for studying the analog and RF performances. Spacer's materials having different permittivities were used to understand their effect on the device performance. Based on the simulations, we can conclude that analog and Radio Frequency performance of the device shows an significant improvement with addition of spacer layer. We have used computer aided design (TCAD) simulations by SILVACO International.

This paper reviews the design of phase locked loop (PLL) using recently reported charge pump circuits. Lock time, phase noise, lock range and reference spur of each charge pump circuit are investigated. Though improved charge pump circuits are designed recently, their performance is not as effective as the basic charge pump PLL (CP-PLL). Initially the design of PLL using the basic charge pump is completed in this paper and then the PLL using improved charge pumps are redesigned in CMOS 180 nm technology and simulated using Cadence Virtuoso Analog Design Environment. Finally all the charge pumps are compared with respect to the PLL performances. The current starved voltage controlled oscillator (VCO) used for the design of PLL brings about a tuning range of 119.5 MHz to 2.3 GHz. The PLL using different charge pumps produces a lock time which varies from 204 ns to 329 ns. The other parameters like lock range, phase noise and reference spur are also examined.

In this work, we have studied the effect of variation in length of GaN gate with p-type doping concentration on the DC performances of AlGaN/GaN normally-off HEMT using 2D Atlas TCAD simulator. A comprehensive simulation is undertaken on the proposed device to examine different performance parameters such as drain current, transconductance factor, energy band diagram, and surface potential with respect to change in p-type GaN gate lengths. The gate lengths are varied from 60 to 90 nm, and it is noticed from the simulation results that with a decrease in gate length the drain current increases and transconductance increases. A proper optimization of gate length is indispensable to preserve the normally-off mode operation and at the same time enhancing certain performance parameters.

The topic SRAM Macro basically explains the memory unit associated with any processor. Here Macro signifies that the explanation will not only contain the memory unit but also contain all the peripherals like control block, I/O block, row & column decoders etc. SRAM signifies that the fundamental memory unit is the SRAM cell. SRAM is nothing but static random access memory that means statically we can access the memory content of the cell. SRAM has some advantages over DRAM that's why SRAM is frequently chosen and the main advantage is SRAM does not require regular periodic refreshment, means once something is stored in a SRAM cell then that will last till power is on. But in case of DRAM regular refreshment is required. Therefore SRAM is widely used. Again SRAM is classified into several categories like 4T SRAM, 6T SRAM, 8T SRAM etc. depending upon the no. of MOSFETs it contains i.e. in 4T SRAM 4 MOSFETs are used, in 6T SRAM 6 MOSFETs are used, in 8T SRAM 8 MOSFETs are used & like wise. Among these, 6T SRAM is widely used because of its advantages over others. In 4T SRAM as no. of MOSFETs are less so it consumes less chip area but here voltage swing is very high so 4T SRAM is discarded from stability point of view. Now if we'll consider the 8T SRAM then it's highly stable but due to more no. of MOSFETs it consumes more chip area so 8T SRAM is discarded from area consumption point of view. Therefore finally 6T SRAM is chosen because it gives stability as well as it consumes moderate chip area.

Charge Pump in a phase locked loop (PLL) generates non-ideal effects such as current mismatches at the output node and switching errors at the pull up and pull down networks. This work presents a novel transmission gate cascode current mirror charge pump circuit. The switches incorporated in this work are Transmission Gates which help to reduce various switching errors, and only one supply independent reference current source is used to have a minimum current mismatch. The performance analysis carried out in the Cadence design environment, and it is observed that the loop locks in 25 ns which is 50 % faster than the conventional charge pump. The control voltage absolutely has no ripple in it after locking which reduces the reference spur further. It could be achieved because the current mismatch is only about 7 %. This PLL operates at 2.5 GHz having a wide lock range of 0.5---2.8 GHz where average power consumption is 1.74 mW. Due to the use of cascade current mirror circuits, the output voltage swing that can be obtained is 1.79 V.

All most all computers and microcontrollers have several serial data ports used to communicate with serial input/output devices such as keyboards and serial printers. By using a modem connected to a serial port serial data can be transmitted to and received from a remote location via telephone line. The serial communication interface, which receives and transmits the serial data is called a UART (Universal Asynchronous Receiver-Transmitter). RxD is the received serial data signal and TxD is transmitted data signal. In this project UART is implemented in virtex II pro FPGA chip due to low cost, high speed, reprogram ability and fast time to market.

CMODE (Combining Multi-objective Optimization with Differential Evolution) technique has been proved to be very efficient to design a low power low phase noise LC Voltage Controlled Oscillator (VCO). The proposed technique optimizes the power consumption and phase noise of the 3.3-4 GHz LC-VCO for GSM-900 standard. The performance indices are optimized by using CMODE technique in MATLAB and corresponding optimal design parameters are obtained and implemented in 90 nm CMOS technology. The Figure Of Merit(FOM) is found out to be -192.436 dBc/Hz @ 3 MHz and -180.1 dBc/Hz @ 100 kHz offset with a very low power consumption of 849.7 μW.

FOM (Figure Of Merit) is a novel performance yardstick of VCOs. Designing LC VCO circuit with desired specifications is highly time consuming and tedious job. In this paper CMODE (Combining Multi objective Optimization with Differential Evolution) optimization technique is used to design an LC VCO of optimal FOM with a target frequency of 2.5 GHz. The design parameters of LC VCO are obtained from the CMODE algorithm used in the MATLAB environment to optimize FOM. By using these parameters the LC VCO circuit is designed and synthesized in 90 nm CMOS technology in the Cadence Spectre Analog Design Environment(ADE). This VCO achieves phase noise of −119.7 dBc/Hz at 1 MHz offset while consuming 515 uW power with a tuning range of 10.53%. The FOM is obtained to be −190.26 dBc/Hz at 1 MHz offset. Hence the best performance index meeting the desired specifications is obtained in a single run of the algorithm.

Application Specific Instruction Set Processor (ASIP) is becoming essential to convergent System on Chip (SoC) Design. Usually there are two approaches to design an ASIP. One of them is at Register Transfer Level (RTL) and another is at just higher level than RTL and is known as Electronic System Level (ESL). Application Description Languages (ADLs) are becoming popular recently because of its quick and optimal design convergence achievement capability during the design of ASIPs. This paper presents the implementation and optimization of an ASIP using an ADL known as Language for Instruction Set Architecture (LISA) and CoWare Processor Designer environment. The CoWare Processor Designer (PD) generates Software Development tools and synthesizable RTL for the processor. The generated RTL can be synthesized using Cadence Encounter.

Cholesterol content of major lipoprotein fractions along with total cholesterol (Tc) and triglyceride (Tg) were measured in 65 samples from 35 women using levonorgestrel contraceptive implant, Norplant-2 from the third month of implantation until the end of second year along with twenty-five healthy controls. There were significant decreases in all the fractional lipid values, Tc and Tg, up to the sixth month followed by a gradual rise of all lipid parameters except HDLc which remained much below the control level. Interestingly, VLDLc exhibited a significant rise at the end of the second year.Total cholesterol, high density lipoprotein cholesterol (HDL), low density lipoprotein cholesterol (LDL), and very low density lipoprotein (VLDL) were measured in 35 Indian women using the levonorgestrel-containing implant, Norplant, and in 25 controls. 65 blood samples were taken from the 35 Norplant users at 3,6, 12 and 24 months after placing the implants. Assays were done by quantitative fractionation methods. Serum HDL fell significantly at 3 months (p0.02), and further over 6-24 months of use (p0.001), from 40.0 to 31.8 mg/dl. The control value was 49.2. LDL and VLDL fell to a minimum at 6 months, and rose somewhat at 12 and 24 months. Total cholesterol also was depressed to a mean of 128.8 at 6 months, then rose to 148 mg/dl at 24 months. Control total cholesterol was 190.1. Triglyceride levels followed a similar pattern. The ratios of HDL/total cholesterol and VLDL/total cholesterol in this series suggest increased risk of coronary heart disease. In contrast, the fall in total cholesterol to values below 100 mg/dl in some subjects is cause for concern. These data add to the widely discrepant findings of serum lipoproteins in different studies on Norplant users.