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This paper is dedicated to the "50 Years of the Relevance Problem" - a long-neglected topic that begs attention from practical statisticians who are concerned with the problem of drawing inference from large-scale heterogeneous data., Comment: Revised (much-improved) version. The procedure (including all the datasets) is implemented in the R-package LPRelevance

Gate stack process (pre-clean, IL, IL/HK interface, HK, post-HK Nitridation) impact on gate leakage, SILC and PBTI is analyzed. IL and HK thickness, channel/IL and IL/HK energy-barrier offsets impact on gate leakage and SILC response from generated bulk traps inside IL and HK is quantified. Time kinetics of generated IL and HK bulk traps for SILC, and IL/HK interface traps for PBTI are simulated by a generic Reaction-Diffusion-Drift (RDD) framework. Model is validated using measurements from differently processed HKMG stacks.

In this work, we propose a novel double quantum well (QW) high electron mobility transistor (HEMT) structure. The DC and RF performances of this proposed structure are compared with those of conventional single QW HEMT. According to this work, the peak drain current of 651 mA/mm is achieved in conventional single QW HEMT, and the peak drain current of 758 mA/mm is achieved in proposed double QW HEMT. Also, the peak transconductances related to the proposed HEMT and conventional HEMT are compared. The peak current gain cut-off frequencies of two structures are compared. Also, the peak power gain cut-off frequencies of two structures are compared. According to these comparisons by simulation studies, the proposed double QW HEMT is more electrically efficient than the conventional single QW HEMT. Therefore, this present work may be a suitable prediction for the experimental fabrication of proposed double QW HEMT in future. This work may be suitable in sensor related applications and high frequency applications.

To keep up with the dominance in the field of leading semiconductor technology innovation, TSMC has announced the risk production of its most advanced 5nm CMOS logic node [1] using the full-fledged EUV and high mobility channel (HMC) FinFETs. Supporting the state of the art mobile SOC chips and HPC application needs, this 5nm technology node provides ~1.8x improvement in logic density, 15% speed gain and 30% power reduction as compared to its previous 7nm generation [1] - [2] . This paper, for the first time, brings out the detailed reliability attributes for the TSMC 5nm technology node from the device to various chip/package level reliability testing. While delivering an enhanced performance for N5, here we demonstrate the reliability benefit in terms of Bias Temperature Instability (BTI), Hot Carrier Degradation (HCD), Time dependent dielectric breakdown (TDDB) degradation modes in device level. Not only that, N5 node also delivers excellent reliability margins in chip level evaluations for SRAM and logic CPU/GPU applications. Moreover, to compete with the strictest industry reliability requirements even to the DPPM or low DPPB levels, N5 logic confirms its benefit for the automotive applications.

In this work, we have optimized the device structure to achieve a maximum drain current of Nanoelectronic AlGaN/GaN single-heterojunction high electron mobility transistors (HEMTs) by the variations of mole fraction, doping concentration and gate length, using the SILVACO-ATLAS software tool. The drain current increases at higher aluminium mole fraction of AlGaN nano-layer. The drain current increases at higher doping concentration of AlGaN nano-layer. The drain current reduces at higher gate length of HEMTs. The conduction band engineering in terms of quantum wells is investigated in detail by involving the Bose-Einstein expression. The simulation results of this work are supported by the available previous experimental results and analytical modelling. This work will be useful to fabricate the AlGaN/GaN HEMTs experimentally for bioengineering applications.

A comprehensive nonparametric statistical learning framework, called LPiTrack, is introduced for large-scale eye-movement pattern discovery. The foundation of our data-compression scheme is based on a new Karhunen–Loeve-type representation of the stochastic process in Hilbert space by specially designed orthonormal polynomial expansions. We apply this novel nonlinear transformation-based statistical data-processing algorithm to extract temporal-spatial-static characteristics from eye-movement trajectory data in an automated, robust way for biometric authentication. This is a significant step towards designing a next-generation gaze-based biometric identification system. We elucidate the essential components of our algorithm through data from the second Eye Movements Verification and Identification Competition, organized as a part of the 2014 International Joint Conference on Biometrics.

Developing algorithmic solutions to tackle the rapidly increasing variety of data types, by now, is recognized as an outstanding open problem of modern statistics and data science. But why does this issue remain difficult to solve programmatically? Is it merely a passing trend, or does it have the potential to radically change the way we build learning algorithms? Discussing these questions without falling victim to the big data hype is not an easy task. Nonetheless, an attempt will be made to better understand the core statistical issues, in a manner to which every data scientist can relate.

The two key issues of modern Bayesian statistics are: (i) establishing principled approach for distilling statistical prior that is consistent with the given data from an initial believable scientific prior; and (ii) development of a consolidated Bayes-frequentist data analysis workflow that is more effective than either of the two separately. In this paper, we propose the idea of “Bayes via goodness-of-fit” as a framework for exploring these fundamental questions, in a way that is general enough to embrace almost all of the familiar probability models. Several examples, spanning application areas such as clinical trials, metrology, insurance, medicine, and ecology show the unique benefit of this new point of view as a practical data science tool.

Consider a big data multiple testing task, where, due to storage and computational bottlenecks, one is given a very large collection of p-values by splitting into manageable chunks and distributing over thousands of computer nodes. This paper is concerned with the following question: How can we find the full data multiple testing solution by operating completely independently on individual machines in parallel, without any data exchange between nodes? This version of the problem tends naturally to arise in a wide range of data-intensive science and industry applications whose methodological solution has not appeared in the literature to date; therefore, we feel it is necessary to undertake such analysis. Based on the nonparametric functional statistical viewpoint of large-scale inference, started in Mukhopadhyay (2016), this paper furnishes a new computing model that brings unexpected simplicity to the design of the algorithm which might otherwise seem daunting using classical approach and notations., Comment: Revised version

A comprehensive modeling framework involving mutually uncorrelated contribution from interface trap generation and hole trapping in pre-existing, process related gate insulator traps is used to study NBTI degradation in SiON and HKMG p-MOSFETs. The model can predict time evolution of degradation during DC and AC stress, time evolution of recovery after stress, impact of stress and recovery bias and temperature, and impact of several AC stress parameters such as pulse frequency, duty cycle, duration of last pulse cycle (half or full) and pulse low bias. The model can successfully explain experimental data measured using fast and ultra-fast methods in SiON and HKMG devices having different gate insulator processes. The trap generation and trapping sub components of the composite model have been verified by independent experiments. Data published by different groups are reconciled and explained. The model can successfully predict long time DC and AC stress data and has been used to determine device degradation at end of life as EOT is scaled for different HKMG devices. (C) 2014 Elsevier Ltd. All rights reserved.

SiGe and Ge pMOSFETs, with channel passivation by Si cap and standard SiO2/HfO2 gate stack, show a very strong oxide electric field dependence of NBTI, beneficial for low voltage operation. However, standard NBTI extrapolation based on voltage accelerated stress tests is complicated for these devices due to an apparent correlation of time-dependence exponent (n) to the applied gate stress overdrive voltage (VOV). This behavior is found to be unrelated to the measurement delay, but induced by a gradual reduction of the stress oxide electric field during the NBTI stress due to the buildup of threshold voltage shift. A unique analog circuit based test setup is proposed to perform a quasi-constant oxide field BTI stress. This method eliminates the field reduction effect during NBTI stress and therefore decouples the time exponent from the applied stress VOV. This allows to calculate the time-to-failure for SiGe and Ge channel devices unambiguously, confirming the superior NBTI reliability of these pMOS technologies as compared to standard Si devices. Possible limitations of the proposed measurement method are also discussed.

We report a broad study of Negative Bias Temperature Instability (NBTI) in Replacement Metal Gate (RMG) SiGe core FinFETs, focusing on the impact of Ge concentration, fin width, fin side-wall orientation, and interface passivation by high pressure anneals (HPA). We focus on Si-cap-free gate stacks, which offer simplified FinFET integration. Direct oxidation of SiGe yields poor interface quality, which can be restored by HPA. Despite a wide distribution of defect levels in the interfacial layer due to Ge suboxide formation, SiGe reliability still benefits from a reduced bulk oxide trapping thanks to favorable energy decoupling of channel carriers to dielectric defect levels. Reduced NBTI is observed in narrow fins, thanks to a reduced oxide electric field. Fin rotation does not improve NBTI in SiGe fins, while some improvement, particularly of the near-interface degradation, was obtained by HPA. Our results show that Si-cap-free RMG SiGe gate stacks with properly optimized HPA can offer a simplified FinFET integration, with a limited reliability penalty compared to best-in-class Si-passivated SiGe devices.

In kernel discriminant analysis, it is common practice to select the smoothing parameter (bandwidth) based on the training data and use it for classifying all unlabeled observations. But this method of selecting a single scale of smoothing ignores the major issue of model uncertainty. Moreover, in addition to depending on the training sample, a good choice of bandwidth may also depend on the observation to be classified, and a fixed level of smoothing may not work well in all parts of the measurement space. So, instead of using a single smoothing parameter, it may be more useful in practice to study classification results for multiple scales of smoothing and judiciously aggregate them to arrive at the final decision. This paper adopts a Bayesian approach to carry out one such multiscale analysis using a probabilistic framework. This framework also helps us to extend our multiscale method for semi-supervised classification, where, in addition to the training sample, one uses unlabeled test set observations to form the decision rule. Some well-known benchmark data sets are analyzed to show the utility of these proposed methods.

Dramatic increases in the size and complexity of modern datasets have made traditional "centralized" statistical inference prohibitive. In addition to computational challenges associated with big data learning, the presence of numerous data types (e.g. discrete, continuous, categorical, etc.) makes automation and scalability difficult. A question of immediate concern is how to design a data-intensive statistical inference architecture without changing the basic statistical modeling principles developed for "small" data over the last century. To address this problem, we present MetaLP, a flexible, distributed statistical modeling framework., The purpose of this paper is to answer the question: What is the relevance of small-data-ideas in this big-data world? The bigger question is: Should we make difficult things easy or easy things look difficult? The first option will probably make some impact in the long-run, but the second one will surely earn prestigious journal publications in short-run, IEEE Transactions on Big Data (forthcoming). The first report came out in 2015

In this chapter, the basic experimental signatures of NBTI and PBTI degradation respectively in p- and n-channel MOSFETs are discussed. Historical results from published reports are briefly reviewed for SiON and HKMG MOSFETs. Results obtained using ultra-fast characterization methods are shown for DC and AC BTI degradation in state-of-the-art SiON and HKMG MOSFETs. The impact of gate insulator processes on magnitude of NBTI degradation and its time, bias and temperature dependence is discussed for SiON p-MOSFETs. Time evolution of NBTI and PBTI degradation during and after DC stress and during AC stress is shown for HKMG MOSFETs, and the impact of stress bias and temperature, as well as that of AC pulse duty cycle and frequency are discussed. Impact of basic HKMG process variations, such as Nitrogen incorporation and interlayer thickness scaling are also discussed. Similarities and differences between NBTI and PBTI results are highlighted.

In this chapter, direct characterization techniques have been used to access the trap generation and trapping subcomponents of BTI degradation in HKMG MOSFETs having different gate stack processes. Generation of new traps is estimated using DCIV for NBTI stress and both DCIV and SILC for PBTI stress respectively in p- and n-channel MOSFETs. Flicker noise is used to estimate the density of process related pre-existing gate insulator traps responsible for hole and electron trapping respectively during NBTI and PBTI stress. The spatial and energetic locations of generated traps for NBTI and PBTI stress are identified. The time, bias, and temperature dependencies of trap generation obtained using the DCIV technique are compared between NBTI and PBTI stress, while these parameters obtained using DCIV and SILC techniques are compared for PBTI stress. The relative dominance of trap generation and trapping on NBTI and PBTI threshold voltage degradation is estimated for different gate insulator processes.

This chapter proposes compact models to predict NBTI and PBTI degradation in p- and n-channel MOSFETs, respectively. Models are based on the physics of BTI degradation discussed in Chap. 3. Compact NBTI model has been verified against measurements in different SiON and HKMG gate insulator process-based planar Si devices, planar HKMG devices having SiGe channel without and with Si cap, and Si channel based HKMG FinFETs. The model can predict degradation in such wide variety of devices with a maximum of five, but in most cases just three, device dependent adjustable parameters. PBTI compact model has been verified to predict degradation in different HKMG gate insulator process-based planar Si devices with six device dependent parameters. Models for both NBTI and PBTI have three underlying subcomponents related to interface and bulk trap generation and charge trapping, overall degradation being the uncorrelated sum of these subcomponents. All subcomponents are independently verified using different measurement techniques, such as CP, DCIV, SILC, and flicker noise, discussed in Chap. 2.

In this chapter, different characterization methods are discussed to determine BTI degradation of MOSFET parameters and to directly estimate the pre-existing and generated gate insulator defects responsible for BTI. V T shift is obtained from full I D–V G sweeps and also from spot I D measurements at fixed V G; one spot measurements are performed either on-the-fly at stress V G or by dropping down to a lower V G from stress. Impact of measurement delay and mobility degradation on V T extracted from different methods is discussed. Flicker noise method is used to access the density of pre-existing defects for different gate insulator processes. Gated diode or DCIV, charge pumping (CP) and low voltage SILC methods are used to determine trap generation at or near the interface between Si channel and gate insulator. Conventional SILC is used to estimate generation of bulk gate insulator defects. Different artifacts related to improper choice of stress bias and measurement delay are discussed.

We perform a comparative study of Negative Bias Temperature Instability (NBTI) reliability on compressively strained Germanium (s-Ge) Quantum Well (QW) Planar and FinFET p-type devices. We see electron trapping from the gate electrode in all these devices with applied negative stress. FinFETs show less ΔV T than Planar but with 1.8 times higher stress time exponent (n) and slower recovery rate than Planar. Also, Δg m /g m0 of FinFETs improves with increasing stress.

The impact of gate insulator processes to achieve deeply scaled interlayer (IL)/high-k (HK) bilayer stacks for sub-20-nm CMOS on negative-bias temperature instability and positive-bias temperature instability is studied. IL scaling is done by novel low-thermal-budget rapid-thermal-process-based ultrathin IL and monolayer IL. Innovative IL top surface treatment enables integration of IL and atomic-layer-deposition-based hafnium oxide HK without vacuum break. Fully integrated stacks show scaling of equivalent oxide thickness down to similar to 6 angstrom, with excellent gate leakage, mobility, and world-class BTI. The mechanism responsible for improved BTI is discussed.

The nano-film of diamond-like carbon (DLC) is coated on the inner walls of microfluidic laboratory-on-a-chip devices as microchannel bends fabricated by microelectronic processes. Maskless lithography and hot embossing lithography techniques are used to fabricate these micron-scale devices. The microfluidic flow of water is controlled by the level of surface wettability of DLC coating inside the microchannel bends. These microchannel bends are structurally modified to separate polystyrene microparticles successfully from test suspension with 100% separation efficiency. These microchannel bends are useful to separate red blood cells (RBCs) and white blood cells (WBCs) from human blood for further clinical tests.

DC and AC NBTI in deep EOT scaled HKMG p-MOSFETs with different IL (scaled to sub 2A) are measured by UF-MSM method with 10μs delay. A model with interface trap generation (ΔV IT-IL ) at Si/IL interface, hole trapping (ΔV HT ) in IL bulk and trap generation (ΔV IT-HK ) linked to H passivated Oxygen vacancy (Ov-H) defects in IL/HK interfacial transition layer has been proposed. The existence of Ov defects and their energy levels are verified using DFT simulation. The model can successfully predict V T shift (ΔV T ) during and after DC stress, dependence on pulse duty cycle (PDC) and frequency (f) for AC stress, and gate insulator process dependence with consistent set of parameters. Impact of EOT scaling on DC and AC NBTI is studied, and end-of-life degradation has been estimated.

Process impact of negative bias temperature instability (NBTI) is studied in silicon oxynitride (SiON) and high- k metal gate (HKMG) p-MOSFETs. An analytical compact model is used to predict long time degradation. NBTI is shown to be governed by the generation of interface and bulk oxide traps and hole trapping in preexisting traps that are mutually uncorrelated. Experimental evidences are provided to independently verify underlying components. Model parameters are extracted; only a few process-dependent parameters are needed to predict the experimental data from wide range of SiON and HKMG p-MOSFETs at various stress bias and temperature. Similarity between SiON and HKMG devices is highlighted.

A comprehensive NBTI framework using the H/H2 RD model for interface traps and 2 well model for hole traps has been proposed and used to predict DC and AC experiments. The framework is validated against experimental data from different DC stress and recovery conditions, AC frequency and duty cycle, measurement speed, and across SiON and HKMG devices having different gate insulator processes. Limitations of the alternative 2 stage model framework is discussed.

NBTI and PBTI are studied in IL/HK/MG gate stacks having EOT down to ~ 6A and fabricated using low T RTP based thermal IL and a novel IL/HK integration. At equivalent EOT, proposed stacks provide improved NBTI and similar PBTI when compared to conventional Chem-Ox IL based HKMG stacks. EOT scaling achieved by RTP thermal IL scaling shows lower rate of increase in NBTI and PBTI when compared to Chem-Ox IL scavenged stacks. Impact of Nitrogen and role of post HK nitridation are studied. Physical mechanism of improved BTI in proposed stacks is discussed in detail.

World class EOT scaling and reliability performance has been achieved by integration (no air-break) of thermal interface layer (IL) and ALD high-k. RTP process is used for the formation of Ultra-Thin IL (UT-IL) and Mono-Layer IL (ML-IL). While integrated with ALD HfOx process, the resultant dielectric stack can reach 6A EOT with excellent gate leakage, mobility and BTI reliability performances. The experiment also demonstrates that integrated thermal IL/HfOx stack provides lower pre-existing trap density and lower trap generation during BTI when compared to conventional chemical oxide IL/air-beak/HfOx stack.

Polymethylmethacrylate (PMMA) microfluidic devices have been fabricated using a hot embossing technique to incorporate micro-pillar features on the bottom wall of the device which when combined with either a plasma treatment or the coating of a diamond-like carbon (DLC) film presents a range of surface modification profiles. Experimental results presented in detail the surface modifications in the form of distinct changes in the static water contact angle across a range from 44.3 to 81.2 when compared to pristine PMMA surfaces. Additionally, capillary flow of water (dyed to aid visualization) through the microfluidic devices was recorded and analyzed to provide comparison data between filling time of a microfluidic chamber and surface modification characteristics, including the effects of surface energy and surface roughness on the microfluidic flow. We have experimentally demonstrated that fluid flow and thus filling time for the microfluidic device was significantly faster for the device with surface modifications that resulted in a lower static contact angle, and also that the incorporation of micro-pillars into a fluidic device increases the filling time when compared to comparative devices.

Modern data mining and bioinformatics have presented an important playground for statistical learning techniques, where the number of input variables is possibly much larger than the sample size of the training data. In supervised learning, logistic regression or probit regression can be used to model a binary output and form perceptron classification rules based on Bayesian inference. In these cases , there is a lot of interest in searching for sparse model in High Dimensional regression(/classification) setup. we first discuss two common challenges for analyzing high dimensional data. The first one is the curse of dimensionality. The complexity of many existing algorithms scale exponentially with the dimensionality of the space and by virtue of that algorithms soon become computationally intractable and therefore inapplicable in many real applications. secondly, multicollinearities among the predictors which severely slowdown the algorithm. In order to make Bayesian analysis operational in high dimensio...