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The boundary-scan test technology can be used for the test of complex circuits. Before the test, the integrity of the boundary-scan structure needs to be tested. Through the study of the boundary scan structure, this paper designs the upper computer software, tests the boundary-scan structure, and successfully checks the condition of the boundary scan link.

The high power consumption during circuit test process can produce unwanted failures or take effects on circuit reliability, therefore the reduction of both peak power and average power of circuit test is necessary. A test pattern generation approach is presented in this paper for the delay faults in digital circuits, the approach makes use of the evolution method with the hybrid strategies to produce the test vectors with low power consumption. First of all, a pair of vectors that may detect a delay fault is coded as an individual. A lot of individuals constitute the populations. Secondly, the test vectors with low power are produced by the evolution of these populations. Many new individuals are randomly produced and are added into every evolution step, and the mutation mode of individuals is related to other individuals in the current population. A lot of experimental results show that the test vectors with low power for the delay faults in digital circuits can be produced by the approach proposed in this paper, and the approach can get the large reduction of power consumption when compared with random test generation algorithm.

The VLSI technology has led to the increased complexity in hardward design, therefore the verification for the correctness of circuit operations has become an exrtremely important task. The verification procedure can be reduced by means of the equivalent signal lines in the circuits. In this paper, a new method is presented for determining the equivalent signal lines, the method utilizes the weight value assignment of signal lines in circuits. First of all, the method makes use of the topological information of circuits to perform forward weight value assignments, assign weight values to the signal lines from the primary inputs to primary outputs. Afterwards, carry out the backward weight value assignment, assign weight values to the signal lines from the primary outputs to primary inputs. Secondly, carry out the random pattern simulation to further check the equivalence of signal lines. A lot of experimental results show that the verification of digital circuits can be carried out effectively by using the method proposed in this paper, the time being needed for the verification procedure can be cut down by utilizing the equivalent signal lines.

The failure analysis of semiconductor apparatus is very needed for ensuring product quality, which can find several types of defects in the semiconductor apparatus. A new testing method for the defects in Si semiconductor apparatus is presented in this paper, the method makes use of photon emissions to find out the failure positions or failure components by taking advantage of the infrared photo emission characteristics of semiconductor apparatus. These emitted photons carry the information of the apparatus structure. If there are defects in the apparatus, these photons can help in understanding the apparatus properties and detecting the defects. An algorithm for the generation of circuit input vectors are presented in this paper to enhance the strength of the emitted photons for the given components in the semiconductor apparatus. The multiple-valued logic, the static timing analysis and path sensitizations, are used in the algorithm. A lot of experimental results for the Si semiconductor apparatus show that many types of defects such as contact spiking and latchup failure etc., can be detected accurately by the method proposed in this paper.

With the complexity of integrated circuits is continually increasing, a local defect in circuits may cause multiple faults. The behavior of a digital circuit with a multiple fault may significantly differ from that of a single fault. A new method for the detection of multiple faults in digital circuits is presented in this paper, the method is based on binary decision diagram (BDD). First of all, the BDDs for the normal circuit and faulty circuit are built respectively. Secondly, a test BDD is obtained by the XOR operation of the BDDs corresponds to normal circuit and faulty circuit. In the test BDD, each input assignment that leads to the leaf node labeled 1 is a test vector of multiple faults. Therefore, the test set of multiple faults is generated by searching for the type of input assignments in the test BDD. Experimental results on some digital circuits show the feasibility of the approach presented in this paper.

The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits with n primary inputs is not more than n+1, for linear tree circuits is two, and for multiplication modulo circuits is two if n is an odd number or if n is an even number and m>3, where the optimal test set of a circuit has minimal number of test vectors. Secondly, it is indicated that the cardinality of optimal multiple fault test set for linear tree circuits with n primary inputs is 1+[n/(m−1)], for multiplication modulo circuits is n+1, for fanout-free circuits that consist of 2-input linear tree circuits and 2-input multiplication modulo circuits is not greater than n+1, where [x] denotes the smallest integer greater than or equal to x. Finally, the single fault location approaches of linear tree circuits and multiplication modulo circuits are presented, and all faults in the two types of circuits can be located by using a test set with n+1 vectors.

A new approach for detecting multiple faults in digital circuits is presented in this paper, which uses neural network technique to generate the test vectors and to diagnose the multiple faults. First of all, the optimal neural network model corresponding to an arbitrary digital circuit is used. For a logic circuit with m inputs and n outputs, the optimal neural networks having m+n neurons can represent the logic function of the circuit. Secondly, the test vectors of multiple faults in the circuit are obtained by using evolutionary strategies to compute the minimum energy states of the optimal neural network. Thirdly, the multi-layer feed forward network and back propagation algorithm are used to diagnose the multiple faults in the circuit. The design of both network configurations and samples patterns are given in detail. Experimental results show that the approaches proposed in this paper are effective for detecting and diagnosing multiple faults in digital circuits.

A new approach to generate test sets for multiple faults of digital circuits is presented in the paper, which employs neural networks and simulated annealing technique. The neural network models for circuit are built, the test vectors of multiple faults in the circuit can be produced by computing the minimum energy states of the neural networks. An algorithm based on simulated annealing is proposed to compute the minimum states of energy functions, the algorithm has global convergence and has polynomial complexity under a decrement scheme of temperature. Experimental results shows that it is possible to obtain high fault coverage for testable multiple faults with the proposed approach without fault simulation.