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Cryptography systems have become inseparable parts of almost every communication device. Among cryptography algorithms, public-key cryptography, and in particular elliptic curve cryptography (ECC), has become the most dominant protocol at this time. In ECC systems, polynomial multiplication is considered to be the most slow and area consuming operation. This article proposes a novel hardware architecture for efficient field-programmable gate array (FPGA) implementation of Finite-field multipliers for ECC. Proposed hardware was implemented on different FPGA devices for various operand sizes, and performance parameters were determined. Comparing to state-of-the-art works, the proposed method resulted in a lower combinational delay and area–delay product indicating the efficiency of design.

The generation of precise linear frequency modulation is a critical requirement for millimeterwave automotive radars. This paper presents the analysis and design of a CMOS 75.5 - 82.5 GHz monotonically linear digitally controlled oscillator (ML-DCO) fulfilling the requirements of the 77 GHz automotive radar. Non-linear large varactors are avoided. Linear coarse, intermediate, and fine-tuning ranges are achieved by arranging the available minimum Metal-Oxide-Metal (MoM) capacitor in unique configurations. Moreover, a new tuning mechanism derived from a Colpitts topology is discussed to meet the wide tuning requirements without losing linearity. The new arrangement results in a minimal amplitude variation while the ML-DCO is tuned. The coarse, intermediate, and fine-tuning steps from the post-layout simulation are 0.22, 10, and 346 KHz, respectively. The power consumption is 14 mW from a 1.2 V supply. The achieved phase-noise is -98.53 dBc/Hz at a 1 MHz offset when oscillating at 77 GHz. The ML-DCO demonstrates -185 Figure of Merit and -184 Figure of Merit for Tuning.

Mathematical modifications have been made to the Izhikevich Neuron Model to allow for a simple, low-area digital hardware implementation with low computational intensity. The implemented neuron circuit only requires one input parameter to replicate all of the cortical neuron behaviours described by Izhikevich. The low hardware requirements of this neuron implementation make large, highly parallel digital spiking neural networks of this neuron feasible. Additionally, the model requires fewer external parameter changes to exhibit diverse neuron behaviours. The alterations made to create this novel model are presented in detail with a performance comparison to the original Izhikevich Neuron. Subsequently a digital hardware realization is presented and its performance is characterized.

This study proposes a novel negative level shifter capable of converting low levels of input voltages to high output voltages while maintaining high speed and low delay and superior static power dissipation. The proposed level shifter is composed of a combination of cross-coupled and current mirror configurations. The minimal operating voltage of the proposed level shifter is 400 mV . In addition to the operating range, the power consumption and delay of the proposed level shifter were designed for low-power applications. Under VDDL= 0.4 V , VDDH= 1.8 V and f in = 1 MHz condition, the average power, energy/transition and static power were 2.6 μ W , 26 fJ / Transition , and 70 pW , respectively.

With advances in low power and battery-operated devices, concerns over power-efficient designs for system-on-chip devices is growing. Since some subsystems require to have both positive and negative voltage rails, it is essential to ensure this requirement is satisfied without increasing the cost and power consumption. This paper presents a novel Negative Level Shifter used to generate negative voltage levels from the positive DC power supply line. Additionally, an improved CMOS Voltage Reference generator based on a Resistorless Beta Multiplier is also proposed. The two circuits were tested under various conditions, and results validate the low-power operation of the proposed design. The proposed Negative Level Shifter required only 772 pW and has a delay equal to 4ns with a supply voltage of 0.3V. When assembled, both the reference voltage and the level shifter consume 8.5 nW with the supply voltage of 1V at room temperature.

In this paper, the design and implementation of a low-power, high-resolution, fully differential readout architecture for capacitive sensing applications is presented. The proposed sensing mechanism is based on the gain variations of two capacitively coupled operational transconductance amplifiers (OTAs). The target analyte acts as the dielectric of a sensing electrode, and its detection results in capacitance variations. These capacitance variations are translated to voltage, and the result is amplified to be used as a biomarker detector. With high-gain OTAs and a high-gain difference amplifier, the proposed mechanism achieves a high-resolution of 1 aF , with a sensitivity of 290 mV / fF . The proposed structure exhibits such a high-resolution while maintains an extremely low-power consumption of 6.6 μ W . Using perfectly matched elements with accurate layout, this structure is able to reduce the mismatch-based errors to less than 0.05 % . An 8-bit control word adjusts the sensitivity and the detection range of the proposed structure which results in a wide dynamic range of 100 dB . The main features of the proposed structure such as high-resolution, high-sensitivity, low-power consumption, selective capacitance detection range and adaptive sensitivity, make this readout mechanism an ideal solution for sensitive, low-power, and accurate life science biosensors.

This paper presents a 77 GHz CMOS Monotonically Linear Digitally Controlled Oscillator (ML-DCO) that is derived from a Colpitts topology. A new tuning mechanism is developed that alleviates the need for an ideal switch and assures linearity. Large nonlinear varactors are avoided, and the ML-DCO achieves 5GHz linear tuning range that fulfills the requirements for short range and long range automotive radar sensors. Oscillating at 77GHz, the ML-DCO consumes a maximum of 9.12 mW and achieves a phase-noise of $-98.53 dBc/Hz$ at a 1MHz offset frequency. The ML-DCO demonstrates $-1\mathrm{S}6$ Figure of Merit and -182 Figure of Merit for Tuning.

Optical Character Recognition system (OCR) can be used in intelligent transportation systems for license plate detection. However, most times the systems are unable to work with noisy and imperfect images. In this work, a robust FPGA-based OCR system has been designed and tested with imperfect and noisy license plate images. The OCR system is based on a feedforward neural networks, which uses an efficient and precise neuron. The neuron transfer function is based on an approximation of the Hyperbolic Tangent Activation Function. The neuron is utilized in a 189 − 160 − 36 feed forward neural network configuration. The network parameters were optimized and then tested with noisy images of license plates numbers. The network was able to maintain a 98.2% accuracy in recognizing the characters despite the image imperfections.

This paper presents a 24 GHz CMOS Colpitts-Clapp Digitally Controlled Oscillator (CC-DCO) with an automatic amplitude stabilization to improves the Phase Noise (PN) performance. Amplitude stability is favorable to suppress the amplitude-to-phase conversion. The DCO is implemented in 65 nm TSMC CMOS process. The Tuning Rang (TR) is from 22 GHz to 29 GHz that is required for a 24 GHz Short Range Radar (SRR). The CC-DCO consumes a maximum of 19 mW. Oscillating at 24 GHz, the PN of −104 dBc=Hz at 1MHz offset frequency is achieved. The amplitude of oscillation varies by 4.56% across 29% TR.

An area and power-efficient modular mixed-signal synapse architecture is proposed for VLSI implementation of the multi-layer feed-forward neural network. The proposed circuitry multiplies synaptic weights that are stored in digital registers with the analog input. The multiplication result is always an analog current. Despite conventional MDACs principle in which all the multiplication work is performed based on weighted current mirrors, our structure performs the multiplication partially by small-area gates. This approach decreases the need for weighted current mirrors and lowers the size of transistors significantly. Modularity feature of the proposed circuit in combination with the scalable S-shaped neuron makes the structure capable of being easily adapted for various network configurations. This feature and the area-efficient multiplier design make the circuit an excellent choice to be used in large size multi-layer neural networks. The circuit is implemented in TSMC CMOS 0.18μm. The power at the maximum input level is 244um2. The area is 0.23mW with the measured output current error of less than 0.5μA.

Astrocyte as one of the brain cells controls synaptic activity between neurons by providing feedback to neurons. A novel digital hardware is proposed for neuron-synapse-astrocyte network based on the biological Adaptive Exponential (AdEx) neuron and Postnov astrocyte cell model. The network can be used for implementation of large scale spiking neural networks. Synthesis of the designed circuits shows that the designed astrocyte circuit is able to imitate its biological model and regulate the synapse transmission, successfully. In addition, synthesis results confirms that the proposed design uses less than 1% of available resources of a VIRTEX II FPGA which saves up to 4.4% of FPGA resources in comparison to other designs.

This paper presents a CMOS 24GHz Clapp-Colpitts Digitally Controlled Oscillator (CC-DCO) with 22GHz–29GHz tuning range that is able to address Short Range Radar (SRR) requirements. In order to overcome the major challenge to design a wide tuning range DCO, proper oscillator topology is chosen, specific tuning mechanism is implemented, and design optimization strategies are employed without degrading the Phase Noise (PN) performance. The CC-DCO is implemented with 65nm CMOS process. A wide tuning range of 29% and a fine tuning step of 1.6 MHz are achieved simultaneously. The CC-DCO consumes 10mA from a 1V supply. It shows a PN of −187dBc/Hz at 1 MHz offset frequency, and achieves −268dBc/Hz figure of merit considering the tuning range.

Multi-valued dynamic memories are appropriate for applications such as implementation of neural networks, where massive number of synaptic weights have to be stored on a chip. In this paper, a novel storage and refreshing configuration to store up to 4 bits (16 levels) per cell on a dynamic memory is proposed. This configuration is based on the Continuous Valued Number System (CVNS). Error correction method according to the CVNS properties is used in order to increase the noise margin of memory cells. Furthermore, by decreasing the leakage current, the refresh cycle time is increased. The circuits are designed, simulated, and finally laid out using 90-nm CMOS technology.

Resistive-type distributed neural networks (DNNs) provide a self-scaling structure for the neuron, which can spontaneously adapt itself to different numbers of inputs. In lumped neural networks, the neuron should be changed whenever the number of inputs changes due to the applications; redesigning the neuron is not practical, particularly for hardware implementations. In this brief, a group of feedforward DNNs based on a continuous valued number system is proposed, which outperforms not only the lumped neural networks but also the conventional DNNs because of the reduced sensitivity to noise.

A new time-multiplexed architecture is proposed for mixed-signal neural networks. MRIII is used for training the network which is more robust for implementing mixed-signal designs. The problem of node addressing and routing for implementing the MRIII is solved by performing the operations in current mode and using a counter. Arrays of mixed-signal multiplying-digital-to-analog (MDAC) blocks are used for synaptic multiplication. A compact architecture with a more linear transfer function is proposed for the MDAC to reduce the area, power consumption and noise. The proposed network is implemented using TSMC CMOS 0.18 μ technology. The results of an XOR (2-2-1) network are presented to show the generality of the design.

This paper explores a mixed-signal method for designing a crypto processor component, the adder, which allows it to produce minimal side channel information, rendering it less vulnerable in terms of hardware. The adder is implemented in TSMC CMOS 90nm technology. The results show that it is possible to maintain a competitively low power consumption, as compared to conventional architectures, all while providing a method to greatly improve data security systems.

Side channels attacks are considered among physical, noninvasive methods employed to obtain private key of cryptographic devices such as smart cards. In this paper, a new approach for countermeasure against Differential Power Analysis (DPA) with an extremely low-area and -power overhead is proposed. The proposed method employs a Phase Locked Loop (PLL) which is placed in the power path of an Advanced Encryption Standard (AES) based encryption system. This method suppresses the power characteristic of the encryption system through both masking and hiding the private key information. Moreover, the proposed method is successful in maintaining high frequency operation of the encryption engine. The proposed method is implemented in TSMC CMOS 65nm technology. The protection circuit has only 5% area overhead, and 6% increase in power consumption, with frequency degradation of only 1%.

In this paper design and implementation of a modular mixed-signal feed-forward neural network is presented. The network is implemented based on the Continuous Valued Number System (CVNS) arithmetic with neurons distributed in the network. Synapse weights are implemented on the chip using capacitive analog memories. Weight values are stored as the CVNS values and are refreshed and updated using the overlap between the CVNS digits. Current-mode logic is used for implementation in order to simplify the circuit design, and especially addition, which resulted in reduced power and area consumption. The distributed nature of the neurons allows for expansion of the network into larger networks. Individual modular layers are fabricated in TSMC CMOS 180nm, and are used to form different network sizes. The module is used to configure two proof of concept examples, a 2 - 2 - 1 and a 3 - 2 - 1 network to solve the XOR problem. Results of test and verification presented in this paper show the network flexibility of the proposed design to form various network configurations.

This paper presents a study of temperature and process sensitivity in CMOS Colpitts oscillator. Based on the analysis of linear and non-linear models, temperature and process sensitivity is derived. The design for temperature compensation and process independent oscillator is based on a clear design methodology, and by taking into consideration all of the parameters that contribute to the deviation of the frequency of oscillation from its nominal value. Using the proposed design methodology, the number of digits required for temperature and process compensation can be estimated early in the design process. Moreover, identifying elements that cause the deviation, allows the designer to develop the required compensation method. Using the proposed design methodology, frequency tuning requirements are derived under restriction of the start-up condition. By defining the process and temperature sensitivity parameters early in the design process, unnecessary design iteration is prevented and time-to-market is reduced.

A temperature and supply independent on-chip reference relaxation oscillator for low voltage design is described. The frequency of oscillation is mainly a function of a PVT robust biasing current. The comparator for the relaxation oscillator is replaced with a high speed common-source stage to eliminate the temperature dependency of the comparator delay. The current sources and voltages are biased by a PVT robust references derived from a bandgap circuitry. This oscillator is designed in TSMC 65nm CMOS process to operate with a minimum supply voltage of 1.4V and consumes 100μW at 157MHz frequency of oscillation. The oscillator exhibits frequency variation of 1.6% for supply changes from 1.4V to 1.9V, and ±1.2% for temperature changes from 20°C to 120°C.

Area and Noise to Signal Ratio (NSR) are two main factors in hardware implementation of neural networks. Despite attempts to reduce the area of sigmoid and hyperbolic tangent activation functions, they cannot achieve the efficiency of threshold activation function. A new NSR efficient architecture for threshold networks is proposed in this paper. The proposed architecture uses different number of bits for weight storage in different layers. The optimum number of bits for each layer is found based on the mathematical derivation using stochastic model. Network training is done using the recently introduced learning algorithm called Extreme Learning Machine (ELM). A 4-7-4 network is considered as a case study and its hardware implementation for different weight accuracies is investigated. The proposed design is more efficient considering area × NSR as a performance metric. VLSI implementation of the proposed architecture using a 0.18 µm CMOS process is presented which shows 44.16%, 58.04 % and 67.30% improvement for total number of bits equal to 16, 20 and 24.

In this paper a new expandable current-mode Analog to Digital Conversion method is proposed for multiple-valued neural networks. The proposed method employs a semi-parallel architecture of current comparators to reduce the conversion time. A feedback path is used to regulate the outputs of the comparators and prevent the possible errors in the reference currents to propagate to the outputs. The circuits for a sample 4-bit conversion are designed and simulated in CMOS 180nm technology from TSMC with a 1.8v power supply.

This paper presents the design and implementation of a multiple-valued adder, with application in smart cards and cryptographic processors. The adder is designed based on the principles of truncated Continuous Valued Number System (CVNS), in order to relax the implementation requirements of the circuit topology and designs. The CVNS adder has an almost constant power consumption, independent of the input values. This feature makes this adder immune against side channel attacks, which may use the power consumption pattern to obtain the intermediate values of arithmetic operations.

Distributed Neural Networks (DNNs) are generally providing self-scaling property together with higher noise immunity for resistive-type neural networks. Continuous Valued Number System (CVNS) is a potential candidate to build the DNNs; however, implementation of a CVNS digit in its complete form needs a high resolution environment which is not practical. Truncation methods are applied to CVNS digits to make them adaptable to the low resolution environments. However, truncated CVNS operations may decrease the accuracy and immunity to noise compared to the complete CVNS operations. In this work, a truncated CVNS DNN is proposed, and studies over Noise to Signal Ratio (NSR) and accuracy are provided. Studies show that the accuracy is acceptable, and the NSR is still less than the NSR of conventional DNNs.

A novel method for converting analog information to digital in current mode is proposed. This configuration is efficient in terms of speed and area consumption. It is designed for a 4-bit conversion in particular, although it can be easily expanded for more number of bits. For a 4-bit approach, the proposed Analog to Digital Conversion Method (ADCM) provides the conversion of each two bits at the same time resulting in a fast conversion. In addition, its specific architecture occupies a small area. The proposed ADCM is suitable for current mode applications.

Continuous Valued Number System (CVNS) representation enables us to integrate complex analog processing functions within digital signal processing units. The CVNS representation is more compatible with analog signals and system, however, it can be applies to applications where traditionally digital arithmetic has been used. The resulted systems usually have compact designs, with reduced number of interconnections, and higher speed of operation. In this paper, design of a mixed signal CVNS adder is proposed, which is used for two operand binary addition. The overall speed of the CVNS adder depends on the analog modular reduction circuits. This paper addresses the limitations in the speed of CVNS adders, and proposes a new method for eliminating this operation from the adder.

A new mixed-signal feed-forward neural network for pattern/shape recognition problems is proposed. The network has a mixed-signal structure, operations are performed in analog and weights are stored in digital. To increase the network robustness, on-chip training with Madaline Rule III is used. The proposed architecture uses time-multiplexing to increase the network density and resistive-type neurons for their self-scaling property. The results of an XOR network are presented to test the network.