Search

Your search keyword '"Mickael Petit"' showing total 10 results
Start Over Author "Mickael Petit" Topic business
10 results on '"Mickael Petit"'

1. On-line temperature measurement during power cycle of PCB-embedded diode

Author

Stéphane Lefebvre, Mickael Petit, Mounira Berkani, S. Bensebaa, Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), and École normale supérieure - Rennes (ENS Rennes)-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Université Paris-Saclay-Centre National de la Recherche Scientifique (CNRS)-Ecole Normale Supérieure Paris-Saclay (ENS Paris Saclay)-Université Gustave Eiffel-CY Cergy Paris Université (CY)

Subjects
Test bench, Materials science, business.industry, 020208 electrical & electronic engineering, Electrical engineering, 02 engineering and technology, AC power, Condensed Matter Physics, Temperature measurement, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, [SPI]Engineering Sciences [physics], 0202 electrical engineering, electronic engineering, information engineering, Power cycling, Junction temperature, Power semiconductor device, Electrical and Electronic Engineering, Safety, Risk, Reliability and Quality, business, ComputingMilieux_MISCELLANEOUS, Diode, Voltage
Abstract

This paper presents an original methodology and a test bench for active power cycling and on-line junction temperature measurement during power cycling of power devices embedded in PCB. This method is based on the use of the ratio between forward voltage and forward current variations (∆VF,∆IF) during conduction period to estimate the thermal voltage UT and thus the junction temperature in real time. The objective of this study is to estimate the junction temperature even for high frequency of power cycling tests. First, the measurement method is presented, and then the test bench is described.

Published
2021
Full Text
View/download PDF

2. Realization and characterization of instrumented power diode with aluminum RTD sensor – application to thermal impedance evaluation

Author

Laurent DUPONT, Mickael Petit, Yvan Avenas, Ibrahima KA, Electronique de Puissance et Intégration (SATIE-EPI), Composants et Systèmes pour l'Energie Electrique (CSEE), Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)-École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)-Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS), and ANR-13-PRGE-0005,MEMPHIS,Suivi de l'Etat de Santé des Composants à Semi-Conducteurs de Puissance dans les Onduleurs Photovoltaïques(2013)

Subjects
010302 applied physics, Wheatstone bridge, Materials science, business.industry, Thermal resistance, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 020208 electrical & electronic engineering, Electrical engineering, 02 engineering and technology, 01 natural sciences, 7. Clean energy, Power (physics), law.invention, Reliability (semiconductor), law, Power module, Power electronics, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Resistance thermometer, Electrical and Electronic Engineering, business, ComputingMilieux_MISCELLANEOUS, Diode
Abstract

Semiconductor devices incorporated into power electronics systems are proven to be highly sensitive to their thermal environment. Thus, temperature measurement is a key concern when it comes to reliability of power modules. Some Thermo-Sensitive Electrical Parameters (TSEPs) are used to evaluate online temperature of semiconductor components, in operating conditions of power converters. However, the accuracy and the reliability of those TSEPs are not yet fully demonstrated. To overcome this drawback, a power instrumented diode was developed with a Resistance Temperature Detector (RTD) sensor integrated on its top metal surface. This validation tool is characterized in this paper under constant power dissipation. The embedded RTD sensor is conditioned in a resistance bridge circuit. A dynamic characterization of a realistic power module is performed through thermal impedance evaluation. A comparative study is carried out to discuss the static and dynamic performances of the RTD sensor and those of ...

Published
2017
Full Text
View/download PDF

3. Study of the Impedance of the Bypassing Network of a Switching Cell – Influence of the Positioning of the Decoupling Capacitors

Author

Francois Costa, Mickael Petit, Yoann Pascal, Denis Labrousse, Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS), Electronique de Puissance et Intégration (SATIE-EPI), Composants et Systèmes pour l'Energie Electrique (CSEE), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)-École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)-Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), ANR-15-CE05-0010,HIT-TEMS,Nouvelle technologie d'intégration hybride d'un convertisseur entrelacé multiniveaux sûr et reconfigurable sous contraintes thermiques et CEM(2015), PASCAL, Yoann, and Nouvelle technologie d'intégration hybride d'un convertisseur entrelacé multiniveaux sûr et reconfigurable sous contraintes thermiques et CEM - - HIT-TEMS2015 - ANR-15-CE05-0010 - AAPG2015 - VALID

Subjects
Materials science, 02 engineering and technology, Decoupling capacitor, law.invention, decoupling, overvoltage, law, Derating, switching cell, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, switching transient, Electrical impedance, bypass, high speed switching, DC-link capacitor, business.industry, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 020208 electrical & electronic engineering, Transistor, Electrical engineering, Converters, 021001 nanoscience & nanotechnology, [SPI.TRON] Engineering Sciences [physics]/Electronics, [SPI.TRON]Engineering Sciences [physics]/Electronics, Capacitor, Overvoltage, GaN transistor, 0210 nano-technology, business, Decoupling (electronics), [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract

International audience; Mechanisms responsible for ringing and oscillations in power converters at transistors turn-offs are, first, studied using small signal modelling. It is explained why a 50 % derating must be applied to high-speed transistors. Experimental measurements validate the analytical predictions. The influence of the distance between a switching cell and its decoupling capacitors is then studied; it appears that using a low-inductance – though simple – layout results in a stray inductance as low as 11 nH when the capacitor is 30 cm away from the switching cell, enabling degrees of freedom for thermal management.

Published
2019
Full Text
View/download PDF

4. Design of a 4-phase intercell transformer converter for a space charge measuring system

Author

Ludovic Boyer, Jean-Charles Laurentie, Mickael Petit, Thierry Martire, and Mourad Jebli

Subjects
Materials science, business.industry, 020208 electrical & electronic engineering, Electrical engineering, Magnetic separation, 02 engineering and technology, Dielectric, Space charge, law.invention, Inductance, law, Power electronics, Thermal, 0202 electrical engineering, electronic engineering, information engineering, business, Transformer, Step method
Abstract

This paper presents the design of a power electronics converter to produce strong current pulses (about 400A) in the core of a HVDC cable in order to use the thermal step method to evaluate the ageing state of the dielectric component. The described converter uses a magnetic coupler with intercells transformers and is current controlled.

Published
2018
Full Text
View/download PDF

5. Decoupled PQ control Applied to a Multicellular Parallel Inverter for Grid-connected Photovoltaic System

Author

Chabakata Mahamat, Francois Costa, Cyrille Gautier, Rym Marquant, Mickael Petit, Abdelkader Mami, Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS), Laboratoire d'Application de l'Efficacité énergétique et Energies renouvelables (LAPER), Electronique de Puissance et Intégration (SATIE-EPI), Composants et Systèmes pour l'Energie Electrique (CSEE), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)-École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)-Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), Laboratoire SATIE-ENS Cachan, Lab-STA, ATTNA, and IEEE Conferences

Subjects
Engineering, decoupled, 02 engineering and technology, 7. Clean energy, Maximum power point tracking, [SPI.AUTO]Engineering Sciences [physics]/Automatic, Synchronization (alternating current), Multicellular, Control theory, 0202 electrical engineering, electronic engineering, information engineering, Grid-connected photovoltaic power system, Electronic engineering, Parallel Inverter, filter, business.industry, 020208 electrical & electronic engineering, Photovoltaic system, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 021001 nanoscience & nanotechnology, Phase-locked loop, Control system, Inverter, 0210 nano-technology, business, control, Pulse-width modulation
Abstract

International audience; – This paper presents the decoupled active and reactive power control (control), using a Phase-Locked Loop () for synchronization, and applied to the control of Multicellular Parallel Inverter (MPI) for a grid-connected Photovoltaic () system. We explain the value of this multicellular structure of inverter compared to a conventional inverter. We also present and discuss the simulation results obtained using the Matlab software (simulink and simpowersystems).

Published
2016
Full Text
View/download PDF

6. Dynamic electric model for IGBT power module based on Q3D® and Simplorer®: 3D Layout design, stray inductance estimation, experimental verifications

Author

Dominique Lhotellier, Francois Costa, Eric Laboure, Menouar Ameziani, Hocine Daou, Mickael Petit, Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM), HESAM Université - Communauté d'universités et d'établissements Hautes écoles Sorbonne Arts et métiers université (HESAM)-HESAM Université - Communauté d'universités et d'établissements Hautes écoles Sorbonne Arts et métiers université (HESAM)-Centre National de la Recherche Scientifique (CNRS), VEhicule DEcarboné et COmmuniquant et sa Mobilité (VeDeCom), Electronique de Puissance et Intégration (SATIE-EPI), Composants et Systèmes pour l'Energie Electrique (SATIE-CSEE), HESAM Université - Communauté d'universités et d'établissements Hautes écoles Sorbonne Arts et métiers université (HESAM)-HESAM Université - Communauté d'universités et d'établissements Hautes écoles Sorbonne Arts et métiers université (HESAM)-Centre National de la Recherche Scientifique (CNRS)-École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), HESAM Université - Communauté d'universités et d'établissements Hautes écoles Sorbonne Arts et métiers université (HESAM)-HESAM Université - Communauté d'universités et d'établissements Hautes écoles Sorbonne Arts et métiers université (HESAM)-Centre National de la Recherche Scientifique (CNRS)-Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), Laboratoire Génie électrique et électronique de Paris (GeePs), Université Paris-Sud - Paris 11 (UP11)-Université Pierre et Marie Curie - Paris 6 (UPMC)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Proccedings of ESARS-ITEC 2016, Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS), Composants et Systèmes pour l'Energie Electrique (CSEE), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)-École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), and Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)-Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE)

Subjects
Engineering, Layout, 02 engineering and technology, 01 natural sciences, Chopper, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Multichip modules, Parasitic extraction, Inductance, 010302 applied physics, Resistive touchscreen, business.industry, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 020208 electrical & electronic engineering, Biological system modeling, Logic gates, Insulated-gate bipolar transistor, Insulated gate bipolar transistors, Power (physics), Power module, Inverter, business, Switches
Abstract

International audience; The layout of power modules is one of the key points in power module design, especially for high power densities, where couplings are increased. Stray inductances cause various problems in switching devices and should be minimized at an early design stage to avoid later required countermeasures and redesign after the device prototype has been built. In this paper, using Ansys® Q3D® Extractor, electromagnetic simulation is carried out to extract and evaluate the inductive and resistive parasitics of one phase of a three-phase automotive inverter module with rating of 650 V-400 A. The purpose is to develop and verily the electrical model including parasitic parameters for the studied phase-leg operating as a chopper. The switching behavior of the studied structure is analyzed based on Ansys® Simplorer® simulation, and a dynamic electrical model is carried out. Experimental test measurements are performed. The comparison between the simulation models and the experimental data is reported and conclusions are made.

Published
2016
Full Text
View/download PDF

7. Comparison of modeling switching losses of an IGBT based on the datasheet and an experimentation

Author

Stéphane Lefebvre, Dominique Lhotellier, Dounia Oustad, Mickael Petit, Menouar Ameziani, Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS), VEhicule DEcarboné et COmmuniquant et sa Mobilité (VeDeCom), Electronique de Puissance et Intégration (SATIE-EPI), Composants et Systèmes pour l'Energie Electrique (CSEE), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)-École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), and Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)-Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE)

Subjects
business.product_category, Computer science, 02 engineering and technology, 01 natural sciences, Temperature measurement, 0103 physical sciences, Electric vehicle, 0202 electrical engineering, electronic engineering, information engineering, Inductance, Simulation, 010302 applied physics, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 020208 electrical & electronic engineering, Insulated-gate bipolar transistor, Switching loss, Solver, Thermal conduction, Current measurement, Insulated gate bipolar transistors, Probes, business, Switches, Datasheet, Voltage
Abstract

International audience; This paper focuses on the prediction and the study of the veracity of a losses model (both conduction and switching losses) in IGBT power modules used for electric vehicle applications. This article shows a test case based on an experimental estimation of losses with a double pulse test circuit and a circuit model based on the use of ANSYS solver Circuit - Simplorer©. This modeling is only linked to the knowledge of the IGBT characteristics obtained from datasheets. Then, it is compared with experimental measurements. The veracity of these models is evaluated, the errors are quantified and if necessary, additional characterizations that will be performed to complete the data from datasheets will be identified. An estimation of the losses with sufficient accuracy will be obtained for different switching conditions (voltage, current, temperature, gate resistance).

Published
2016
Full Text
View/download PDF

8. Study of short-circuit robustness of SiC MOSFETs, analysis of the failure modes and comparison with BJTs

Author

Denis Labrousse, Hervé Morel, Cheng Chen, Mickael Petit, Stéphane Lefebvre, Cyril Buttay, Lefebvre, Stéphane, Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS), Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Electronique de Puissance et Intégration (SATIE-EPI), Composants et Systèmes pour l'Energie Electrique (CSEE), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)-École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), and Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)-Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE)

Subjects
SiC, Materials science, [SPI] Engineering Sciences [physics], BJT, Time-dependent gate oxide breakdown, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, law.invention, MOSFET, [SPI]Engineering Sciences [physics], chemistry.chemical_compound, Robustness (computer science), law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Silicon carbide, Hardware_INTEGRATEDCIRCUITS, Electrical and Electronic Engineering, Safety, Risk, Reliability and Quality, 010302 applied physics, business.industry, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 020208 electrical & electronic engineering, Transistor, Bipolar junction transistor, Electrical engineering, short circuit, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, chemistry, Optoelectronics, business, Short circuit, AND gate, Hardware_LOGICDESIGN, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract

International audience; This paper presents experimental robustness tests made on Silicon Carbide (SiC) MOSFETs and SiC Bipolar Junction Transistors (BJTs) submitted to short-circuit operations (SC) or current limitation modes. For SiC MOSFETs, a gate leakage current is detected before failure without being responsible for the immediate failure. Nevertheless this gate leakage current is not without effect on the integrity of the SiC MOSFETs. Based on several robustness tests performed on SiC MOSFETs and on the comparison with experimental results obtained with SiC BJTs, the paper points out two main failure modes for SiC MOSFETs. The first one results in a simultaneously short circuit between drain and gate and drain and source and the second one in a degradation of the insulation between gate and source leading to a short circuit between gate and source. For some tested devices, the failure appears in a very interesting open state mode between drain and source after physical short-circuit between gate and source with a mode of failure very similar to those observed for SiC BJT.

Published
2015
Full Text
View/download PDF

9. Impact of Single Event Gate Rupture and Latent Defects on Power MOSFETs Switching Operation

Author

Antoine Touboul, A. Privat, Francois Forest, Eric Lorfevre, Richard Arinero, Frédéric Wrobel, Jean-Jacques Huselstein, Frédéric Saigné, N. Chatry, Mickael Petit, G. Chaumont, J.-R. Vaille, S. Bourdarie, Institut d’Electronique et des Systèmes (IES), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Radiations et composants (RADIAC), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Laboratoire de Métrologie et de Dosimétrie des Neutrons (LMDN), Institut de Radioprotection et de Sûreté Nucléaire (IRSN), Groupe énergie et matériaux (GEM), Institut de recherche en astrophysique et planétologie (IRAP), Institut national des sciences de l'Univers (INSU - CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Observatoire Midi-Pyrénées (OMP), Météo France-Centre National d'Études Spatiales [Toulouse] (CNES)-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD)-Météo France-Centre National d'Études Spatiales [Toulouse] (CNES)-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD)-Centre National de la Recherche Scientifique (CNRS), Université de Nîmes (UNIMES), ONERA - The French Aerospace Lab [Toulouse], ONERA, Composants à Nanostructure pour le moyen infrarouge (NANOMIR), TRAD [Labège], TRAD, STMicroelectronics, and Centre National d'Études Spatiales [Toulouse] (CNES)

Subjects
Nuclear and High Energy Physics, Materials science, business.industry, Electrical engineering, [SPI.TRON]Engineering Sciences [physics]/Electronics, Stress (mechanics), Nuclear Energy and Engineering, Hardware_INTEGRATEDCIRCUITS, Gate driver, Enhanced degradation, Energy transformation, Power semiconductor device, Electrical and Electronic Engineering, Power MOSFET, business, Sensitivity (electronics), Event (particle physics), ComputingMilieux_MISCELLANEOUS
Abstract

This paper reports on the impact of single event gate rupture and post-irradiation gate stress on Power MOSFETs switching ability. A dedicated setup has been developed and presented in this paper. The data showed that devices can switch after Single Event Gate Rupture. Failure of energy conversion system does not depend on gate current of the device but its associated external circuitry. Moreover, the data showed that devices having a gate layout constituted of parallel stripes are less sensitive than hexagonal shape when electrical constraints are applied after failure. It was also observed that the sensitivity of SEGR can be enhanced by X-ray irradiation but enhanced degradation is not observed during the switching operation.

Published
2014
Full Text
View/download PDF

10. Instrumented Chip Dedicated to Semiconductor Temperature Measurements in Power Electronic Converters

Author

Jean-Christophe Crebier, Ibrahima Ka, Benoit Thollin, Mickael Petit, Laurent Dupont, Raha Vafaei, Yvan Avenas, Laboratoire de Génie Electrique de Grenoble (G2ELab), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Technologies pour une Electro-Mobilité Avancée (SATIE-TEMA), Composants et Systèmes pour l'Energie Electrique (CSEE), Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)-École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)-Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), and Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)

Subjects
Computer science, 020209 energy, INSTRUMENTED CHIP, 02 engineering and technology, 7. Clean energy, Temperature measurement, THERMO SENSITIVE ELECTRICAL PARAMETER (TSEP), SURVEILLANCE, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Calibration, MESURE, CAPTEUR, [PHYS.PHYS.PHYS-INS-DET]Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det], POWER ELECTRONIC CONVERTER, TEMPERATURE, business.industry, 020208 electrical & electronic engineering, Electrical engineering, Process (computing), Dissipation, Converters, Chip, Power (physics), Power module, business
Abstract

ECCE 2016 - IEEE Energy Conversion Congress and Exposition, Milwaukee, ETATS-UNIS, 18-/09/2016 - 22/09/2016; Temperature measurement of semiconductor components is essential, in particular to evaluate performances and to propose health monitoring of power modules.ThermoSensitive Electrical Parameters (TSEPs) are widely used to estimate a representative temperature of these components, mainly in non-operating conditions, different from the real environment of the latter (offline measurements). Nevertheless, some TSEPs may be adapted to online temperature measurements, in operating conditions of power converters. It is however difficult to evaluate the accuracy of those TSEPs. This paper presents an instrumented chip dedicated to estimate the temperature in power electronic modules under functional constraints. Thus, it offers a reliable and robust tool for temperature measurements in power electronic converters. Preliminary results presented in this paper concern the technological process of realization and demonstrate the good functioning of this instrumented chip under power dissipation and switching conditions.

Full Text
View/download PDF

Catalog

Books, media, physical & digital resources
See catalog results