Search

3D Multi-stacking technology using Cu-Cu hybrid wafer bonding has been developed to achieve superior power, speed performances and higher density with minimized form factor. To realize multi-stacked device by using Wafer on wafer (WoW) bonding, both Face-to-Face (F2F) and Back-to-Face (B2F) interconnection can be required for more efficient and simple I/O pad design as well as lower resistance thanks to shorter interconnections. In this paper, we successfully demonstrated wafer-level multi-stacking structure by applying robust Cu-to-Cu bonding combined with Through-Si-Via (TSV) process. Three key subjects of comprehensive understanding about bonding interface, TSV and edge engineering to avoid defects and yield drop were essential to fulfill this research. Chemical-Mechanical-Polishing (CMP) and surface treatment had a huge impact on the Cu/dielectric hybrid bonding surface. In particular, planarization at the backside of the wafer is the key technology for robust follow up wafer bonding. For TSV formation, etch advancement performed to control the enhanced target compared to existing scheme. One more key subject is the edge engineering including integration considered edge treatment and effect by the process has been conducted to improve wafer bonding quality and reproducibility. Through the optimization of multi-stack oriented processes and integration, we confirmed extremely high yield of electrical connection including wafer edge for multiple layers. Many valuable applications can be introduced for sensors, memories, logic devices and even combinations of them by utilizing this novel processes.

This paper reports a 1280×960 DVS. A 4.95-μm pixel pitch is achieved with in-pixel Cu-Cu connection and the newly designed GIDL-suppression scheme. A sequential column selection scheme and a global event-holding function are implemented to minimize motion artifacts. The power consumption per pixel of 122 nW is 1.25× smaller and the maximum readout speed of 1.3 Geps is 4.33× faster than the previous state-of-the-art.

Phase change memory (PCM) that is operated on resistance changes caused by joule heating has been suggested as the next-generation memory for scaling since its programming current scales linearly. We propose a U-shaped cell design to further reduce the reset current in PCM devices, which enables easier and more efficient scaling than conventional PCMs. Simulation studies of heat transfer demonstrated that our U-shaped design with a dashed heater has a higher thermal efficiency of 4.97 K/μA compared to 3.36 K/μA in a lance cell with a ring heater for the same storage node. The reset current can be better scaled proportionate to k 2.0 in which the exponent is higher than the lance cell of k 1.5 in non-isotropic scaling. This better scalability is attributed to the small programming volume of the U-shaped cell, which was verified by transmission electron microscopy analysis. Furthermore, the cyclic endurance of the U-shaped cell was enhanced by 1 order of magnitude compared to a lance cell and the thinner CGeSbTe films reduced the reset current further. Our results show that a U-shaped cell is a highly promising design to scale reset current in next-generation PCM devices.

High density 1Gb embedded STT-MRAM in 28nm FDSOI technology was successfully demonstrated. Based on the highly reliable and manufacturable eMRAM technology, high yield over 90% was achieved at the operating temperature from −40°c to 105°c with satisfying read, write function and 10 years retention at 105°c. These results are mainly attributed to the advanced process for better control of MTJ CD, highly manufacturable process window and robust circuit design for high density chip. MTJ properties can be systematically adjusted by tailoring the MTJ stack and MTJ module process. Improved endurance up to 1E10 cycles was achieved to broaden eMRAM applications to eDRAM replacement.

The scaling of semiconductor device below 10nm has faced the higher process difficulty and longer development periods. Three-dimensional integrated circuits (3D IC) using chip partitioning and wafer-to-wafer bonding have been acknowledged as the next generation semiconductor stacking technology because of smaller form factor, higher density integration and higher performance compared to same-node devices. Wafer-to-wafer bonding is widely used in stacked CMOS image sensor, that is, the bonding between pixel and logic wafer, and this technology has the potential to apply other semiconductor devices. Cu-Cu hybrid bonding has achieved by simultaneous wafer bonding of metal (Cu-Cu) and dielectric materials. In this study, it is investigated on the microstructure of Cu pad for Cu-Cu bonding after post-electroplating and post-bonding annealing process. The Cu grain size distribution and orientation are analyzed with different anneal temperature, which is applied on electroplated Cu, and with additional heat treatment as post-bonding process. The effect of pad size as well as the position within pattern array on Cu microstructure is also studied as the bonding pad is required smaller and smaller size for high density bonding. After Cu-Cu bonding, the cross-section analysis of bonding interface is carried out to see inter-diffusion of Cu atoms across the opposite Cu pad. Cu-Cu hybrid bonding is applied to test vehicle having the daisy chain of 2.4 million. The electrical resistance is measured before and after thermal stress and the Cu-Cu bonding interface is confirmed as robust structure.

As the cell size of phase change memory devices decreases to less than 100 nm, the dry etch used for cell patterning becomes extremely critical because of its impact on the properties of memory cells. HBr gas has been known as the etchant that can minimize surface etching damage to GeSbTe-based phase change materials. However, the findings reported herein show that the HBr etch of CGeSbTe (CGST) films causes voids after annealing at temperatures below 400 °C due to the vaporization of volatile bromides (GeBr4, SbBr2, and TeBr2) that form when bromine diffuses during the etch. In this investigation, we report on the use of NH3 etchants to suppress the formation of volatile compounds and thereby eliminate void formation in CGST materials. The properties of NH3 etchants were compared to those of HBr etchants as a function of both etch rate and profiles. The effects of void suppression as observed in transmission electron microscopy images of as-etched CGST film after annealing indicate that phase change memory devices etched using an NH3 exhibited enhanced set cycles that were over 108 superior to results of HBr etchants by 2 orders of magnitude.

We successfully demonstrated the manufacturability of 8Mb STT-MRAM embedded in 28nm FDSOI logic platform by achieving stable functionality and robust package level reliability. Read margin were greatly improved by increasing TMR value and also reducing distribution of cell resistance using advanced MTJ stack and patterning technology. Write margin was also increased by improving the efficiency using novel integration process. Its product reliability was confirmed in package level with passing HTOL 1000 hours tests, 106 endurance test, and retention test. For a wider application, we also demonstrated the feasibility of high density 128Mb STT-MRAM. Based on these results, we clearly verified the product manufacturability of embedded STT-MRAM.

We demonstrate, for the first time, 28-nm embedded STT-MRAM operating at full industrial temperature range (−40~125°C) with >1E+6 endurance and >10 year retention for high speed MCU/IoT application. Robust cell operation is also demonstrated after solder reflow (260°C, 90 second) and during external magnetic disturbance (550-Oe under writing). It is built on 28-nm FDSOI technology in modular format for IP reuse and has great potential to serve wide variety of applications such as IoT, and high performance MCU.

In this paper, a physical mechanism for hot carrier injection (HCI) induced trap generation and degradation in bulk FinFETs is investigated and verified with both experiment and simulation evidence. HCI degradation is mainly caused by interface states generated by drain avalanche hot carrier injection. From this model, impact ionization intensity, location and trapping immunity are proposed as key parameters to modulate HCI degradation. HCI reliability in I/O FinFETs is severely degraded with respect to planar FETs because of the enhanced capability of the gate to control the channel potential profiles increasing the intensity of the lateral E-field in comparison with planar devices. Based on this FinFET HCI mechanism, we have successfully optimized source/drain junction process to achieve reliable HCI characteristics for 14nm and 10nm FinFET devices.

A two-step annealing method with a low thermal budget is proposed for advanced surface-energy-driven secondary grain growth of Ge films without any agglomeration. In the first-step annealing, the normal grain growth from as-deposited poly-crystalline Ge films was induced to make the grain size equivalent to the film thickness at 800 °C. After the subsequent second-step annealing at 900 °C, the much larger secondary grains were obtained than those by single-step annealing at 900 °C. The possible explanation regarding the final microstructure of the two-step annealed film is proposed. The two-step annealing was able to form the microstructure of Ge thin film with very large-grained matrix without any agglomeration, resulting in higher carrier mobility. Therefore, the proposed two-step annealing is believed to be a promising process applicable for channel formation processes in the next-generation Ge thin film transistors for 3D integrated circuits and vertical NAND flash memories.

As a versatile processing method for nanoscale memory integration, laser-induced epitaxial growth is proposed for the fabrication of vertical Si channel (VSC) transistor. The fabricated VSC transistor with 80 nm gate length and 130 nm pillar diameter exhibited field effect mobility of 300 cm²/Vs, which guarantees “device quality”. In addition, we have shown that this VSC transistor provides memory operations with a memory window of 700 mV, and moreover, the memory window further increases by employing charge trap dielectrics in our VSC transistor. Our proposed processing method and device structure would provide a promising route for the further scaling of state-of-theart memory technology.

A novel tensile Si (tSi) and compressive SiGe (cSiGe) dual-channel FinFET CMOS co-integration scheme, aimed at logic applications for the 5nm technology node and beyond, is demonstrated for the first time, showing electrical performance benefits and excellent co-integration feasibility. A Strain-Relaxed SiGe Buffer (SRB) layer is introduced as buried stressor and successfully transfers up to ∼1 GPa uniaxial tensile and compressive stress to the Si/SiGe n-/p-channels simultaneously. As the result, both tSi and cSiGe devices show a 40% and 10% electron and hole mobility gain over unstrained Si, respectively. Through a novel gate stack solution including a common interfacial layer (IL), HK, and single metal gate for both n- and pFET, secured process margin for 5nm gate length, low interface trap density (Dit) for SiGe channel and threshold voltage (Vt) target for both the Si and SiGe device are successfully demonstrated. Lastly, reliability investigation shows that tSi and cSiGe, employing the newly developed common gate stack scheme, possess superior reliability characteristics compared with those of equivalent Si devices.

In this work, the oxide electric field (Eox) reduction caused by negatively charged traps is proposed to explain the robustness of SiGe pMOSFETs to negative gate bias temperature instability (NBTI) stress. The high density of negatively charged acceptor-like traps close to the SiGe valance band (E v ) lowers the E ox and reduces the NBTI degradation at fixed overdrive. We demonstrate that trap engineering can be exploited to meet aggressive reliability requirements. Furthermore, it is predicted that there are no reliability issues in the SiGe pMOSFETs comparing with the Si counterparts.

Three-dimensional stacked memory has attracted much attention due to its advantages such as high-speed operation, low-power consumption, and high-level integration. Many researchers have reported various novel approaches to achieve three dimensional device integration, including wafer bonding, epitaxial lateral overgrowth (ELO), zone melting recrystallization (ZMR), and lateral-solid phase epitaxy (L-SPE). These methods have some limitations, in terms of the requirement of stacked memory process which include simple integration process, low thermal budget due to the performance degradation of underlying devices and single crystalline quality on oxide. In this work, we suggest a laser-induced epitaxial growth (LEG) process that utilizes a single crystalline seed grown by selective epitaxial growth (SEG) process. This seed layer was formed in patterned contact holes linking the substrate Si and the stacked layer. A raised seed could prevent the degradation of electrical properties of underlying devices. An excimer laser was then used as a light source of the epitaxial growth via recrystallization to melt the deposited amorphous Si films both on oxide layer and seed contact during several nano-seconds.

The technology of increasing Internal Vcc without using memory tester is used to enhance the photon emission and the failure range is defined in detail by nano probing. With these methods, we found out that the leakage current was caused by dislocations of STI arranged in a row.

We have investigated thin film transistors (TFTs) with ultra-thin polycrystalline silicon (poly-Si) of 77 A – 185 A. The TFT charge transfer characteristics such as ON current and effective mobility are dominated not by the thickness itself but by the grain size of poly-Si channel. When the poly-Si channel thickness is decreased with the same grain size, the sub-threshold TFT characteristics are improved without degradation of ON current and reliability properties. These results give us appropriate criteria to establish an excellent poly-Si channel in vertical NAND flash memory.

We suggested the heterogeneously stacked oxide (HSO) for the future tunnel oxide of high density NAND flash memory. HSO has a structure of SiO 2 /a-Si/a-SiOx using the concept of tunnel barrier engineering. By employing HSO tunnel barrier, it was possible to fabricate the tunnel oxide, which is thicker physically and thinner electrically than the single layer tunnel oxide. The bandgap of a-SiOx can be modified, which made it possible to achieve tunnel barrier engineering without employing high-k material. By reducing the erase voltage, the reliabilities of NAND flash memory was improved.

The improvement of device performances has been achieved successfully through OAO IPD EOT scaling, which shows that OAO IPD is applicable to sub-40nm devices which require aggressive scaling of IPD EOT. Charge loss of OAO IPD at high temperature is explained by thermionic emission of alumina traps. Trap profiles of alumina were obtained by monitoring Vth shift above 100°C. OAO IPD shows good data retention at room temperature, which is consistent with trap profiles.

Novel Al/sub 2/O/sub 3/ process was developed in order to extend the applicability of reliable SIS and MIS Al/sub 2/O/sub 3/ capacitors as well as Al/sub 2/O/sub 3/ EBL for a MIM capacitor. By applying ALD process utilizing a smart growth mechanism, electrical and interfacial properties of Al/sub 2/O/sub 3/ film were surprisingly improved. The SIS and MIS Al/sub 2/O/sub 3/ capacitor technologies with ultra-low thermal budget were confirmed by producing fully working 1 Gbit DRAM with design rule of 0.15 and 0.13 /spl mu/m, respectively. Moreover, Al/sub 2/O/sub 3/ EBL for a MIM capacitor was successfully used to preserve the excellent dielectric characteristics for the application of DRAM with design-rule of 0.10 /spl mu/m, and beyond.

The advanced solid phase crystallization (SPC) method using the SiGe/Si bi-layer structure is proposed to obtain high-mobility poly-Si thin-film transistors in next generation vertical NAND (VNAND) devices. During the SPC process, the top SiGe thin film acts as a selective nucleation layer to induce surface nucleation and equiaxial microstructure. Subsequently, this SiGe thin film microstructure is propagated to the underlying Si thin film by epitaxy-like growth. The initial nucleation at the SiGe surface was clearly observed by in situ transmission electron microscopy (TEM) when heating up to 600 °C. The equiaxial microstructures of both SiGe nucleation and Si channel layers were shown in the crystallized bi-layer plan-view TEM measurements. Based on these experimental results, the large-grained and less-defective Si microstructure is expected to form near the channel region of each VNAND cell transistor, which may improve the electrical characteristics.