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Forecasting the electricity consumption has always played an important role in the management of power system management, which requires higher forecasting technology. Therefore, based on the principle of “new information priority”, combined with rolling mechanism and Markov theory, a novel grey power-Markov prediction model with time-varying parameters (RGPMM(λ,1,1)) is designed, which overcomes the inherent defects of fixed structure and poor adaptability to the changes of original data. In addition, in order to prove the validity and applicability of the prediction model, we have used the model to predict China’s total electricity consumption, and have compared it with the prediction results by a series of benchmark models. The result shows that the can better adapt to the characteristics of electricity consumption data, and it also shows the advantages of the proposed forecasting model. In this paper, the proposed forecasting model is used to predict China’s total electricity consumption in the next six years from 2018 to 2023, so as to provide certain reference value for power system management and distribution.

Van der Waals heterostructures composed of two-dimensional (2D) transition metal dichalcogenides (TMD) materials have stimulated tremendous research interest in various device applications, especially in energy-efficient future-generation electronics. Such ultra-thin stacks as tunnel junction theoretically present unprecedented possibilities of tunable relative band alignment and pristine interfaces, which enable significant performance enhancement for steep-slope tunneling transistors. In this work, the optimal 2D-2D heterostructure for tunneling transistors is presented and elaborately engineered, taking into consideration both electric properties and material stability. The key challenges, including band alignment and metal-to-2D semiconductor contact resistances, are optimized separately for integration. By using a new dry transfer technique for the vertical stack, the selected WS2/SnS2 heterostructure-based tunneling transistor is fabricated for the first time, and exhibits superior performance with comparable on-state current and steeper subthreshold slope than conventional FET, as well as on-off current ratio over 106 which is among the highest value of 2D-2D tunneling transistors. A visible negative differential resistance feature is also observed. This work shows the great potential of 2D layered semiconductors for new heterostructure devices and can guide possible development of energy-efficient future-generation electronics.

In this letter, a novel graded-channel heterojunction tunnel field-effect transistor (GCH-TFET) is proposed and studied by simulation. The novel TFET adopts a near broken-gap heterojunction at the source/channel interface to enhance the tunnel efficiency. Besides, it employs a graded component channel which works as an electron barrier to block up the leakage current at the OFF-state and can be removed with the increased gate voltage at the ON-state for high ON/ OFF-current ( ${I}_{\scriptscriptstyle\text {ON}}/{I}_{\scriptscriptstyle\text {OFF}}$ ) ratio. Such graded channel also allows a sudden turn-on of band-to-band tunneling, resulting in a reduced sub-threshold swing (SS) compared with conventional heterojunction TFETs. The GCH-TFET demonstrates an ${I}_{\scriptscriptstyle\text {ON}}/{I}_{\scriptscriptstyle\text {OFF}}$ ratio of more than seven decades with ${I}_{\scriptscriptstyle\text {ON}}$ up to 225 $\mu \text{A}/\mu \text{m}$ at ${V}_{\textsf {DD}} = \textsf {0.3}$ V, ${I}_{\scriptscriptstyle\text {OFF}}$ more than two decades lower than a near broken-gap heterojunction TFET and SS lower than 30 mV/decade for more than five decades, exhibiting excellent potential for ultra-low power applications.

As one of the important sources of low-frequency noise, random telegraph noise (RTN) in tunnel FET (TFET) has attracted growing attention recently. However, there is still lack of explanation for the high-amplitude RTN, which may cause serious variability and reliability problems to TFET-based ultralow-power circuits. In this paper, we experimentally investigate the RTN amplitude characteristics in TFETs, revealing the mechanism of high-amplitude RTN. It is found that the nonuniform distribution of band-to-band tunneling (BTBT) generation rate along device width direction is responsible for the high-amplitude RTN. Locations with relatively higher BTBT generation rate may act as critical paths dominating the device current. “Lucky” trap located at a critical path can induce the high-amplitude RTN. With device width shrinking, the number of critical paths may be reduced, resulting in much higher maximum RTN amplitude. In addition, the impacts of process parameters on RTN amplitude are discussed. Both higher source doping concentration ( $\text{N}_{\text {S}})$ and higher thermal budget can effectively mitigate the nonuniformity of BTBT generation rate along device width direction, causing suppressed RTN amplitudes. Considering that the higher thermal budget may lead to degraded device performance, the annealing process should compromisingly be designed in terms of both variation and device performance.

In this letter, a novel hetero-stacked TFET (HS-TFET) is experimentally demonstrated and optimized for the first time, which can effectively suppress the sub-threshold slope (SS) degradation without leakage current increase through self-adaptively current replenishing with bandgap engineering, greatly alleviating the critical issue of high average SS in conventional TFETs. Based on CMOS-compatible technology, the fabricated HS-TFETs of vertically stacked Si-Si1–xGex source can experimentally achieve superior performance with nearly constant SS over five decades of drain current, high $I_{{{\mathrm{\scriptscriptstyle ON}}}}$ ( $\sim 14\mu \text{A}/\mu \text{m}$ @ $V_{\mathrm {DS}}=-1$ V), and large $I_{{{\mathrm{\scriptscriptstyle ON}}}}/I_{{{\mathrm{\scriptscriptstyle OFF}}}}$ ratio ( $\sim 10^{7})$ . The proposed device with high process compatibility shows great potentials for future ultra-low power applications.

Oxide-based resistive switching devices have tremendous potential in next-generation nonvolatile memory and neuromorphic applications. Here, the emergence of quantized conductance is investigated in resistive switching devices based on Ta 2 O 5 or HfO 2 . By applying sweeping voltages with different current compliances or using consecutive voltage pulses, quantized conductance states including integer and half integer multiples of quantum conductance (G 0 ) were observed, suggesting well-controlled formation of atomic point contacts. Compared with Pt/Ta/Ta 2 O 5 /Pt devices, a larger number of quantized conductance states were obtained in the Pt/Ta/HfO 2 /Pt devices. Such quantized conductance states are inherently discrete and multilevel, which could be promising for applications as multilevel nonvolatile memory and artificial synapses in hardware neural networks.

Purpose The purpose of this study was to evaluate the interocular differences in choroidal vasculature, choriocapillaris perfusion, and retinal microvascular network, and to explore their associations with interocular asymmetry in axial lengths (ALs) in children with anisomyopia. Methods Refractive error, AL, and other biometric parameters were measured in 70 children with anisomyopia. Using optical coherence tomography (OCT) and OCT-angiography, we measured the submacular choroidal thickness (ChT), total choroidal area (TCA), luminal area (LA), stromal area (SA), choroidal vascularity index (CVI), choriocapillaris flow deficit (CcFD), retinal vessel density (VD), and foveal avascular zone (FAZ) area. Results The mean interocular differences in spherical equivalent refraction and AL were −2.26 ± 0.94 diopters and 0.95 ± 0.46 mm, respectively. Submacular ChT, TCA, LA, SA, and CVI were all significantly lower in the more myopic (longer AL) eyes than in the less myopic (shorter AL) fellow eyes. In eyes with longer ALs, both the CcFD and FAZ areas were significantly greater, whereas the superficial and deep retinal VDs were significantly less. After adjusting for corneal power and intraocular pressure, interocular differences in LA (β = −0.774), SA (β = −0.991), and CcFD (β = 0.040) were significantly associated with interocular asymmetry in AL (all P < 0.05). Conclusions In pediatric anisomyopes, eyes with longer ALs tended to have lower choroidal vascularity and choriocapillaris perfusion than the contralateral eyes with shorter ALs. Longitudinal investigations would be useful follow-ups to test for a causal role of choroidal circulation in human myopia.

The rapid development of information technology has led to urgent requirements for high efficiency and ultralow power consumption. In the past few decades, neuromorphic computing has drawn extensive attention due to its promising capability in processing massive data with extremely low power consumption. Here, we offer a comprehensive review on emerging artificial neuromorphic devices and their applications. In light of the inner physical processes, we classify the devices into nine major categories and discuss their respective strengths and weaknesses. We will show that anion/cation migration-based memristive devices, phase change, and spintronic synapses have been quite mature and possess excellent stability as a memory device, yet they still suffer from challenges in weight updating linearity and symmetry. Meanwhile, the recently developed electrolyte-gated synaptic transistors have demonstrated outstanding energy efficiency, linearity, and symmetry, but their stability and scalability still need to be optimized. Other emerging synaptic structures, such as ferroelectric, metal–insulator transition based, photonic, and purely electronic devices also have limitations in some aspects, therefore leading to the need for further developing high-performance synaptic devices. Additional efforts are also demanded to enhance the functionality of artificial neurons while maintaining a relatively low cost in area and power, and it will be of significance to explore the intrinsic neuronal stochasticity in computing and optimize their driving capability, etc. Finally, by looking into the correlations between the operation mechanisms, material systems, device structures, and performance, we provide clues to future material selections, device designs, and integrations for artificial synapses and neurons.

Magneto-electronic logic is an innovative approach to performing high-efficiency computations. Additionally, the ultra-large scale integration requirement for computation strongly suggests exploiting magnetoresistance effects in non-magnetic semiconductor materials. Here, we demonstrate the magnetoresistance effect in a silicon nanowire field effect transistor (SNWT) fabricated by complementary metal-oxide-semiconductor (CMOS)-compatible technology. Our experimental results show that the sign and the magnitude of the magnetoresistance in SNWTs can be effectively controlled by the drain-source voltage and the gate-source voltage, respectively, playing the role of a multi-terminal tunable magnetoresistance device. Various current models are established and in good agreement with the experimental results that describe the impact of electrical voltage and magnetic field on magnetoresistance, which provides design feasibility for the high-density magneto-electronic circuit. Such findings will further pave the way for nanoscale silicon-based magneto-electronics logic devices and show a possible path beyond the developmental limits of CMOS logic.

Here we report a device size and structure dependent study on the resisitive switching and synaptic plasticity in HfO2-based memristive devices. We found that the on/off ratio of resistive switching constantly increases as device size decreases, and bilayer Pt/TaO x /HfO 2 /Pt devices generally exhibit more uniform switching characteristics and lower threshold voltages compared with single-layer Pt/HfO 2 /Pt devices. Long-term potentiation and depression behaviors have been emulated using such bilayer devices, suggesting potential applications for neuromorphic hardware.

In this work, the power, performance and area of novel multi-Finger Schottky-Barrier Tunnel FET (mFSB-TFET) are benchmarked with standard MOSFET and low-power MOSFET from device and circuit level. Under the same area penalty, mFSB-TFET circuits could obtain comparable delay with significantly lower static and total power consumption by orders of magnitude than standard MOSFET circuits. The advantages are more significant at ultra-low working voltage, even compared with low-power MOSFET circuits, indicating great practical potential of mFSB-TFET for ultra-low power application.

In this paper, a novel combinational access topology of Tunnel FET (TFET) SRAM is proposed for ultra-Low Power applications. Since forward p-i-n current of TFET could cause serious damage to SRAM circuit performance, the proposed topology can avoid the forward bias applied to the p-i-n junction, thus increasing SRAM cell read and hold static noise margin (SNM) and decreasing its static power consumption dramatically. At 0.6 V supply voltage, the combinational access TFET SRAM topology presents 26% hold SNM larger than traditional TFET SRAM topologies, 8 orders of magnitude lower static power consumption, and 2 order of magnitude lower power delay product, demonstrating its great potential for ultra-low power applications.

The gate dielectrics reliability in Tunnel FETs (TFETs) has been thoroughly investigated for the first time, which is found to be the dominant device failure mechanism compared with bias temperature ins tability degradation, and is much worse than MOSFETs with the same gate stacks due to a new stronger localized dielectric field peak at gate/source overlap region. The non-uniform electric field of dielectric in TFET also leads to the different mechanisms between soft breakdown and hard breakdown failure. Moreover, dielectric-field-associated parameters are discussed in detail, showing an intrinsic trade-off between dielectrics reliability and device performance optimization caused by the positive correlation between dielectric field and source junction field. A new robust design consideration is further proposed for reliability and performance co-optimization, which is experimentally realized by a new TFET design with both dramatically improved performance and reliability, indicating its great potentials for ultralow-power applications.

Neuromorphic engineering offers a promising route toward intelligent and low power computing systems that may find applications in artificial intelligence and the Internet. Construction of neuromorphic systems, however, requires scalable nanodevices that could implement the key functionalities of biological synapses. Here, we demonstrate an artificial synaptic device consisting of a Ti/yttria-stabilized-zirconia (ZrO2:Y)/Pt memristive structure, where the loss microstructure, high oxygen vacancy concentration, and resultant high ionic conductivity in ZrO2:Y facilitate the oxygen vacancy migration and filament evolution in the devices, leading to a bipolar artificial synapse with low forming and operation voltages. As the thickness of ZrO2:Y film increases, a transition from bipolar to unipolar resistive switching was observed, which can be ascribed to the competing vertical and radial ion transport dynamics. The emergence of unipolar switching has in turn allowed the device to exhibit metaplasticity, a history dependent plasticity that is important for memory and learning functions. This work thus demonstrates on-demand manipulation of ionic transport properties for building synaptic elements with rich functionalities.

In the above paper [1] , there is an error in the information of corresponding author’s email address. The corrected corresponding author’s email address information is underlined and shown as follows

BiFeO3 thin films were epitaxially grown on (001) GaAs substrate by pulsed laser deposition with Nb doped SrTiO3 as a buffer layer. Piezoresponse force microscopy images exhibit effective ferroelectric switching of the heterostructure. The temperature-dependent current-voltage characteristics of the heterostructure reveal a resistance switching phenomenon and diode-like behavior with a rectifying ratio of 2 × 102 at the applied voltage of ±13.4 V. The electrical transport mechanism in the heterostructure has been illustrated by constructing the energy band structure. In addition, the resistance switching behavior in the heterostructure could be explained by the polarization modulation of the depletion region at the interface of the semiconductor and the ferroelectric layers.