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The high peak mobility of 509 cm2/ $\text {V}\cdot \text {s}$ of the chemical vapor deposition -grown GeSn pMOSFETs is obtained using 1-nm Ge cap. The Ge cap on GeSn can reduce the scattering of oxide/interface charges and surface roughness for the holes in the GeSn quantum wells. However, the thick cap induces holes in the Ge cap itself, leading lower mobility than GeSn channels. The on current is enhanced by external stress due to the effective mass reduction. The normalized noise power density of the GeSn devices decreases with increasing Ge cap thickness, indicating the carrier number fluctuation and correlated mobility fluctuation are suppressed when the holes are away from interface.

The channel cross section geometry and size dependence of the electron mobility in Ge nanowire nFETs is studied by theoretical calculations for devices beyond the 7nm node. circular channels have the highest mobility for wide channels (width>7nm) operating at high overdrive voltage (>0.5V). While diamond-shaped channels have the highest mobility for wide channels operating at low overdrive voltage (

The performance variation caused by the stress field near a through-silicon via (TSV) is measured using 28-nm node devices across 12-in wafers. The TSV is fabricated by a via-last process. The back-end-of-line dielectrics on TSV cause the asymmetric stress field, i.e., the absolute value of radial stress ( $\vert \sigma _{r}\vert )$ does not equal to that of tangential stress ( $\vert \sigma _{\theta }\vert )$ on silicon and leads to the asymmetric keep-out zone (KOZ), different from previously reported. A modified KOZ model with the asymmetric radial and tangential stress field is proposed and verified by 3-D finite-element analysis simulation and experiment data. The physics behind the asymmetry is also described. Comparable KOZ size for nFETs and pFETs is observed.

It is the first time that CVD-grown GeSn channels with low thermal budget of 400°C significantly outperforms the Ge channel processed at high thermal budget of 550°C. Low thermal budget is necessary to prevent the Sn loss during the process. Note that only MBE-grown GeSn had large mobility reportedly in the past. Even with high Sn content (9%), the strong photoluminescence is observed from GeSn layers on Ge buffer on 300mm Si (001), indicating the high crystalline quality by CVD epitaxy. Ge cap with significant Δ Ev at Ge/GeSn interface can ensure the gate stack quality, and reduce the scattering of holes in the GeSn quantum wells by oxide/interface charges and surface roughness. However, the mobility is degraded by thick cap due to low hole population in the GeSn wells. The ∼7% mobility enhancement on channel direction is observed using external transverse uniaxial tensile strain of ∼0.11% due to the reduction of effective mass. The mobility of GeSn QW p-MOSFETs increases with decreasing temperature at both high and low inversion carrier density, indicating that the mobility is dominated by phonon scattering. On the contrary, Ge channels are dominated by Coulomb scattering at low inversion carrier density, which has decreasing mobility with decreasing temperature. The normalized noise power density of GeSn p-MOSFETs decreases with increasing Ge cap thickness, reportedly for the first time, indicating that the carrier number fluctuation and correlated mobility fluctuation can be reduced when the carriers are away from interface.

The low channel doping concentrations of 1.2×1019 cm−3 to deplete the channel and the high S/D doping of 1.2×1020 cm−3 to reduce the S/D resistance are achieved simultaneously by selective laser annealing on the same CVD P-doped epi-Ge on SOI without ion implantation. The device with Wfin down to 7 nm, EOT = 2.2 nm, and Lch = 60 nm has Ion = 1146 μA/pm, Ion/Ioff = 2×106, and SS = 95 mV/dec. The Ion can be further boost to 1235 μA/μm with external uniaxial tensile strain of 0.16%. The self-heating effect is responsible in part for such high Ion, because the high device temperature can reduce the dominant impurity scattering in the channel. The increasing mobility with increasing temperature indicates the impurity scattering is dominant. The lower low frequency noise is observed with junctionless (JL) gate-all-around (GAA) FETs than planar inversion mode (INV) devices due to the bulk conduction nature of JL FETs.

Pseudomorphic Ge 0.91 Sn 0.09 on Ge on Si with strong photoluminescence and low defect density is used for p-MOSFET channels. The mobility of Ge 0.91 Sn 0.09 Quantum Well p-MOSFETs are higher than control Ge p-MOSFETs due to hole population in the GeSn wells. The 7.5% mobility enhancement on channel direction is observed using external transverse uniaxial tensile strain (∼0.11%). The highest [Sn] of 9% in the channels grown by CVD, Pt SB S/D, high I on /I off ratio, and strain-enhanced mobility are obtained in this work.

In-situ CVD doping and laser anneal can reach [P] and tensile strain as high as 2×1020 cm−3 and 0.34%, respectively, in Ge on SOI with low defect density and high activation rate (nearly 100% near the surface), and enables high performance of the junctionless (JL) Ge gate-all-around (GAA) nFETs. The device with the W fin of 13 nm, EOT of 10 nm, and nominal L G of 280 nm has I on = 350 µA/µm, I on /I off = 3×106, SS = 185 mV/dec, and DIBL = 16 mV/V. The device with the W fin of 9 nm and EOT of ∼ 0.8 nm achieves the record high I on of 828 µA/µm at V GS - V T = 1.5 V and V DS = 2 V with DIBL = 54 mV/V, I on /I off = 1×105 and SS = 150 mV/dec. Besides the epitaxial tensile strain (0.34%) generated by laser anneal due to the misfit of thermal expansion coefficients between Ge and Si, the enhanced tensile strain by the microbridge structure is also beneficial for I on . The drain current enhancement of ∼40% is achieved under the mechanical uniaxial tensile strain of ∼0.25% due to sub-band splitting and carrier repopulation into the L4 valleys with the small conductive effective mass. The non-uniform shape of Ge channel with a minimum width at the center leads to enhanced I on as compared to uniform channel. The extracted mobility of JL devices increases with increasing temperature, indicating the domination of impurity scattering. The threshold voltage of JL devices has the negative temperature coefficient and EOT scaling reduces the temperature dependence.

Well-behaved Ge n-channel metal-oxide-semiconductor field-effect transistors on (001) substrates with dispersion-free, high on/off ratio, and high peak mobility are demonstrated. The interface trap density is effectively reduced down to 5 × 1011 cm−2 eV−1 near midgap by GeO2 passivation using rapid thermal oxidation, resulting in high peak mobility of ∼1050 cm2/Vs. The fast roll-off of the mobility at high electric field is probably due to the large surface roughness scattering. By applying uniaxial 〈110〉 tensile strain (0.08%) on 〈110〉 channel direction, the best mobility enhancement (12%) can be achieved. The calculated strain responses with proper stress configurations are consistent with experimental results.