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1. Co-integration of TSV mid process and optical devices for Silicon photonics interposers

Author

Frederic Boeuf, Jean Charbonnier, Benoit Charbonnier, Stephane Bernabe, F. Ponthenier, Pierre Tissier, Alexis Farcy, Jean-Emmanuel Broquin, and Remi Velard

Subjects
010302 applied physics, Silicon photonics, Computer science, Process (engineering), business.industry, ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Substrate (electronics), 021001 nanoscience & nanotechnology, Supercomputer, 01 natural sciences, Engineering physics, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Interposer, Wafer, Process variability, Photonics, 0210 nano-technology, business
Abstract

In the framework of High Performance Computing and Datacom, silicon photonics interposers propose an interesting approach, while providing new challenges. This paper demonstrates such an integration and focuses on TSV Mid integration impact on sensitive photonic structures such as ring modulators, focusing on two specific technological aspects: substrate thinning and TSV integration. It is shown that thinning down to 100 microns and integrating TSV do not impact photonic performances more than wafer level process variability. Finally, thanks to these results, 3D Si photonics design opportunities will be discussed.

Published
2020
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2. Active Interposer Technology for Chiplet-Based Advanced 3D System Architectures

Author

Didier Campos, P. Coudrain, Yorrick Exbrayat, Lucile Arnaud, Stephane Minoret, F. Ponthenier, Andrea Vinci, Severine Cheramy, Alain Gueugnot, Daniel Scevola, Cesar Fuguet Tortolero, P. Chausse, Roselyne Segaud, Giovanni Romano, Christophe Aumont, Didier Lattard, Jean Charbonnier, Pierre-Emile Philip, C. Ribiere, Arnaud Garnier, Jean Michailos, Mathilde Gottardi, Raphael Eleouet, Frédéric Berger, Eric Guthmuller, Gilles Simon, Jerome Beltritti, Gilles Romero, Maxime Argoud, Denis Dutoit, Alexis Farcy, Nacima Allouti, Therry Mourier, Remi Velard, Pascal Vivet, and Corinne Legalland

Subjects
010302 applied physics, Through-silicon via, business.industry, Computer science, 020208 electrical & electronic engineering, Process (computing), 02 engineering and technology, 01 natural sciences, Silicon interposer, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Technology integration, Interposer, business, Computer hardware
Abstract

We report the first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested. Benefits of chiplet-based architectures are discussed. Built up technology is presented and focused on 3D interconnects process and characterization. 3D packaging is presented up to the successful structural test and characterization of the demonstrator.

Published
2019
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3. Breakthroughs in 3D Sequential technology

Author

C. Scibetta, S. Beaurepaire, F. Fournel, A. Roman, S. Chevalliez, C. Fenouillet-Beranger, X. Garros, Xavier Federspiel, J. Aubin, V. Larrey, Perrine Batude, F. Kouemeni-Tchouake, F. Ponthenier, J-B. Pin, Daniel Scevola, Lucile Arnaud, F. Aussenac, C. Guerin, P. Acosta-Alba, V. Mazzocchi, Sebastien Kerdiles, H. Fontaine, Shay Reboh, P. Perreau, Sylvain Maitrejean, Laurent Brunet, N. Rambal, M. Vinet, Pascal Besson, Christophe Morales, T. Lardin, V. Balan, Vincent Jousseaume, D. Ney, F. Mazen, and Francois Andrieu

Subjects
010302 applied physics, Materials science, business.industry, Order (ring theory), 02 engineering and technology, Epitaxy, 01 natural sciences, Active devices, 020202 computer hardware & architecture, Design for manufacturability, Reliability (semiconductor), CMOS, Surface preparation, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, Wafer, business
Abstract

The 3D sequential integration, of active devices requires to limit the thermal budget of top tier processing to low temperature (LT) (i.e. $\mathrm{T}_{\text{TOP}}=500^{\circ}\mathrm{C})$ in order to ensure the stability of the bottom devices. Here we present breakthrough in six areas that were previously considered as potential showstoppers for 3D sequential integration from either a manufacturability, reliability, performance or cost point of view. Our experimental data demonstrate the ability to obtain 1) low-resistance poly-Si gate for the top FETs, 2) Full LT RSD epitaxy including surface preparation, 3) Stability of intermediate BEOL between tiers (iBEOL) with standard ULK/Cu technology, 4) Stable bonding above ULK, 5) Efficient contamination containment for wafers with Cu/ULK iBEOL enabling their re-introduction in FEOL for top FET processing 6) Smart Cut™ process above a CMOS wafer.

Published
2018
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4. ITAC: A complete 3D integration test platform

Author

Arnaud Garnier, Gael Pillonnet, R. Segaud, A. Jouve, Pascal Vivet, H. Jacquinot, Alexandre Arriordaz, Fabrice Casset, S. Cheramy, Jean Michailos, N. Bresson, Lucile Arnaud, C. Chantre, Sandrine Lhostis, Didier Lattard, K. Azizi-Mourier, Franck Bana, Alexis Farcy, F. Ponthenier, and Stephane Moreau

Subjects
Engineering, Integration testing, business.industry, 020208 electrical & electronic engineering, Stacking, 02 engineering and technology, Chip, Supercomputer, Die (integrated circuit), Reliability (semiconductor), Embedded system, 0202 electrical engineering, electronic engineering, information engineering, System integration, business, Electronic circuit
Abstract

System integration takes benefit from 3D stacking technology in a wide range of applications such as smart imagers, photonic, wide I/O memories and high-performance computing. The 700 mm2 ITAC 3D integration test platform contains a set of “Integrated Technological and Application Circuits” for process development, electrical and RF characterization, reliability, die stacking, warpage and underfilling studies, DC-DC converter and IntAct chip which is the full application chip. After a brief presentation of the targeted high performance computing application. The contributions integrated in the test platform are described with a particular focus on the 10 μm diameter 20 μm pitch die-to-die interconnects which is the key technology of the 3D stack. These test vehicles have been embedded on the same silicon to secure the application chip at all the steps from technology development to assembly and test.

Published
2016
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5. First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers

Author

L. Pasini, Perrine Batude, V. Benevent, Maud Vinet, Thomas Signamarcheix, R. Kachtouli, Sébastien Barnola, A. Royer, C. Vizioz, F. Fournel, J.M. Hartmann, G. Romano, N. Allouti, Sebastien Kerdiles, Christophe Morales, A. Seignard, C. Agraffeil, Frederic Boeuf, F. Ponthenier, Vincent Delaye, F. Deprat, M. Jourdan, L. Benaissa, L. Baud, C. Euvrard-Colnat, O. Faynot, Bernard Previtali, C. Guedj, P. Besombes, C. Comboroure, Claire Fenouillet-Beranger, L. Hortemel, Laurent Brunet, Claude Tabone, Nicolas Posseme, Alain Toffoli, C.-M. V. Lu, Christian Arvet, and Pascal Besson

Subjects
010302 applied physics, Very-large-scale integration, Engineering, business.industry, Electrical engineering, Silicon on insulator, 02 engineering and technology, 01 natural sciences, 020202 computer hardware & architecture, PMOS logic, Front and back ends, CMOS, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Wafer, business, Metal gate, NMOS logic
Abstract

For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Metal 1 level of an industrial short loop and the return in a front end environment is presented, confirming the industrial compatibility of CoolCube™ integration.

Published
2016
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6. New challenges and opportunities for 3D integrations

Author

Claire Fenouillet-Beranger, E. Saugier, Vincent Fiori, E. Deloffre, A. Jouve, Alexis Farcy, Francois Guyader, N. Hotellier, Laurent Brunet, Severine Cheramy, Pascal Vivet, Perrine Batude, F. Breuf, F. Ponthenier, Sandrine Lhostis, R. Prieto, Jean-Philippe Colonna, Maud Vinet, Yann Henrion, Perceval Coudrain, Yannick Sanchez, L. Benaissa, R. Velard, Fabrice Casset, Jean Michailos, B. Vianne, and L.-M. Collin

Subjects
Microelectromechanical systems, business.industry, Computer science, New product development, Hardware_INTEGRATEDCIRCUITS, Interposer, Systems engineering, Key (cryptography), Low density, Electronic engineering, Photonics, business
Abstract

From low density 3D integrations embedding Via Last Through Silicon Vias (TSV) to high densities hybrid bonding or 3D VSLI CoolCubeTM solutions, a multitude of new product opportunities is now envisioned. An overview of existing emerging 3D integrations is provided covering Image sensors, Photonics, MEMS, Wide I/O memories and Silicon Interposers for advanced logics. Associated key challenges and developments are highlighted focusing on 3D platform performance assessment.

Published
2015
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7. Monolithic 3D integration: A powerful alternative to classical 2D scaling

Author

O. Faynot, Ogun Turkyilmaz, F. Deprat, F. Ponthenier, M.-P. Samson, Hossam Sarhan, G. Cibrario, L. Pasini, V. Lu, Claude Tabone, J-E. Michallet, M. Vinet, Perrine Batude, N. Rambal, Fabien Clermidy, O. Billoint, JM Hartmannn, Claire Fenouillet-Beranger, O. Rozeau, Benoit Sklenard, Laurent Brunet, Sebastien Thuries, and Bernard Previtali

Subjects
Engineering, business.industry, law, Scale (chemistry), MOSFET, Transistor, Hardware_INTEGRATEDCIRCUITS, Electrical engineering, Electronic engineering, business, 3d ic design, Scaling, law.invention
Abstract

Monolithic or sequential 3D Integration is a powerful technological enabler for actual 3D IC design as the stacked layers can be connected at the transistor scale. This paper reviews the opportunities brought by M3DI and highlights the applications benefiting from this small 3D contact pitch. It also presents the technological challenges of this concept and offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.

Published
2014
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8. Gate-last integration on planar FDSOI MOSFET: Impact of mechanical boosters and channel orientations

Author

L. Brevard, C. Le Royer, C. Euvrard, F. Ponthenier, A. Seignard, O. Faynot, R. Gassilloud, David K. C. Cooper, Y. Morand, J.M. Hartmann, L. Tosti, S. Morvan, Claude Tabone, Thierry Poiroux, Maurice Rivoire, Pascal Besson, C. Leroux, F. Allain, B. Saidi, P. Perreau, X. Garros, M. Casse, Francois Andrieu, and P. Caubet

Subjects
Electron mobility, Materials science, Silicon, business.industry, Transistor, Silicon on insulator, chemistry.chemical_element, Equivalent oxide thickness, PMOS logic, law.invention, chemistry, law, Gate oxide, MOSFET, Electronic engineering, Optoelectronics, business
Abstract

We present for the first time Gate-Last (GL) planar Fully Depleted (FD) SOI MOSFETs featuring both ultra thin silicon body (3-5 nm) and BOX (25 nm). Transistors with metal-last on high-k first (TiN/HfSiON) have been successfully fabricated down to 15nm gate length. We have thoroughly characterized the gate stack (reliability, work-function tuning on Equivalent Oxide Thickness EOT=0.85nm) and transport (hole mobility, Raccess) for different surface and channel orientations. We report excellent ION, p=1020μA/μm at IOFF, p=100nA/μm at VDD=0.9V supply voltage for pMOS channel on (001) surface with in-situ boron doped SiGe Raised Source and Drain (RSD) and compressive CESL. This is explained by the high efficiency of the strain transfer into the ultra-thin channel, as evidenced by physical strain measurements (dark field holography).

Published
2013
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9. Gate-last integration on planar FDSOI for low-VTp and low-EOT MOSFETs

Author

X. Garros, P. Caubet, L. Tosti, Francois Andrieu, N. Allouti, C. Le Royer, F. Ponthenier, Sébastien Barnola, P.K. Baumann, S. Morvan, U. Weber, P. Perreau, Gerard Ghibaudo, A. Seignard, C. Euvrard, Yves Morand, Maurice Rivoire, L. Desvoivres, M.-C. Roure, C. Leroux, F. Martin, R. Gassilloud, M. Casse, Olivier Weber, Thierry Poiroux, Pascal Besson, Laboratoire de géologie de l'ENS (LGENS), Institut national des sciences de l'Univers (INSU - CNRS)-Centre National de la Recherche Scientifique (CNRS)-Département des Géosciences - ENS Paris, École normale supérieure - Paris (ENS Paris), Université Paris sciences et lettres (PSL)-Université Paris sciences et lettres (PSL)-École normale supérieure - Paris (ENS Paris), Université Paris sciences et lettres (PSL)-Université Paris sciences et lettres (PSL), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Département d'Astrophysique, de physique des Particules, de physique Nucléaire et de l'Instrumentation Associée (DAPNIA), Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Géosciences Environnement Toulouse (GET), Institut national des sciences de l'Univers (INSU - CNRS)-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Observatoire Midi-Pyrénées (OMP), Météo France-Centre National d'Études Spatiales [Toulouse] (CNES)-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD)-Météo France-Centre National d'Études Spatiales [Toulouse] (CNES)-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche pour le Développement (IRD), STMicroelectronics [Crolles] (ST-CROLLES), UMR CNRS 8179, Université de Lille, Sciences et Technologies-Centre National de la Recherche Scientifique (CNRS), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), École normale supérieure - Paris (ENS-PSL), Université Paris sciences et lettres (PSL)-Université Paris sciences et lettres (PSL)-École normale supérieure - Paris (ENS-PSL), Institut de Recherche pour le Développement (IRD)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut national des sciences de l'Univers (INSU - CNRS)-Observatoire Midi-Pyrénées (OMP), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut national des sciences de l'Univers (INSU - CNRS)-Centre National d'Études Spatiales [Toulouse] (CNES)-Centre National de la Recherche Scientifique (CNRS)-Météo-France -Institut de Recherche pour le Développement (IRD)-Institut national des sciences de l'Univers (INSU - CNRS)-Centre National d'Études Spatiales [Toulouse] (CNES)-Centre National de la Recherche Scientifique (CNRS)-Météo-France -Centre National de la Recherche Scientifique (CNRS), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Electron mobility, Materials science, business.industry, Silicon on insulator, Time-dependent gate oxide breakdown, Equivalent oxide thickness, 02 engineering and technology, 021001 nanoscience & nanotechnology, Condensed Matter Physics, 01 natural sciences, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Threshold voltage, Gate oxide, 0103 physical sciences, MOSFET, Optoelectronics, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, ComputingMilieux_MISCELLANEOUS, Leakage (electronics)
Abstract

Graphical abstractDisplay Omitted We integrated a gate-last on high-k first on planar fully depleted SOI MOSFETs.pMOSFETs reach a low threshold voltage of VTp=-0.2V.Gate-last pMOSFETS present one decade gate current gain compared to gate first ones.The use of a TiN MOCVD capping decreases the EWF by 0.2eV and degrades the reliability compared to TiN ALD.EOT down to 0.8nm with midgap TaN are obtained on HfO2 in a high-k last integration. We integrated planar fully depleted (FD) SOI MOSFETs with a gate-last on high-k first (GL-HKF) down to gate lengths of Lg=15nm and active widths of W=80nm. Such an integration scheme enables reaching for pMOSFETs a threshold voltage of VTp=-0.2V and one decade gate current (JG) gain, as well as similar hole mobility and ON-currents, compared to pMOSFETs integrated with a gate first. This approach is also benchmarked with high-k last (GL-HKL) stacks in terms of leakage, equivalent oxide thickness (EOT), effective work-function (EWF) and flat band voltage (VFB) shift under stress.

Published
2013
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10. Low temperature high voltage analog devices in a 3D sequential integration

Author

O. Rozeau, Perrine Batude, C. Fenouillet-Beranger, Gerard Ghibaudo, X. Garros, C. Cavalcante, Joris Lacord, Christoforos G. Theodorou, A. Tataridou, F. Allain, G. Romano, F. Gaillard, Laurent Brunet, T.A. Karatsori, Francois Andrieu, M. Vinet, M. Casse, N. Rambal, R. Gassilloud, J.-P. Colinge, F. Ponthenier, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP ), and Université Grenoble Alpes (UGA)

Subjects
Materials science, Negative-bias temperature instability, 010308 nuclear & particles physics, business.industry, Annealing (metallurgy), Gate stack, High voltage, 01 natural sciences, [SPI.TRON]Engineering Sciences [physics]/Electronics, Logic gate, 0103 physical sciences, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, ComputingMilieux_MISCELLANEOUS
Abstract

We built an original stackable 2.5V device on FDSOI with analog performance comparable to high temperature reference and passing the PBTI reliability criteria. In depth characterization of low temperature (LT) gate stack devices with thick EOT are investigated, enabling to draw guidelines for future optimization. This paper demonstrates the feasibility of LT high V DD analog devices, which can be used for sensor read out operation, paving the way to ultraminiaturized smart sensor arrays.

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