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LDPC codes are state-of-art error correcting codes, included in several standards for broadcast transmissions. Iterative soft-decision decoding algorithms for LDPC codes reach excellent error correction capability; their performance, however, is strongly affected by finite-precision issues in the representation of inner variables. Great attention has been paid, in recent literature, to the topic of quantization for LDPC decoders, but mostly focusing on binary modulations and analysing finite precision effects in a disaggregrated manner, i.e., considering separately each block of the receiver. Modern telecommunication standards, instead, often adopt high order modulation schemes, e.g. M-QAM, with the aim to achieve large spectral efficiency. This puts additional quantization problems, that have been poorly debated in previous literature. This paper discusses the choice of suitable quantization characteristics for both the decoder messages and the received samples in LDPC-coded systems using M-QAM schemes. The analysis involves also the demapper block, that provides initial likelihood values for the decoder, by relating its quantization strategy with that of the decoder. A new demapper version, based on approximate expressions, is also presented, that introduces a slight deviation from the ideal case but yields a low complexity hardware implementation. Index Terms--Demodulation, digital communication, error correction codes, fixed point arithmetic, quantization.

In this paper we investigate the potential gain that can be obtained in DVB-H using application layer forward error correction (AL-FEC) to perform a multi-burst protection of the transmission for improving the reception of streaming services for mobile terminals. Compared to the conventional approach with link layer multi protocol encapsulation FEC (MPE-FEC), this technique allows to increase the robustness of the DVB-H transmission not only as a function of the capacity devoted for error repair (FEC overhead), but also as a function of the number of bursts jointly encoded. The main drawback of this approach is an increase of the network latency, that can be translated into a larger service access time, and, in the case of mobile TV, a larger zapping time between channels, which is currently seen as a crucial parameter for DVB-H usability. In this paper the performance of the proposed approach is evaluated using field measurements. We evaluate the gain compared to MPE-FEC in terms of reduced IP packet error rate of the streaming service as a function of the FEC overhead and the latency introduced. Moreover, simulations have been performed to quantify feasible link margin gains. We also discuss techniques to reduce and hide the zapping time from the perception of the users. Index Terms--AL-FEC, DVB-H, IPDC, mobile TV, MPE-IFEC, multi-burst FEC, raptor codes.

Traditional reliability models are refined to handle novel scenarios called cumulative and self-clearing, which has produced more precise analysis in the mean time to failure (MTFF) calculation for memory systems. Successive single event upset (SEU) might hit the same bit without increasing the count of errors and the ratio of the MTTF of the new models versus the traditional one is a constant and independent of the size of the single-error correction protected memories.

In this paper we present the comparison of error estimators using in 3-D magnetoharmonic FE model dedicated to eddy-current testing. The first error estimator is based on the nonverification of the behaviour law. This estimator is very accurate but requires the solution of both complementary formulations. The second estimator is based on an energetic approach using the Poynting vector in conductive regions and using the variation of the magnetic energy in nonconductive regions. Both estimators are tested within an adaptive meshing procedure and the results are compared with experimental results. Index Terms--Eddy currents, error analysis, finite element methods, nondestructive testing.

An automatic electroencephalogram (EEG) artifact removal method is presented in this paper. Compared to past methods, it has two unique features: 1) a weighted version of support vector machine formulation that handles the inherent unbalanced nature of component classification and 2) the ability to accommodate structural information typically found in component classification. The advantages of the proposed method are demonstrated on real-life EEG recordings with comparisons made to several benchmark methods. Results show that the proposed method is preferable to the other methods in the context of artifact removal by achieving a better tradeoff between removing artifacts and preserving inherent brain activities. Qualitative evaluation of the reconstructed EEG epochs also demonstrates that after artifact removal inherent brain activities are largely preserved. Index Terms--Artifact removal, electroencephalogram, error correction, weighted support vector machine (SVM).

This paper analyzes the effects of roundoff noise on our ability to nonconcurrently detect and identify transient faults that corrupt state variables during the operation of a fault-tolerant discrete-time linear time-invariant (LTI) dynamic system. Our analysis leads to two decoding algorithms, i.e., one based on the Peterson-Gorenstein-Zierler algorithm and the other based on singular-value decomposition techniques. We analytically obtain bounds on the roundoff noise level (equivalently, the precision) at which both algorithms can guarantee the correct determination of the number of errors. Our simulations verify our analysis and suggest that our bounds can be very tight for certain choices of design parameters. The developments in this paper can be used to provide guidance about the design of fault-tolerant systems and have immediate implications for digital implementations of LTI dynamic systems (e.g., digital filters) because such implementations unavoidably have to deal with finite-precision effects. Index Terms--Discrete-time (DT) linear time-invariant (LTI) dynamic systems, fault-tolerant systems, Peterson-Gorenstein-Zierler (PGZ) algorithm, roundoff noise, singular-value decomposition (SVD).

This paper proposes a new class of low-density generator-matrix codes (LDGM) based on chaotic dynamical systems. The codes are designed by controlling symbolic dynamics and using linear convolutional codes. Analyzing the complex structure of chaotic systems, iterative decoding is developed. The communication performance is studied, and convergence analysis of the iterative-decoding system is presented. Finally, comparison and advantages over LDGM linear block codes in terms of encoding complexity and bit-error-rate performance are described, and possible applications of our codes are discussed. Index Terms--Chaos, encoding complexity, factor graphs, iterative-decoding analysis, low-density codes.

In this paper, a heterogeneous channel-coding scheme that combines a convolutional codec and a chaotic system into a single unit is proposed. The goal is to achieve a new coding technique that possesses the dual features of error correction and encryption. The proposed system is able to achieve reasonable error-correction performance when made to switch between optimal configurations. Its increased complexity makes it more secure relative to the conventional systems. Two additional systems that employ different chaotic switching methods are also proposed and studied. The investigation reveals the existence of tradeoffs between error-correction capability and the complexity of these systems. Index Terms--Channel coding, chaos, cryptography, error correction.

Filter banks over finite fields have found applications in digital signal processing and error-control coding. One method to design a filter bank is to factor its polyphase matrix into the product of elementary building blocks that are fully parameterized. It has been shown that this factorization is always possible for one-dimensional (l-D) paraunitary filter banks. In this paper, we focus on two-channel two-dimensional (2-D) paraunitary filter banks that are defined over fields of characteristic two. We generalize the 1-D factorization method to this case. Our approach is based on representing a bivariate finite-impulse-response paraunitary matrix as a polynomial in one variable whose coefficients are matrices over the ring of polynomials in the other variable. To perform the factorization, we extend the definition of paraunitariness to the ring of polynomials. We also define two new building blocks in the ring setting. Using these elementary building blocks, we can construct FIR two-channel 2-D paraunitary filter banks over fields of characteristic two. We also present the connection between these 2-D filter banks and 2-D error-correcting codes. We use the synthesis bank of a 2-D filter bank over the finite field to design 2-D lattice-cyclic codes that are able to correct rectangular erasure bursts. The analysis bank of the corresponding 2-D filter bank is used to construct the parity check matrix. The lattice-cyclic property of these codes provides very efficient decoding of erasure bursts for these codes. Index Terms--Factorization, paraunitary matrices, two-dimensional (2-D) codes, 2-D filter bank.

The linear discriminant analysis (LDA) technique is very popular in pattern recognition for dimensionality reduction. It is a supervised learning technique that finds a linear transformation such that the overlap between the classes is minimum for the projected feature vectors in the reduced feature space. This overlap, if present, adversely affects the classification performance. In this paper, we introduce prior to dimensionality-reduction transformation an additional rotational transform that rotates the feature vectors in the original feature space around their respective class centroids in such a way that the overlap between the classes in the reduced feature space is further minimized. As a result, the classification performance significantly improves, which is demonstrated using several data corpuses. Index Terms--Rotational linear discriminant analysis, dimensionality reduction, classification error, fixed-point algorithm, probability of error.

Typical test methods for characterizing the single event upset performance of an analog to digital converter (ADC) have involved holding the input at static values. As a result, output error signatures are seen for only a few input voltage and output codes. A test method using an input beat frequency and output code error detection allows an ADC to be characterized with a dynamic input at a high frequency. With this method, the impact of an ion strike can be seen over the full code range of the output. The error signatures from this testing can provide clues to which area of the ADC is sensitive to an ion strike. Index Terms--Analog-distal conversion, beat frequency, code error, single event upset.

An error-correction setup based on a time-bin qubit is examined for obtaining error-free entanglement distribution. Findings reveal that the performance of the error-correction setup is dependent on the amount of entanglement between polarization and time-bin.

A radiation hardened by design 32 x 36 b register file with error detection and correction (EDAC) capability is presented. The lightweight EDAC scheme (LEDAC) supports fine granularity (byte) writes, with low area and latency overhead, suitable for small, fast memories such as register file and first-level cache memory. The LEDAC scheme is described and its impact on memory efficiency and speed are quantified. The register file has been tested to be functional on a foundry 0.13 [micro]m bulk CMOS process with a measured speed over I GHz at VDD = 1.5 V. The LEDAC scheme is implemented in an external FPGA. Accelerated heavy ion testing results are also described. The experimentally measured RHBD register file SEE behavior is examined, and the proposed LEDAC scheme is shown to alleviate all soft errors in accelerated testing. Index Terms--Error detection and correction (EDAC), radiation hardening, register file.

A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for sub-100-nm SRAM memories in space environments. Because sub-100-nm SRAM memory cells can be upset by a critical charge ([Q.sub.crit]) of 1.1 fC or less, they may exhibit significantly higher upset rates than those reported in earlier technologies. Because of this, single-bit-correcting ECCs may become impractical due to memory scrubbing rate limitations. The overhead needed for protecting memories with a triple-bit-correcting ECC is examined relative to an approximate 2X 'process generation' scaling penalty in area, speed, and power. Index Terms--Error correction coding, memory fault tolerance, radiation effects.

Leading zero anticipation with error correction is a widely adopted technique in the implementation of high-speed IEEE-754-compliant floating-point units (FPUs), which are critical for area and power in multimedia-oriented systems-on-chips. We investigated a novel LZA algorithm allowing us to remove error correction circuitry by reducing the error rate below a commonly accepted limit for image processing applications, which is not achieved by previous techniques. We embedded our technique into a complete FPU definitely obtaining both area saving and overall FPU latency reduction with respect to traditional designs. Index Terms--CMOS VLSI, floating-point unit (FPU), floating-point arithmetic, leading zero anticipation (LZA).

A built-in serf-test (BIST) technique is presented for testing analog iterative decoders. Catastrophic circuit faults are detected by temporarily operating the analog soft gates in a digital mode. Self-testing operations are performed in the digital domain, thereby lowering the cost and complexity compared to alternative mixed-signal BIST approaches. A proof-of-concept CMOS integrated circuit realization of the BIST is also presented. BER measurements show that the added circuits do not interfere with the decoder's performance during normal operation. Index Terms--Error-control codes, low-density parity check (LDPC) codes, factor graphs, analog decoding, built-in self-test (BIST), message passing.

We have investigated an adaptive reliability-based iterative soft-decision Reed-Solomon decoding algorithm using belief propagation and we propose a reduced-complexity version of this algorithm. We discuss implementation and performance evaluation of these algorithms on magnetic recording channels. Index Terms--Belief propagation, iterative decoding, magnetic recording, reduced-complexity algorithms, Reed-Solomon codes, reliability-based decoding, soft-decision decoding.

The problem of creating reliable caches by using extremely unreliable technologies is examined. A novel Content Addressable Memory-based design is proposed that incorporates best-practice fault tolerant design techniques.

The study describes several rate-distortion (RD) optimal methods for slicing and unequal error protection (UEP) of packets over IP that also allows the transmission of packets with bit errors, hence giving highly accurate and efficient end results.

A new framework is proposed for multiple scalable bitstream video communications over lossy channels. Its major feature is the encoder that estimates the effects of postprocessing concealment and includes those effects in the rate-distortion analysis.

The prediction error (PE) identification methods are used for the concurrent estimation of the echo path and an autoregressive near-end signal. A new recursive prediction error (RPE) identification algorithm and three PE identification algorithms from adaptive feedback cancellation are applied to different double-talk scenarios occurring in acoustic echo cancellation.

The change detection problem in partially observed nonlinear systems with unknown change parameters, which satisfy the hidden Markov model (HMM) property, is analyzed. The results have shown that expected log likelihood (ELL) complements the existing detection statistics such as tracking error (TE) or observation likelihood (OL), which are designed to detect the loss of track that occurs due to sudden changes.

Interlayer interaction of a layered error-recovery mechanism to act against channel errors for wireless-data communications is examined in this paper. Error-control designs are implemented at two different layers in the protocol stack. A finite number of retransmissions is performed at the lower layer by a mix-mode automatic-repeat request as the primary error removal. At the upper layer, a time-out mechanism is employed, together with a packet-level coding technique, as the secondary error elimination. Performance of the proposed scheme is analyzed and verified by simulations. Through numerical experiments, we have demonstrated how the system performance is influenced by layer parameters. It is discovered that error-correcting capability needs to function at the upper layer to ensure a good system performance. Index Terms--Layered error-control scheme, retransmissions, wireless-data networks.

A novel reconfigurable sequential decoder architecture based on the Fano algorithm is presented in which the constraint length, the threshold spacing, and the time-out threshold are all run time reconfigurable. To maximize decoding performance, a maximum possible backward depth (of a whole frame) is performed. This is achieved by using shift registers combined with memory to store the information of an entire visited path. A field-programmable gate array) prototype of the decoder is built and actual hardware decoding performances in terms of decoding speeds, bit error rates (BERs), and buffer overflow rates, are obtained and comparisons made. To overcome the decoding delay that is inherent in sequential decoders, a hybrid scheme, including simple block codes and cyclic redundancy check is proposed to limit the number of backward search operations that the sequential decoder has to execute. As a result, a significant reduction in decoding delay and buffer overflow rate is achieved while maintaining comparative decoding performance in terms of BER. Index Terms--Error correcting codes, Fano decoding, hybrid decoding, field-programmable gate array (FPGA), reconfigurable design, sequential decoding.

Combining broadcast and mobile phone technologies, 3GPP2 has introduced the Broadcast and Multicast Services (BCMCS) architecture to deliver multimedia content over cdma2000 1xEV-DO wireless networks. In designing a mobile device to support multimedia broadcast services, it is important to reduce delay and energy consumption, while maintaining a tolerable level of data loss. We analyse the energy consumed by a mobile device receiving broadcast services, focusing on error recovery using the Reed-Solomon (RS) MAC-layer coding scheme. Our model is based on the energy consumed by each computational component of the RS decoder, which we determined by running the decoding process on a realistic ARM7TDMI testbed with experimentally justified cache sizes, and characterizing the energy consumption accurately with the SNU Energy Explorer. By varying the radio channel conditions, RS coding scheme and other system parameters, we determined energy-efficient cache configurations and operating ranges for each RS encoding scheme, corresponding to given levels of service quality in a video application. We have also found that significant energy can be saved by selecting a size of error control block that is appropriate to the target video quality and the channel conditions at the mobile. Index Terms--Broadcasting, code division multiaccess, energy conservation, multimedia communication, Reed-Solomon codes.

In this paper we develop cross-layer schemes combining source rate selection, power management, and error control for wireless multicast of SNR scalable video. In particular, two error control schemes are analysed and compared. The first one, type 2 hybrid ARQ/FEC, is based on incremental redundancy chosen to recover losses and provide the required level of video quality. The second one, called noncausal error control, relies on error concealment from future video data whose quality is adaptively adjusted to bring the video quality up to the desired level for all users. Our results indicate that noncausal error control can be significantly more efficient than type 2 hybrid ARQ/FEC. Index Terms--Error concealment, error control, power management, wireless video multicast.

Error concealment has a great importance within block-based video decoding systems especially for mobile transmission systems like DVB-T or DVB-H. In this paper, we propose a spatio-temporal and spatio-bi-temporal fading technique for recovering lost or erroneously received macroblock samples. For spatio-temporal fading based on a boundary error criterion obtained from temporal error concealment, either spatial, temporal, or fading of both methods is used for recovering lost image samples in one macroblock. A weighted absolute difference between well received macroblock boundary samples from the current frame and motion compensated macroblock boundary samples from the previous frame represents the boundary error. The weights for fading are interpolated from the boundary error. For spatio-bi-temporal fading, one lost macroblock can individually be recovered pel-wise spatially from the current or bi-temporally from the previous and the future frame by weighted averaging three different estimations for the lost macroblock. The simulation results have shown that for concealing erroneously received uncompressed and compressed video data the proposed methods outperform the reference methods both in subjective and objective video quality. Index Terms--Error concealment, video coding and transmission, video restoration.

In order to meet very low packet loss rate (PLR) requirements under strict delay constraints for IP based DVB services over wireless home networks (WHN), an optimized real-time transport protocol (RTP) level hybrid error correction (HEC) scheme is proposed in this paper. The scheme is compared with the Adaptive Forward Error Correction (AFEC) scheme using Reed-Solomon code. By the HEC scheme, the needed redundancy information (RI) for repairing missing packets can be minimized, especially in DVB systems with a single user. The result of quantitative analysis shows that the needed RI of the proposed scheme can even achieve the Shannon limit with only three retransmission rounds. On the other hand, our studies show that the performance of the HEC scheme is better than that of the AFEC scheme if both the average link PLR and group size are small. However, if both the average link PLR and group size are large enough, the AFEC scheme performs better than the HEC scheme. At last, the simulation results for one typical scenario are also provided in the paper to validate the result of quantitative analysis for the HEC scheme. As a result, because of the simplicity and efficiency of the proposed HEC scheme, it is a very good choice for guaranteeing the Quality of Service for DVB systems in WHN with the small group size and small average link PLR. However, for scenarios with the large average link PLR and large group size, the AFEC scheme should be taken into account. Index Terms--ARQ, DVB, forward error correction, Reed-Solomon code, wireless home networks.