Analysis and implementation of a novel leading zero anticipation algorithm for floating-point arithmetic units

Leading zero anticipation with error correction is a widely adopted technique in the implementation of high-speed IEEE-754-compliant floating-point units (FPUs), which are critical for area and power in multimedia-oriented systems-on-chips. We investigated a novel LZA algorithm allowing us to remove error correction circuitry by reducing the error rate below a commonly accepted limit for image processing applications, which is not achieved by previous techniques. We embedded our technique into a complete FPU definitely obtaining both area saving and overall FPU latency reduction with respect to traditional designs. Index Terms--CMOS VLSI, floating-point unit (FPU), floating-point arithmetic, leading zero anticipation (LZA).