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Your search keyword '"ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)"' showing total 9 results
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9 results on '"ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)"'

1. New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube™ integration

Author

J.-P. Colinge, Gerard Ghibaudo, Perrine Batude, C-M. V. Lu, F. Allain, C. Le Royer, C. Fenouillet-Beranger, M. Vinet, Sorin Cristoloveanu, C. Diaz Llorente, Sebastien Martinie, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
Materials science, Fabrication, Tunnel FET, Schottky barrier, Silicon on insulator, 02 engineering and technology, Epitaxy, 01 natural sciences, Planar, TFET, 0103 physical sciences, Materials Chemistry, Low temperature, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Quantum tunnelling, 3D integration, 010302 applied physics, SOI, business.industry, SPER, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Tunnelling BTBT, Electronic, Optical and Magnetic Materials, Threshold voltage, Optoelectronics, 0210 nano-technology, business, Voltage
Abstract

International audience; This paper reports the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) made using a Low-Temperature (LT) process designed for 3D sequential integration. These proof-of-concept TFETs feature junctions obtained by Solid Phase Epitaxy Regrowth (SPER). Their electrical behavior is analyzed and compared to reference samples (regular process using High-Temperature junction formation, HT). Dual ID-VDS measurements verify that the TFET structures present Band-to-Band tunnelling (BTBT) carrier injection and not Schottky Barrier tunnelling. P-mode operating LT TFETs deliver an ON state current similar to that of the HT reference, opening the door towards optimized devices operating with very low threshold voltage VTH and low supply voltage VDD.

Published
2018
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2. High performance low temperature FinFET with DSPER, gate last and Self Aligned Contact for 3D sequential mtegration

Author

J. Micout, M. Casse, J.-P. Colinge, L. Desvoivres, Vincent Delaye, C. Fenouillet-Beranger, S. Barraud, X. Garros, Perrine Batude, J.M. Hartmann, R. Bortolin, V. Mazzocchi, Frédéric Mazen, G. Romano, B. Mathieu, N. Rambal, V. Balan, Zineb Saghi, F. Allain, M.-P. Samson, P. Besombes, C. Comboroure, M. Vinet, Quentin Rafhay, Joris Lacord, Claude Tabone, Alain Toffoli, Gerard Ghibaudo, C. Vizioz, Benoit Sklenard, V. Lapras, L. Lachal, Laurent Brunet, Virginie Loup, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), Laboratoire des technologies de la microélectronique (LTM ), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010), and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
Materials science, Fabrication, business.industry, 020208 electrical & electronic engineering, Doping, Recrystallization (metallurgy), 02 engineering and technology, Epitaxy, Logic gate, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, 020201 artificial intelligence & image processing, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract

session 32: Process and Manufacturing Technology (32.2); International audience; For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC). The LT devices exhibit performances close to those of the High Temperature Process Of Reference (HT POR). Several techniques of SPER doping are investigated and an innovative Double SPER (DSPER) process using two amorphization/recrystallization steps, is demonstrated. This DSPER process has the advantage of doping the bulk of the S/D junctions. This work opens the door to the fabrication of high-performance LT FinFETs for 3D sequential integration.

Published
2017
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3. Self-heating assessment and cold current extraction in FDSOI MOSFETs

Author

C. Fenouillet-Beranger, Laurent Brunet, Perrine Batude, K. Triantopoulos, G. Reimbold, Gerard Ghibaudo, Mikael Casse, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Nano 2017, and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
010302 applied physics, Materials science, business.industry, Thermal resistance, Transistor, 01 natural sciences, PMOS logic, Ion, law.invention, law, 0103 physical sciences, Thermal, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Current (fluid), Thin film, business, NMOS logic
Abstract

session: Modeling and Characterization; International audience; We present an experimental study of thermal effects in thin film FDSOI MOSFETs, with a focus on the impact of self-heating effect (SHE) on drain current. We have performed thermal resistance extraction using the gate thermometry method, and calculated the resulting cold drain current (Id0), i.e. without SHE. We demonstrate that SHE is more pronounced in shorter and narrower devices without essential differences between nMOS and pMOS transistors. Our experiments show that although the temperature increases significantly in the channel due to SHE, its effect on the ION performances could be limited at operating voltage.

Published
2017
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4. Precise EOT regrowth extraction enabling performance analysis of Low Temperature Extension First devices

Author

L. Pasini, Jean Coignus, Perrine Batude, J. Micout, N. Rambal, R. Gassilloud, Claire Fenouillet-Beranger, Maud Vinet, C.-M. V. Lu, Mikael Casse, Xavier Garros, Quentin Rafhay, G. Romano, Gerard Ghibaudo, Laurent Brunet, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics, This work is partly funded by the French Public Authorities through NANO 2017 program and EQUIPEX FDSOI11, ST-LETI Alliance program and by LabEx Minos ANR-10-LABX-55-01., IEEE, ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010), and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
0209 industrial biotechnology, Work (thermodynamics), Materials science, business.industry, 020206 networking & telecommunications, 02 engineering and technology, Temperature measurement, Length measurement, 020901 industrial engineering & automation, Logic gate, MOSFET, Thermal, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Optoelectronics, Degradation (geology), Extraction (military), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract

session B2L-G: Advanced CMOS Characterization and Reliability; International audience; — 3D sequential integration requires top FETs processing with a low thermal budget (500°C). The analysis of the origin of the performance difference between Low Temperature (LT) MOSFET and high temperature standard process must take into account a potential EOT modification for short gate lengths. In this work, the difficulty of precise EOT extraction for scaled devices is observed by CV measurements and an alternative methodology using IV measurements is proposed. This methodology has been applied to an extension first integration, and the extraction accuracy is high enough to conclude to an EOT regrowth for the low temperature nFETs only. Thus, the origin of performance degradation between LT and HT, previously attributed to larger access resistance, highlights also a detrimental role of gate stack instability. The origin of this variation is attributed to oxygen ingress, through the thin extension first liner which should be suppressed by minor process optimizations.

Published
2017
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5. First SOI Tunnel FETs with low-temperature process

Author

C. Diaz Llorente, Sebastien Martinie, Gerard Ghibaudo, M. Vinet, Perrine Batude, C. Le Royer, C. Fenouillet-Beranger, Sorin Cristoloveanu, F. Allain, C-M. V. Lu, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
Fabrication, Materials science, Silicon, Tunnel FET, Silicon on insulator, chemistry.chemical_element, low temperature, Epitaxy, 01 natural sciences, tunneling, TFET, 3D sequential integration, 0103 physical sciences, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, BTBT, Quantum tunnelling, 010302 applied physics, business.industry, Electrical engineering, CoolCube, SPER, Threshold voltage, chemistry, Logic gate, Optoelectronics, business, Voltage
Abstract

session 1: Nanoscale FETs; International audience; We demonstrate for the first time the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) with low temperature (LT) processes devoted to 3D sequential integration. The electrical behavior of these TFETs, with junctions obtained by Solid Phase Epitaxy Regrowth (SPER), is analyzed and compared to reference samples (regular process at high temperature, HT). The threshold voltage (VTH) of p-mode operating TFETs shows a 300 mV reduction with similar ON state currents (wrt HT reference), opening path towards optimized devices (very low VTH & supply voltage VDD).

Published
2017
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6. High performance CMOS FDSOI devices activated at low temperature

Author

Louis Hutin, J. Mazurier, D. Barge, L. Pasini, Olivier Weber, Frédéric Mazen, F. Piegas Luce, Claire Fenouillet-Beranger, M. Vinet, Antoine Cros, E. Ghegin, B. Mathieu, S. Chhun, J. Borrel, Frederic Boeuf, Quentin Rafhay, Anthony Payet, Michel Haond, Perrine Batude, M. Casse, Fuccio Cristiano, Benoit Sklenard, Zineb Saghi, Joris Lacord, D. Blachier, J.P. Barnes, Gerard Ghibaudo, Francois Andrieu, V. Mazzocchi, N. Rambal, J. Micout, Vincent Delaye, V. Lapras, Laurent Brunet, R. Daubriac, Pascal Besson, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Équipe Matériaux et Procédés pour la Nanoélectronique (LAAS-MPN), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Nano 2017, ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), and Université Fédérale Toulouse Midi-Pyrénées

Subjects
010302 applied physics, Materials science, business.industry, 02 engineering and technology, 01 natural sciences, 020202 computer hardware & architecture, PMOS logic, CMOS, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, [PHYS.COND.CM-MS]Physics [physics]/Condensed Matter [cond-mat]/Materials Science [cond-mat.mtrl-sci], Optoelectronics, business, NMOS logic
Abstract

International audience; 3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).

Published
2016
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7. Contacts for Monolithic 3D architecture: Study of Ni$_{0.9}$Co$_{0.1}$ Silicide Formation

Author

C. Sese, F. Deprat, Fabrice Nemouchi, Ph. Rodriguez, Claire Fenouillet-Beranger, Patrice Gergaud, S. Favier, STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), ANR-11-EQPX-0010,CRGF,Lignes synchrotron françaises à l'ESRF(2011), and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
Diffraction, Materials science, Silicon, NiCo, chemistry.chemical_element, 02 engineering and technology, Substrate (electronics), silicide, 01 natural sciences, law.invention, chemistry.chemical_compound, law, Phase (matter), 0103 physical sciences, Silicide, Thermal stability, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Sheet resistance, 010302 applied physics, business.industry, Transistor, 021001 nanoscience & nanotechnology, Crystallography, chemistry, solid-state reaction, Optoelectronics, 0210 nano-technology, business
Abstract

Auteur correspondant: "philippe.rodriguez@cea.fr"; International audience; In this work, we studied the solid-state reaction between a Ni$_{0.9}$Co$_{0.1}$ film and a silicon substrate. NiCo silicide is considered to substitute Ni-and NiPt-based silicides in 3D integration in order to extend the bottom transistor thermal stability. Thanks to the combined analysis of sheet resistance data, X-ray reflectivity spectra modelling, X-ray diffraction and wavelength dispersive X-ray fluorescence analyses on Ni$_{0.9}$Co$_{0.1}$ /Si samples annealed at various temperatures, we were able to describe the phase sequence of the NiCo silicide formation.

Published
2016
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8. 3DVLSI with CoolCube process: An alternative path to scaling

Author

Maud Vinet, Thomas Signamarcheix, V. Lu, Julie Widiez, Fabien Clermidy, A. Royer, J. Mazurier, M.-P. Samson, F. Piegas-Luce, Fabrice Nemouchi, L. Pasini, J.M. Hartmann, M. Casse, F. Deprat, Laurent Brunet, N. Rambal, Maurice Rivoire, Perceval Coudrain, M. Bidaud, Ogun Turkyilmaz, Hossam Sarhan, F. Ponthenier, G. Ghibaudo, C. Euvard-Colnat, Perrine Batude, Louis Hutin, Sebastien Kerdiles, Claude Tabone, Emmanuel Josse, L. Benaissa, E. Petitprez, Remi Beneyton, Claire Fenouillet-Beranger, L. Hortemel, G. Cibrario, Pascal Besson, A. Seignard, B. Mathieu, F. Fournel, C. Bout, C. Agraffeil, S. Sollier, Michel Haond, O. Billoint, P. Leduc, O. Rozeau, Benoit Sklenard, Sebastien Thuries, Bernard Previtali, O. Faynot, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics, ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010), European Project: 619325,EC:FP7:ICT,FP7-ICT-2013-11,COMPOSE3(2013), Laboratoire d'Electronique et des Technologies de l'Information (CEA-LETI), Université Grenoble Alpes (UGA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), and ANR-10-EQPX-0030/10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
010302 applied physics, Very-large-scale integration, Materials science, business.industry, Transistor, Stacking, Electrical engineering, 02 engineering and technology, Direct bonding, Dopant Activation, 01 natural sciences, 7. Clean energy, 020202 computer hardware & architecture, law.invention, law, 0103 physical sciences, MOSFET, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, Process optimization, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Scaling
Abstract

session 5: 3D Systems and Packaging; International audience; 3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm 2 . This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.

Published
2015
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9. In situ cleaning/passivation of surfaces for contact technology on III-V materials

Author

Fabrice Nemouchi, Philippe Rodriguez, Névine Rochat, Laura Toselli, Eugénie Martinez, E. Ghegin, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), ANR-13-NANO-0001,MOSINAS,MOSFET à hétérostructure et film ultra mince d'InAs sur substrat silicium(2013), and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)

Subjects
010302 applied physics, In situ, Materials science, Passivation, Silicon, business.industry, Analytical chemistry, chemistry.chemical_element, 02 engineering and technology, Plasma, 021001 nanoscience & nanotechnology, 01 natural sciences, chemistry.chemical_compound, chemistry, X-ray photoelectron spectroscopy, Attenuated total reflection, 0103 physical sciences, Optoelectronics, Fourier transform infrared spectroscopy, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, Indium gallium arsenide
Abstract

International audience; In this work we introduce the use of physical plasmas (e.g. Ar-and He-based plasmas) in order to study the in situ cleaning (prior to metal deposition) of InGaAs layers dedicated to the realisation of self-aligned contacts. For the characterisation of cleaning efficiency, we performed surface analyses like X-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy in attenuated total reflection mode. The first results described in this work are encouraging. We have found efficient processes for removing totally or partially III-V native oxides.

Published
2015
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