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Conventional pseudomorphic high electron mobility transistor (pHEMTs) with lattice-matched InGaAs/InAlAs/InP structures exhibit high mobility and saturation velocity and are hence attractive for the fabrication of three-terminal low-noise and high-frequency devices, which operate at room temperature. The major drawbacks of conventional pHEMT devices are the very low breakdown voltage (xGa(1−x)As (x = 0.53 or 0.7) channel material plus the contribution of other parts of the epitaxial structure. The capability to achieve higher frequency operation is also hindered in conventional InGaAs/InAlAs/InP pHEMTs, due to the standard 1 μm flat gate length technology used. A key challenge in solving these issues is the optimization of the InGaAs/InAlAs epilayer structure through band gap engineering. A related challenge is the fabrication of submicron gate length devices using I-line optical lithography, which is more cost-effective, compared to the use of e-Beam lithography. The main goal for this research involves a radical departure from the conventional InGaAs/InAlAs/InP pHEMT structures by designing new and advanced epilayer structures, which significantly improves the performance of conventional low-noise pHEMT devices and at the same time preserves the radio frequency (RF) characteristics. The optimization of the submicron T-gate length process is performed by introducing a new technique to further scale down the bottom gate opening. The outstanding achievements of the new design approach are 90% less gate current leakage and 70% improvement in breakdown voltage, compared with the conventional design. Furthermore, the submicron T-gate length process also shows an increase of about 58% and 33% in fT and fmax, respectively, compared to the conventional 1 μm gate length process. Consequently, the remarkable performance of this new design structure, together with a submicron gate length facilitatesthe implementation of excellent low-noise applications.

A transparent polycrystalline diamond field-effect transistor (FET) was fabricated and measured in room temperature measurements, which reveals comparatively high maximum current density and high breakdown voltage of more than 1000 V. A harsh stress environment is proposed for simple and time-effective reliability stress measurement of the FET using a method of 50 continuous cycles of 500-V voltage stress. A 400-nm-thick Al2O3 counter-destructive passivation layer was implemented on the FET for the stress measurements. Devices with wide gate–drain length ( ${L}_\text {GD}$ ) retain their FET characteristics after the harsh stress measurements by only 50% reductions maximum current density.

Diamond has unique physical properties, which show great promise for applications in the next generation power devices. Hydrogen-terminated (C–H) diamond metal–oxide–semiconductor field-effect transistors (MOSFETs) often have normally-on operation in devices, because the C–H channel features a p-type inversion layer; however, normally-off devices are preferable in power MOSFETs from the viewpoint of fail safety. We fabricated hydrogen-terminated (C–H) diamond MOSFETs using a partially oxidized (partial C–O) channel. The fabricated MOSFETs showed a high breakdown voltage of over 2 kV at room temperature and normally-off characteristics with a gate threshold voltage $\text{V}_{\mathrm{th}}$ of −2.5–−4 V.

We fabricated and characterized black polycrystalline diamond field effect transistors. By implementing a C-H bonded channel with a wide gate-drain length up to 20 μm, a breakdown voltage of 1.8 kV was achieved, which is the highest value reported for a diamond field effect transistor (FET) to date. Several of our devices achieved a breakdown voltage/wide gate-drain length ratio > 100 V/μm. This is comparable to the performance of lateral SiC and GaN FETs. We investigated the effects of voltage stress up to 2.0 kV, and showed that the maximum current density fell to 26% of its initial value of 2.42 mA/mm before the device eventually broke down at 1.1 kV.