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High-speed data communication is becoming essential for many applications, including satellite communication. The security algorithms associated with the communication of information are also required to have high-speed for coping up with the communication speed. Moreover, the Authenticated Encryption (AE) algorithms provide high-speed communication and security services include data encryption, authentication, and integrity. The AE algorithms are available with serial and parallel architectures; among them, the Galois Counter Mode (GCM) algorithm has a parallel architecture. The Synthetic Initialization Vector (SIV) mode in the AES-GCM-SIV algorithm provides the nonce misuse protection using the GCM algorithm. Besides, reduced data throughput is provided using the AES-GCM-SIV algorithm as compared to the AES-GCM algorithm. This work introduced a parallel algorithm with re-keying and randomization of the initialization vector for high data throughput, nonce misuse protection, and side-channel attack protection. The implementation of the proposed algorithm is performed on Field Programmable Gate Array (FPGA) and it’s compared with the FPGA implementations of AES-GCM, AES-GCM-SIV, and recently introduced algorithms. The optimization of the proposed algorithm and security analysis is presented for space application using different optimizations and a combination of optimizations.

The need for high-speed communication has led the research towards designing parallel architectural algorithms for data security. The utilization of the Advanced Encryption Standard in Counter mode (AES-CTR) in cipher-based Authenticated Encryption (AE) algorithms has realized the importance of a unique Initialization Vector (IV) for data security. The Synthetic Initialization Vector (SIV) is an improvement of a generic IV used in the AES-CTR algorithm for nonce misuse and key wrapping attacks. In this work, we have proposed a new AE algorithm with parallel architecture named as Parallel Cipher-based Message Authentication Code with SIV Algorithm (PCMAC-SIV). The PCMAC-SIV AE algorithm is consists of an AES-CTR algorithm and parallel implementation of the Cipher-based Message Authentication Code (CMAC) algorithm with SIV algorithm for avoiding nonce misuse. The proposed algorithm is implemented on FPGA for showing its utility for high throughput applications. In this work, we compared the proposed algorithm implementation with the AES-GCM -SIV algorithm. The experimental results show that the throughput of the proposed algorithm show higher throughput of 1.629 Gbps for single plaintext and 13.06 Gbps for eight plaintexts.

Advance Encryption Standard (AES) is an algorithm widely used for encryption, authentication, authenticated encryption as well as in security protocols for providing security services in many modern-day applications. The primary reasons for the extensive use of AES are its stronger security and faster speed than its competitors. In the AES algorithm, different keys derived from the main key are used in encryption rounds, to provide strength to the security of the algorithm. However, in standard AES key expansion algorithm, the sub-keys are derived sequentially, that is one after other. This dependence on the previous sub-key has two problems. Firstly, the key generation cannot be parallelized, secondly, if any single sub-key is known to the attacker, all the other sub-keys, including master key, can be extracted. Also, Differential Power Analysis attack is known effective on standard AES key schedule. In this paper, we proposed a new key parallelized expansion algorithm for AES. The proposed algorithm removes the dependence on other sub-keys to provide faster speed and enhanced security. The proposed algorithm has been implemented in MATLAB software and on FPGA. The results of implementation validate that the computational efficiency of the proposed algorithm is superior to standard AES Key expansion.

The growing number of threats and attacks on communication systems has encouraged researchers to identify methods for providing security for data communication. Besides the encryption and authentication algorithms provide data security services for communication systems. However, the recent attacks on communication systems reveal that the attacks utilize the analysis of plaintext/ciphertext to breach the security of communication systems. Therefore, the plaintext should be randomized to prevent correlation between ciphertext. In this work, an algorithm is proposed for increasing ciphertext randomness in Parallel Cipher-based Message Authentication Code (PCMAC) Algorithm. The proposed algorithm utilizes the high throughput of PCMAC authenticated encryption algorithm for providing high throughput and more randomized ciphertext. The proposed algorithm is implemented for generation of Initialization Vector (IV) using the GEFFE generator and right shift operation for creating randomness in the ciphertext. The comparisons result show that the proposed implementation is more randomized as compared to the previous implementation.

The advancements in communication technology have evolved the algorithms used for communication security. Recently, the Authenticated Encryption (AE) algorithms are employed for providing security services for data communication. The Advanced Encryption Standard in Counter mode (AES-CTR) with Cipher-block Chaining Message authentication code (AES-CCM) algorithm is used for providing the data security for various applications. But the AES-CCM algorithm provides limited throughput for data communication. Therefore, in this work, new architecture is proposed for increase in throughput for provision of data security for communication application. The proposed algorithm uses the AES-CTR algorithm with the Cipher-based Message Authentication Code (CMAC) algorithm for providing AE. The proposed AE algorithm is implemented on FPGA and it’s compared with the FPGA implementation of AES-CCM algorithm. The comparison results of the proposed algorithm and the AES-CCM algorithm shows that the proposed algorithm provides improvement in the consumption of the area, processing time, and throughput. The implementation of proposed AES-CMAC AE algorithm on FPGA provides a throughput of 4.30 Gbps.

The evolution in digital communication technology has provoked the need for providing efficient security services for communication. The data security services majorly includes; confidentiality, authenticity, and integrity services. The Authenticated Encryption (AE) algorithm provides all these three services. Initially, AE algorithms were proposed with serial architecture. These AE algorithms are low throughput as compared to parallel architecture algorithms such as Galois Counter Mode (GCM) algorithm. In this work, we have presented a new AE algorithm with parallel architecture named as Parallel Cipher-based Message Authentication Code (PCMAC). The PCMAC AE algorithm is consists of Advanced Encryption Standard (AES) algorithm in Counter mode (CTR) and parallel implementation of the CMAC authentication algorithm. The proposed PCMAC algorithm is implemented on FPGA for showing its utility for high throughput applications. In this work, we compared the PCMAC AE algorithm implementation with the GCM AE algorithm implementation. The experimental results show that the throughput of PCMAC algorithm for pipelined implementation is 41.45 Gbps.