122 results on '"Wilson, Ron"'
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2. 32-bit CPUs go application-specific to beat desktop price barriers
3. LSI Logic links ASICs to synthesis
4. Megacells a challenge for ASIC designers: a big, black box of economic, simulation and testing questions opens
5. At CICC: CMOS rules; BiCMOS champions watch as pure 0.5 CMOS ASICs blaze by
6. Is in-circuit emulation finally doomed?
7. Simulate, emulate, or hope for the best?
8. Scope
9. Platform SoCs now possible
10. IP assembly represents a sea change in the design of ASICs
11. Structured ASICs walk a fine line
12. Structured ASICs strut at 90 nm -- Evolutionary moves at Altera, LSI Logic signal shift beyond FPGA-replacement market
13. Faraday platform targets Layer 4 to 7 switching -- Platform-ASIC-based design taps all-digital serdes block, metal-configured logic
14. Fujitsu finds growth in structured ASICs
15. When ASSPs go general-purpose
16. LSI Logic takes aim at PCI Express -- RapidChip structured ASICs tackle high-speed interface
17. In a shift from venerable ASIC, OEMs now embrace ASSP -- Even more than cost issues, time-to-market spurs a move that is reshaping chip arena
18. For startup, power savings start in architecture -- Parameterized hardware blocks enforce designer's energy-efficiency scheme
19. Choosing the Right Silicon Solution
20. Structured ASIC makes nest for CPU -- LSI Logic opens up a spot for cores on RapidChip
21. Fujitsu boosts structured-ASIC lineup -- ARM9 version launched, along with family that offers mix of PHY blocks
22. Choice of ASIC gate width can be boon to design -- Kawasaki expands designers' options by placing grid size, threshold voltage in play
23. Weighing design effort vs. results
24. The one-mask structured ASIC
25. ASICs and the future
26. Overview
27. IDT rolls chips to handle data flow management -- Device family allows use of double-data-rate DRAM for broadband comms data
28. Structured ASIC pioneer opts out of production -- Lightspeed adopts new model as IP provider
29. Broadcom ICs target slots in TVs, set-tops -- LNA, analog cable tuner serve OpenCable systems
30. Small Company Conjures Up 'Unique' Synthesizable IP -- Says 8051-compatible processors are portable
31. This is not your father's Hot Chips -- Annual conference mirrors industry's swing away from general-purpose processors
32. Challenges beset ASIC design in new processes -- A DAC panel concludes that the road does go forward, albeit far from smoothly
33. Teams scour RTL for design guidance -- ASIC makers use analysis tools to predict problem spots prior to synthesis
34. What is memory's role, anyhow?
35. 'Structured' ASICs arrive -- A handful of vendors offers a new breed of device-second cousin to the gate array-as way around high NRE costs, long development cycles
36. Reconfigurable computing arrays challenge DSPs -- A phalanx of programmable processors promises speedy dispatch of many algorithms
37. Are cell-based ASICs endangered?
38. Chip Express tips two series of structured ASICs -- Unlike competing products, CX5000 devices do not target FPGA conversion
39. Statistical analysis gets a 'go' for ASIC testing
40. Another road to fast ASICs
41. Drive for bandwidth leads IMEC team to rethink Carnival OFDM device -- Demodulator ASIC gains flexibility as FPGA
42. Startup puts twist on coarse-grained ASICs
43. At 90 nm, process issues push into design flows
44. A new reason for PLDs
45. Embattled gate array players pull out an ace
46. OLA greeted with caution
47. FPGA-vs.-ASIC panel reaches few conclusions
48. A physical predicament
49. VLSI supplies chips for telecom
50. Programmable devices displace ASICs for high-speed state control
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