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Flip-chip interconnects made entirely from copper are promising candidates to overcome the intrinsic limits of solder-based interconnects and match the demand for increased current densities of high-performance microprocessors. To this end, dip-based all-copper interconnects have been demonstrated to be a viable approach to form electrical interconnects by sintering copper nanoparticles between the copper pillar and pad. However, the performance of this technology is limited by residual porosity of the copper joint formed between the pillar and the pad during sintering. Moreover, the applicability of this technology in the printed circuit board industry is constrained by thermomechanical stresses that arise from the sintering. Furthermore, the compatibility of the sintering approach with standard finishing layers used as diffusion-barrier layers to provide wetting and to prevent the oxidation of the pillar and pad surfaces is unknown. In this paper, we pursue the advancement of dip-based all-copper interconnect technology. We demonstrate the robustness of dip-transfer of copper paste for varying withdrawal velocities and typical nonuniformities in copper pillar heights. Moreover, we prove the applicability of this technology with fine pillar diameters and pitches down to 10 and $20~\mu \text{m}$ , respectively. In addition, we demonstrate reduced porosities of the copper joints by applying pressure during the bonding process at 200 °C. This densification leads to interconnects with four times the shear strength and half the electrical resistance compared to interconnects formed without the application of pressure. In addition, the bonding temperature is decreased to 160 °C by applying a novel copper paste formulation, reducing the thermomechanical stress in the assembly caused by the cooling from the sintering temperature. Finally, the compatibility of this technology with EPAG, ENIG, and ENEPIG finishing layers is demonstrated, with resulting shear strength of the interconnects above 70 MPa and electrical resistance comparable to the unfinished samples.

Pastes based on copper (Cu) nanoparticles (NPs) are promising electronic-packaging materials for the attachment of high-power devices. However, the rapid oxidation of nanostructured Cu requires the use of reducing agents during processing, which makes it less suitable for attaching large-area dies (> 4 mm2). Recently, the functionalization of Cu-NP surfaces with a mixture of amines prevented oxidation, allowing for sintering without the need for reducing agents. Here we investigate the sintering mechanisms involved during die attachment using pastes of passivated Cu NPs, with particular focus on the critical role of the carrier solvents. Using 1-nonanol or 1-decanol as solvents, we first demonstrate the absence of Cu-oxide phases in the pastes after fabrication and the stability of the resulting nanostructured copper for as much as 30 min in air. By measuring the evolution of the electrical characteristics of the paste during drying and sintering, we show that electrically conductive agglomerates form among the NPs between 141°C and 144°C, independent of the carrier solvent used. The carrier solvent was found to affect mainly the densification temperature of the copper agglomerates. Because they lead to uniform sintering of the material, Cu pastes based on solvents with a low boiling point and high vapor pressure are preferable for attaching dies with area greater than 25 mm2. We show that dies with an area as large as 100 mm2 can be attached using a Cu paste based on 1-nonanol. These pastes enables the formation of temperature-resistant bonding for high-power devices using a simple and cost-effective approach.

Non-isothermal liquid evaporation in micro-pore structures is studied experimentally and numerically using the lattice Boltzmann method. A hybrid thermal entropic multiple-relaxation-time multiphase lattice Boltzmann model (T-EMRT-MP LBM) is implemented and validated with experiments of droplet evaporation on a heated hydrophobic substrate. Then liquid evaporation is investigated in two specific pore structures, i.e. spiral-shaped and gradient-shaped micro-pillar cavities, referred to as SMS and GMS, respectively. In SMS, the liquid receding front follows the spiral pattern; while in GMS, the receding front moves layer by layer from the pillar rows with large pitch to the rows with small one. Both simulations agree well with experiments. Moreover, evaporative cooling effects in liquid and vapour are observed and explained with simulation results. Quantitatively, in both SMS and GMS, the change of liquid mass with time coincides with experimental measurements. The evaporation rate generally decreases slightly with time mainly because of the reduction of liquid–vapour interface. Isolated liquid films in SMS increase the evaporation rate temporarily resulting in local peaks in evaporation rate. Reynolds and capillary numbers show that the liquid internal flow is laminar and that the capillary forces are dominant resulting in menisci pinned to the pillars. Similar Péclet number is found in simulations and experiments, indicating a diffusive type of heat, liquid and vapour transport. Our numerical and experimental studies indicate a method for controlling liquid evaporation paths in micro-pore structures and maintaining high evaporation rate by specific geometry designs.

Nanoparticle deposition by drying of colloidal suspension in thin micro-porous architectures has attracted a lot of attention in scientific research as well as industrial applications. However, the underlying mechanisms of such three-dimensional (3D) deposition are not yet fully revealed due to the complexity of the co-occurring processes of two-phase fluid flows, phase change and mass transport. Consequently, the control of 3D nanoparticle deposition remains a challenge. We use a combined experimental and numerical approach to achieve controlled 3D nanoparticle deposition by drying of colloidal suspension in two pillar-based thin micro-porous architectures. By the design of pillar layout, rectangular-spiral and circular-spiral deposition configurations are obtained globally. By varying the surface wettability, vertically symmetric and sloped nanoparticle depositions can be achieved locally. While the numerical modeling reveals the mechanisms of liquid internal flow, as well as the impact of local drying rate on nanoparticle transport, accumulation and final deposition, the experimental results of deposition configurations validate the controlling strategies. This combined experimental and numerical work provides a framework to achieve desired 3D nanoparticle deposition in thin micro-porous architectures, with a thorough understanding of the underlying mechanisms of two-phase fluid flows, phase change and mass transport. (© Elsevier 2020)., International Journal of Heat and Mass Transfer, 158, ISSN:0017-9310, ISSN:1879-2189

Efficient thermal management of large vertically stacked integrated circuits (ICs) requires a material with high thermal conductivity inside the micrometer-sized gaps between the IC dies. Such an underfill material can be obtained by adding thermally conductive filler particles at high loadings to the adhesive matrix material. However, viscosity requirements for the state-of-the-art capillary-driven filling of particle-loaded adhesives limit the particle fill fraction to values lower than those necessary to reach true percolation. Accordingly, heat transfer through the composite material is dominated by conduction through the adhesive matrix material. We propose using an alternative, sequential filling method to achieve percolation with particles down to $1~\mu \text{m}$ in diameter. The percolating thermal underfill (PTU) can be achieved by a centrifuge-assisted filling of micrometer-sized particles, followed by a backfilling of a low-viscosity epoxy with long open time acting as matrix material, and a final thermal curing step. In this paper, we present and discuss the fabrication and relevant process parameters of the PTU composite material in chip stacks with critical dimensions below $30~\mu \text{m}$ . The wet dispensing of alumina particles with a diameter distribution of 1– $15~\mu \text{m}$ is proposed for overcoming the agglomeration observed for dry particle filling. Thermal conductivities of up to 3 W/( $\hbox {m}\cdot \hbox {K}$ ) for the underfill system with a particle fill fraction of 61% were achieved, which is three times higher than those of commercially available capillary thermal underfills. Critical parameters in the formation of the percolating composite, such as the choice of filler material and its refinement, as well as the properties of the particle bed and the process parameters for the centrifugal filling, epoxy capillary backfilling, and composite curing are addressed.

The solder alloys applied in state-of-the-art flip-chip electrical interconnects are one of the main limits to improving the high power handling of this technology. To overcome this issue, the replacement of solder with interconnects purely made from copper is desirable, owing to copper's superior electromigration resistance with respect to solder. Recently, dip-based all-copper interconnects were shown to be a promising approach to form all-copper flip-chip interconnects by the sintering of Cu nano -and microparticles between copper pillars and pads. In this process, the Cu particles are applied on the pillar tips by a dip-transfer method and then collapsed onto pads, forming an assembly. Then, the assembly is sintered for 30 min in a thermal oven under constant flow of formic-acid-enriched nitrogen. After the sintering, copper joints that connect the pillars and pads are formed, resulting in the so called "dip-based all-copper interconnects". Despite the large interest raised around this approach, the requirement of formic-acid application and the long sintering time limits its scalability. In our work, we report the first example of dip-based all-copper interconnects formed by laser sintering, without the application of formic acid and with a process time of only a few seconds. These results could lead to the development of a novel ultrafast and formic-acid free assembly technique of all-copper flip-chip interconnects.

Flip-chip interconnects made entirely from copper are needed to overcome the intrinsic limits of solder-based interconnects and match the demand for increased current densities. To this end, dip-based all-copper interconnects are a promising approach to form electrical interconnects by sintering copper nanoparticles between the copper pillar and pad. However, the remnant porosity of the copper joint formed between the pillar and the pad limits the performance of this technology. Moreover, the applicability of this technology in the printed circuit board (PCB) industry is endangered by thermo-mechanical stresses that arise during the sintering and by the unknown compatibility with standard finishing layers used to prevent the oxidation of the copper. This work reports three main advances in dip-based all-copper interconnect technology. First, a reduction in the porosity level of the copper joint is obtained by application of pressure during the bonding. Second, a decrease of the bonding temperature to 160 °C is achieved. Third, the compatibility of this technology with standard finishing layers is demonstrated.

Flip chip interconnects purely made out of Cu, so-called all-Cu interconnects, have the potential to overcome the present current capacity limit of state-of-the-art solder based interconnects, while meeting the demand for ever decreasing interconnect pitches. Parasitic effects in solder based interconnects, caused by interdiffusion of various metals, are mitigated in all-Cu interconnects. In this work, all-Cu interconnects were formed by the use of low temperature and pressureless sintering of Cu nanoparticles. Thereby, a Cu paste material was applied between the Cu pillars of a silicon chip and the Cu pads on a silicon substrate by a dip transfer method. The electrical and mechanical properties of sintered Cu were characterized on films of the same Cu pastes. The porous films resulted in 4.4 times higher electrical resistivity and one order of magnitude reduced mechanical stiffness and tensile strength compared to bulk Cu. All-Cu interconnects with a diameter of 30 µm and a pitch of 100 µm were formed with an optimized Cu particle distribution and sintering procedure. Resistances down to 1.7 ± 0.5 mO were measured for these all-Cu interconnects which is comparable to solder based benchmark interconnects. However, the porosity of the sintered Cu interconnect results in lower shear strength compared to the solder benchmark.

Copper is the metal of choice for electrical circuits in electronics. It is lower in cost than silver and offers excellent electrical properties like low electrical resistivity and electromigration resistance. Physical vapor deposition and wet-chemical etching or electroforming are the standard processes used to deposit and pattern copper on silicon and in printed-circuit-board technology. Recently, copper inks and pastes have become available for the printing of copper films, with the potential outcome of lowering the production cost beyond that of the established processes. Furthermore, the printing processes are compatible with role-to-role fabrication, and are hence attractive for flexible electronics. In this study, a bi-modal copper paste containing nano- and micro-particles is transferred in a relief printing process by using silicon stamps. It was possible to demonstrate electrical conductive tracks with a linewidth down to 8 μm. The spacing between neighboring tracks is related to their width and can be as low as 10 μm. It was possible to achieve a sheet resistance of less than 8 mΩ sq–1 after formic-acid-assisted sintering at 180 °C. The low sintering temperature enables the direct placement of electronic components without additional soldering and thus saves time and production costs.