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This paper presents the modeling of the electrothermal and electromagnetic behavior in SiC-based multi-chip power modules. The proposed approach is based on a macromodeling technique and is applied to a realistic case-study. Preliminarily, the assembly under analysis was experimentally characterized to estimate its parasitics due to electromagnetic interactions. Extremely fast and efficient electrothermal simulations were then performed in a SPICE-like environment. Parasitics and nonlinear thermal effects were accounted for in simulations at high switching frequencies. Results demonstrate that such an approach can be successfully adopted in the design flow of power modules in any device technology.

In this paper, an advanced electrothermal simulation strategy is applied to a 3.3 kV silicon carbide MOSFET power module. The approach is based on a full circuital representation of the module, where use is made of the thermal equivalent of the Ohm’s law. The individual transistors are described with subcircuits, while the dynamic power-temperature feedback is accounted for through an equivalent thermal network enriched with controlled sources enabling nonlinear thermal effects. A synchronous step-up DC-DC converter and a single-phase inverter, both incorporating the aforementioned power module, are simulated. Good accuracy was ensured by considering electromagnetic effects due to parasitics, which were experimentally extracted in a preliminary stage. Low CPU times are needed, and no convergence issues are encountered in spite of the high switching frequencies. The impact of some key parameters is effortlessly quantified. The analysis witnesses the efficiency and versatility of the approach, and suggests its adoption for design, analysis, and synthesis of high-frequency power converters in wide-band-gap semiconductor technology.

In this paper, an enriched version of a VHDL-AMS tool devoted to electro-thermo-mechanical simulations is presented. The major improvement consists in the evaluation of the vertical displacements of the layers in the domain. As a case study, the mechanical deformations and stress in a principle structure emulating a state-of-the-art multi-chip SiC-based power module are thoroughly examined. By means of the proposed approach, the vertical displacements were quickly investigated and quantified in a typical electro-thermo-mechanical stress test scenario.

The relevant cooling action ensured by the thermal vias in PCB-based power circuits allows extending the operating conditions of the semiconductor devices. However, to properly drain off the power dissipated in the active regions, efficient thermal designs must be developed. To further reduce the devices operating temperature, a strategy to take advantage of the unexploited PCB areas surrounding the device footprint is proposed and discussed in this paper. The analysis is carried out by means of 3-D FEM thermal simulations performed in the COMSOL Multiphysics environment. This investigation is devoted to providing guidelines for an optimum design of thermal vias by accounting for their main geometrical features.

This article presents the detailed thermal analysis and modeling of multichip power modules (PMs). For the first time, a fair thermal comparison between the widespread single-sided cooled (SSC) technology and the innovative double-sided cooled (DSC) one is presented. The latter solution emerges among all packaging techniques due to its improved electrical performances and mechanical reliability. The investigation is carried out using 3-D finite-element method thermal simulations automated by an in-house routine. The PMs under test are thoroughly studied in a wide range of boundary conditions (BCs) in order to support the choice of an appropriate cooling strategy and the comprehension of the heat spreading (HS) effect occurring in such domains. In addition, attention is paid to dynamic behavior. Thermal modeling strategies are then proposed and discussed. As the main finding, no relevant thermal discrepancies were observed in the two PM technologies. In most of the BCs, the SSC PM enjoys an enhanced HS effect leading to a better thermal behavior with respect to the DSC counterpart, the adoption of which is justified only in the presence of excellent cooling systems.

This paper investigates the thermal vias (TVs) design in PCB-based power circuits; the study aims to experimentally validate an analytical model for the quick estimation of the TVs thermal resistance. Such a model efficiently supports the identification of the optimum PCB layout and allows avoiding time-demanding numerical simulations and/or nontrivial measurements. An experimental procedure performed on ad hoc PCB samples is exploited to confirm the model accuracy. The results of repeated measures and their statistical distribution are reported and discussed along with the model predictions.

This work proposes analytical thermal models for through-PCB thermal vias and passive heat-sinks, two key components of the overall junction-to-ambient thermal resistance in modern integrated power electronics circuits based on advanced wide-band-gap semiconductor technology. The proposed models aim to support the thermal design of PCB and cooling system by the quick estimation of their thermal resistances. The models are scalable in that they fully include the geometry, material properties and boundary conditions. As a case-study, reference is made to the cooling of last generation gallium nitride HEMTs in SMD type package. Here, only the static behavior is considered. The models accuracy is evaluated by comparison with accurate FEM simulations performed exploiting the commercial software COMSOL Multiphysics aided by a MATLAB routine developed by the authors.

This paper presents a comparative study of different approaches and solutions to the cooling of new type highly compact flat packages for gallium nitride (GaN) transistors. The focus here is on an inverter intended for hybrid and full-electric transport applications, where optimization of the gravimetric power density is paramount. As a case-study, a 3-level active neutral point clamped (aNPC) bi-directional inverter-rectifier topology is considered. The outcomes of the investigation are manifold: optimum design of thermal vias is considered; it is highlighted that the use of a graphene layer just underneath the chip can help reduce the temperature gradient between chip and PCB and can also improve heat-conduction in subsequent layers of the assembly, by enabling a better exploitation of lateral heat-flow possibilities, too; the benefit of using a soldered DCB substrate to assist heat removal from the vias towards the heat-sink is quantified for different materials of the insulating layer (ceramic).

In this paper, an experimental and numerical study of the electrical ruggedness in double-sided cooled power modules is presented. In particular, the analysis focuses on the role of the spacing between substrates, which are commonly kept distant to avoid electrical failures like partial discharge and dielectric breakdown. To this aim, many double-sided cooled assemblies were manufactured and then tested by monitoring the leakage current due to high voltages applied to the terminals. Two failure mechanisms are recognized and characterized. To provide an explanation of the counterintuitive measurement outcomes, 3-D FEM electrostatic simulations were performed on the power module samples in the COMSOL Multiphysics environment.

This paper focuses on the thermal investigation of SiC-based power modules with the purpose to support their design in terms of cooling techniques and material choices. The analyses are aimed to compare the widespread single-sided cooling technology with an innovative double-sided cooling variant. The comparison is carried out by simulating extremely detailed 3-D FEM structures realized through an in-house routine developed to automatically perform extensive simulation sessions. First, the effects of convective boundary conditions on the thermal resistance and the heat spreading mechanism are thoroughly examined in both technologies; then, the role of ceramic layers composing the power module substrate is evaluated and quantified in terms of thermal performances.

This paper investigates the effect of negative gate bias voltage (V gs ) on the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs. The device's ability to withstand energy dissipation during avalanche regime is a connoting figure of merit for all applications requiring load dumping and/or benefiting from snubber-less converter design. The superior material properties of SiC material means that SiC MOSFETs even at 1200V exhibit significant intrinsic avalanche robustness.

This paper presents an in-depth investigation into the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs comprising of functional as well as structural characterization and the corresponding underlying physical mechanisms responsible for device failure. One aspect of robustness for power MOSFETs is determined by its ability to withstand energy during avalanche breakdown. Avalanche energy (EAV) is an important figure of merit for all applications requiring load dumping and/or to benefit from snubber-less converter design. 2D TCAD electro-thermal simulations were performed to get important insight into the failure mechanism of SiC power MOSFETs during avalanche breakdown.

Beyond their main function of high-frequency switches in modulated power converters, solid-state power devices are required in many application domains to also ensure robustness against a number of overload operational conditions. This paper considers the specific case of 1200 V SiC power MOSFETs and analyses their performance under three main transient regimes at the edge of and out of their Safe Operating Area: unclamped inductive switching led avalanche breakdown; short-circuit; operation as current limiting and regulating devices. The results presented highlight both inherent major strengths of SiC over Si and areas for improvement by tailored device design. The paper aims to contribute useful indications for technology development in future device generations to better match widespread and varied application requirements.

The behavior of Silicon Carbide Power MOSFETs under stressful short circuit conditions is investigated in this paper. Illustration of two different short-circuit failure phenomena for Silicon Carbide Power MOSFETs are thoroughly reported. Experimental evidences and TCAD electro-thermal simulations are exploited to describe and discriminate the failure sources. Physical causes are finally investigated and explained by means of properly calibrated numerical investigations, and are reported along with their effects on devices short-circuit capability.

Relatively recently, SiC power MOSFETs have transitioned from being a research exercise to becoming an industrial reality. The potential benefits that can be drawn from this technology in the electrical energy conversion domain have been amply discussed and partly demonstrated. Before their widespread use in the field, the transistors need to be thoroughly investigated and later validated for robustness and longer term stability and reliability. This paper proposes a review of commercial SiC power MOSFETs state-of-the-art characteristics and discusses trends and needs for further technology improvements, as well as device design and engineering advancements to meet the increasing demands of power electronics. 2016 Elsevier Ltd. All rights reserved.

This work aims to present an investigation on short-circuit (SC) failure behaviour of SiC Power MOSFETs due to the onset of thermal runaway. As inferable from experimental outcomes, it is related to the formation of hotspot, whose exact location is mainly unpredictable and dictated by device structure and design parameters non-uniformities. TCAD simulations were performed to examine the impact of some parameters mismatch on hotspot formation and failure occurrence.