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Operational Transconductance Amplifiers (OTAs) are the most pivotal blocks in analog circuits and systems. With the emersion of catastrophic short channel effects for Complementary Metal Oxide Semiconductor (CMOS) transistors at deep nanometric regime, the microelectronics scientists have focused on designing ultra-miniature OTAs based on non-silicon materials. During the last few years, Gate-All-Around Carbon Nanotube Field Effect Transistors (GAA-CNTFETs) with astonishing electrical and physical properties have drawn extensive attention of nanoelectronics researchers as a potential platform to represent high-performance nanoscale OTAs. In this regard, this work aims to propose an ultra-miniature ultra-wideband OTA based on the 10 nm GAA-CNTFET technology node. The proposed OTA benefits from the ballistic transport operation of the GAA-CNTFET transistors at ultra-scaled dimensions which provide a superior bandwidth (2.88 GHz) along with suitable power consumption (44.8 $$\upmu$$ W). The proposed OTA shows a 64.5 dB open-loop gain and a 59 dB common-mode rejection ratio at a 1 V supply voltage. Moreover, due to the utilization of the indirect feedback compensation method, the proposed GAA-CNTFET-based OTA presents an appropriate phase margin (61 $$^{\circ }$$ ) with a smaller compensator capacitor. With the mentioned performance metrics and occupying only 0.198 $$\upmu {\mathrm{m}^{2}}$$ physical area, the proposed GAA-CNTFET OTA has the potential to be considered as a replacement for nanoscale CMOS-based OTAs.

In this paper, we present two new logic schemes to implement full adder cell using XOR-XNOR and NOR gates. Gate diffusion input (GDI) and modified GDI (MGDI) cells help to design low power circuits...

In recent years, usage of novel non-Si materials as the gate channel region in next generation of field effect transistors, including carbon nanotubes, have been in the spotlight of nanoelectronics research due to astounding carrier transport and I-V characteristics. These properties make them a highly suitable platform in modern radio frequency applications. Therefore, the aim of this work is to design and investigate the performance of current-starved and skewed ring oscillators based on ballistic carbon nanotube transistors (CNTFETs). In this work, we have utilized wrap-gate structure to have a better electrostatics control and mitigate the gate leakage current. All the CNTs in both n-type and p-type transistors have 0.9 nm diameter and an array of CNTs have been exploited in the gate region to achieve low-power and high-performance operation. The simulation results demonstrate that the proposed CNTFET-based ring oscillators have sub-100μW power consumption (Pcurrent-starved = 6.011 μW, Plow-skew = 67.2 μW, and Phigh-skew = 23.5 μW) along with wide frequency tuning range (fcurrent-starved = 0.202 GHz − 1.205 GHz, flow-skew = 0.361 GHz − 2.137 GHz, and fhigh-skew = 0.335 GHz − 2.38 GHz) which are suitable for internet of thing (IoT) devices operating from 100 MHz to 5.8 GHz. Finally, based on the simulation results, we have emphasized that the CNTFET-based skewed ring oscillators are suitable for high-speed purposes, while the CNTFET-based current-starved ring oscillator is recommended for low-power and high-swing applications.

In this paper, a robust carrier recovery loop for high dynamic and weak signals in GPS receivers is proposed. To achieve optimal tracking performance at synchronization loops, different methods are investigated. Since phase jitter sources are identified at the receiver, suitable controller coefficients are calculated and used in carrier and timing recovery loops. This improvement induces higher speed and lower variance of jitter in acquisition and tracking modes, respectively. Furthermore, this simple design can obviate the need of large digital filters or complex circuits such as wavelet de-noising filters in the loop. To extend the linear range of the phase estimator, phase unwrapper unit is used which can improve loop tracking ability and resolve Kalman filter difficulties. To compensate the cycle-slip phenomenon, a novel recursive algorithm is introduced which causes better performance for low CNR signals and high dynamic environments. Simulation results show the effectiveness of the proposed architecture for different Doppler rates and CNRs. Moreover, the results indicate good matching between fixed-point FPGA implementation and floating-point simulation.

This work reports on the optimization of factors affecting the performance of InSb-based quantum-well (QW) laser. The QW laser designs and its parameters are improved using physical modeling and simulation. The designed QWs can emit light at a range of 5.40–6.48 µm. The InAlSb is used as barrier between InSb active region and InAlAs cladding layer. To optimize the laser performance, the influence of Al concentration variation in barrier and cladding layers, as well as thickness of the active region on the QW, is investigated. The optical and electro-optical characteristics are compared with related experimental results. The output power, spontaneous emission and peak intensities versus injected current of the proposed QW structures demonstrate good similarity with similar reported grown samples. It is demonstrated that Auger recombination is truly reflected in the proposed QWs.

The memristor (memory resistor) is the fourth passive element of electrical circuits having dynamic resistance with the ability to keep the last level of resistance even after the power supply is interrupted. This article presents a simplified mathematical function with the capability to define the threshold conditions for memristor operation and a new pattern to describe and modeling of the unwanted current leakage in the subthreshold situation for HP TIO2 memristor. These special features provide a more realistic scheme of TIO2 memristor behavior. Our proposed mathematical function is adaptive with the majority of previous prominent works around the ionic drift modeling of HP memristor and is easy to use in SPICE simulators so can be utilized in a wide range of designs and applications. To our best known this is the first research paper in which the issue of subthreshold current leakage modeling of the memristor is addressed.

Content addressable memory (CAM) as a high-speed memory structure plays an important role in a wide variety of applications, particularly in network routers however its high-power consumption has been a complex challenge for designers and manufactures as well. Fortunately, exploiting memristors as non-volatile memory elements in the structure of CAM in recent years has resulted in a significant reduction in its power consumption and creates a promising outlook for the future of CAM. This paper presents novel architectures of memristor-based CAMs with considerable optimization in terms of the physical layout area, power consumption, and simplicity of performance in comparison with previous similar works. Our main goal is to provide more favorable options for the manufacturers in near future.

A novel full-swing, low-power and energy-aware full adder using hybrid logic scheme is presented in this paper. At first, a new energy-efficient 10T XOR-XNOR cell is designed by modifying inverter and pass transistor based 3T XOR-XNOR gates combined with a feedback loop. The performance of this new cell is compared with some reported ones and then, using this new cell and two other modules, a novel full adder circuit is proposed and evaluated in TSMC 0.18m CMOS process technology. Post-layout simulations using Cadence Virtuoso tool showed 33%74% and 35%81% improvement in terms of power consumption and power-delay product (PDP), respectively, compared with some well-known counterparts in the literature. Furthermore, high-performance claim of our proposed full adder cell is verified through the process, voltage and temperature (PVT) variations' simulation of the adders. Finally, implementation of different full adders in 4-bit ripple carry adders (RCAs) proved our new design has high performance in the aspects of power dissipation and PDP.

As the most attractive phosphors, the enhancement of the optical properties of single crystalline alkali halides such as KCl using different types of dopants was approached. Pure and doped KCl single crystals were grown using Czochralski method. Different activators such as Ag, In, Mn, and Sn ions were employed to enhance the optical properties of grown KCl single crystals. The structure of the single crystalline samples was investigated through X-ray diffraction (XRD). The optical properties of the samples were studied by employing UV–vis spectroscopy, photoluminescence (PL) analysis and ion beam-induced luminescence (IBIL), to confirm the incorporation of dopants into the host lattice. In the PL spectra of the samples, two UV and near UV emission lines and one red emission line were detected in the PL spectrum of the pure sample at 357 nm, 420 nm and 697 nm respectively that have not been reported before. Dopants led to the change in the intensity and position of the peaks. The peaks at 420 nm and 697 nm in the doped samples were shifted towards shorter wavelengths and a 500 nm emission was emerged due to impurities. The IBIL analysis proposed the violet color center for the Sn and Mn doped samples. These peaks turn the KCl single crystals into attractive phosphors.

Detection of small targets in an infrared (IR) image with high reliability is very important for defence systems. Small targets in an IR image are defined as salient features which attract the attention of human visual system. In this study, a robust method for detection of small targets in an IR image is proposed based on HV attention. In this method, first, the Gaussian-like feature maps are extracted from the original image. Then, saliency maps (SMs) are created based on pulsed discrete cosine transform, in which the target is salient and background clutter is suppressed. Finally, to increase the contrast between target and background clutter and to raise robustness of this method against false alarms, SMs are fused adaptively. Experiments are carried out on the data set including real-life IR images with small targets as well as various and complicated backgrounds. Qualitative and quantitative assessments show that the proposed method can detect small targets in IR image with high reliability and is more effective compared with other methods based on HV attention. Therefore, it can be used in many applications for detection of small targets in IR image with minimum false alarms.

Mitral valve stenosis (MS) is one of the most prevalent heart valve diseases. The mitral valve orifice area (MVA) is a reliable measure for evaluating the MS severity. This measure is typically obtained by applying planimetry methods to the echocardiography video frames in a parasternal short axis view (PSAX). From the diagnostic perspective, the most proper frame for measuring the MVA is the mid-diastole frame. Since manual methods for localizing this frame within a sequence of recorded echocardiography frames are time-consuming and user-dependent, a novel three-stage approach is proposed. Firstly, the mitral valve orifice (MVO) region is detected automatically for each frame using the Circular Hough transform (CHT) leading to a lower computational cost and an increased accuracy. Secondly, for each of the detected MVO regions, a data dimensionality reduction (DR) method is applied to map it into a single point in a two-dimensional (2D) space. Finally, a curve is generated based on Euclidean distances between consecutive points in the 2D space. The curve analysis allows for the detection of the location of the mid-diastole frame. The proposed algorithm was validated using echocardiographic video sequences collected from 11 different participants including 7 individuals diagnosed with mitral valve stenosis and 4 control non-stenosis individuals. The mid-diastole frame location estimated by an expert cardiologist was used as the gold standard for assessing the evaluation results. The performance of different DR methods including the linear principal component analysis (LPCA) and the kernel PCA (with a polynomial or a Gaussian kernel) was evaluated. The PCA with Gaussian kernel produced the best results with the average difference between the proposed method and the gold standard equal to 0.57 frames in MS and 0.50 frames in non-MS cases.

The emergence of heterogeneous computing systems has been accompanied by serious design issues. Being a highly influential factor on performance in these systems, application scheduling is one of the major design considerations. In this paper, we propose a new critical path-oriented list scheduling heuristic algorithm called Communication-Intensive Path on a Processor (CIPOP) for heterogeneous computing environments. It is a modification of the well-known CPOP algorithm that presented the idea of scheduling the most costly entry-exit path of tasks, commonly known as the critical path, on a single processor. Generally, this processor selection strategy has different potential impacts on computation and communication costs along a selected path in the produced schedule. However, these probably different effects are not considered in the common definition of a critical path. Differentiating between these two types of costs, the proposed algorithm introduces a novel performance-effective definition for a critical path that is compatible with this processor selection strategy. CIPOP has a time complexity the same as that of the state-of-the-art list scheduling heuristic algorithms, which is of the order O(v2.× p) for v tasks and p processors. The conducted comprehensive experiment based on a wide variety of randomly generated application DAGs demonstrates the performance improvement of the proposed algorithm.

in this paper, an optimized hardware for Convolutional Neural Networks with the purpose of implementation on embedded vision systems is presented. This design method is meant to be implemented with minimum resource consumption on a low-end hardware platform. We propose an architecture on a Z-turn evaluation board featuring a Xilinx Zynq-7000 system on chip (SoC). All computations in this architecture are optimized as 8-bit. Also, the accelerator has a frequency of 160 MHz and power consumption of 1.77 watts which leads to a performance of 40.96GOP/s, using only 134 computing units and 601 KB of internal memory. So we can claim that the acceptable speed and low power and low area consumption of this architecture make it an ideal choice for portable and embedded CNN applications.

This paper presents a compact hybrid architecture of memristor-based Ternary Content Addressable Memory (mTCAM) along with a novel simplified method for programming memristors in CAM. In addition to simplifying the writing and searching operations, the proposed structure has led to a significant reduction in layout area. Memristor, as fourth fundamental passive circuit element, has a dynamic resistance level with the capability of maintaining the last level of resistance even after disconnecting the power supply. The CAM with two types of forms (Binary and Ternary) is a well-known storage structure with a variety of applications, especially in network routers. The most significant advantage and challenge of CAM are high speed and high power consumption respectively.

Nonlinear contact between tip and sample in tapping mode atomic force microscopy (AFM) systems induces higher harmonics, which may be useful for extraction of some characteristics of the sample. In this paper, a new efficient method for implementing multichannel digital lock-in technique is presented, which is able to measure the amplitude and phase of multiple modulated frequency signals. In order to solve the two most important problems in AFM systems, which are resolution and cost, previous multichannel lock-in amplifier methods are investigated and an improved algorithm for amplitude and phase extraction using fast Fourier transform is developed. In addition, we propose a novel multichannel digital lock-in algorithm including an $N$ -slow digital filter and a multichannel direct digital synthesis block for generating reference signals. We achieve optimal noise reduction using the appropriate decimation filters prior to harmonic extraction. This modification results in a significant hardware reduction in implementation compared with classical designs. Since the precision of the design is sensitive to the sampling frequency, we perform the suitable sampling rate conversion using fractional delay and decimation filters, which enhance the accuracy and noise resiliency of the designed architectures. Experimental results prove the efficiency of the proposed method in multiple modulated frequencies extraction. Also, FPGA implementation results show that the proposed architecture is superior to previous structures, especially in the aspect of area.

Synchronisers are a significant part of digital communication receivers since they are used to estimate the received signal timing. Among these synchronisers, non-data-aided (NDA) or blind synchronisers are even more important due to bandwidth efficiency. In this study, a different approach is investigated to derive new feedforward NDA timing estimators based on Newton algorithm. Two novel estimators with four and two samples per symbol are presented and compared with traditional timing estimators, respectively. One of the main advantages of the second proposed estimator is the ability to control the loop gain automatically. This ability improves the convergence speed and robustness of the design. Simulation results show that the presented estimators outperform the conventional estimators over a noisy channel, especially at small excess bandwidth and low signal to noise ratio.

In this paper, an efficient all-digital demodulator in digital communication receivers is proposed and implemented on a reconfigurable hardware platform in order to compensate timing and carrier phase offset. In the proposed design, a feedforward architecture which has better stability and performance than traditional feedback architectures is used in the timing synchronization loop. To mitigate the problem of oversampling rate of feedforward synchronizer, an innovative parallel demodulator architecture is presented which is optimized for high speed transmissions. This proposed architecture results in asynchronous data sampling where there is no need to adjust sampling rate of the analog to digital converter with an external feedback. To achieve good stability conditions in the presence of loop delay in carrier recovery loop, an appropriate compensation method using a novel Smith predictor is utilized. Since the delay compensation technique is applied, the proposed architecture is well suited for pipelined VLSI implementations. The proposed architecture is used to implement M-QAM digital communication receiver on a Xilinx Virtex-7 FPGA platform achieving a clock rate of 612 MHz. Implementation results show that our design has a good performance for different modulation orders as well as excellent robustness against loop delays and variations in the loop.

This paper presents a new way of image encryption based on biologic DNA sequence operations and Cellular Neural Network (CNN), which consists of three processes; bit-substitution, key stream generation process, and diffusion process. Firstly, a plain-image is equally divided into four sub-images and a DNA sequence matrix of each sub-image is obtained. Then we employed the hamming distance (between DNA sequences) and DNA sequence operation to encrypt each DNA sub-image. The second process is a pseudo-random key stream generator based on Cellular Neural Network. The parameters and initial conditions of the CNN system are derived using a 256 bit-long external secret key by applying some algebraic transformations to the key. The original key stream is related to the plain-image which increases the level of security and key sensitivity of the proposed algorithm. In the final process, we use the chaotic sequences generated by CNN to modify the pixel gray level values and crack the strong correlations between adjacent pixels of an image simultaneously. This feature will significantly increase plaintext sensitivity. Moreover, in order to reach higher security and higher complexity, the proposed method employs the image size in key stream generation process. The experimental results reveal that the new image encryption algorithm has the advantages of large key space (2256), high security, high sensitivity (Number of Pixels Change Rate: NPCR >99.6201 %, Unified Average Changing Intensity: UACI >33.5065 %), and high entropy (> 7.9975). Also, the distribution of gray level values of the encrypted image has a semi-random behavior.

Detection of dim small targets in infrared (IR) images with high reliability is very important in defence systems. In this study, a new method is introduced based on human visual system and saliency maps fusion to detect the small target in IR images with high reliability. By using the static and motion saliency maps fusion, emphasizing the obtained saliencies from one method to another and applying the information and benefits of all maps in the saliency map fusion, this method suppresses the background clutter and noise with high reliability, makes the target more prominent and finally increases the contrast among them. The experiments are carried out on some real-life data of IR images containing the moving target. The obtained results show the efficiency and robustness of the proposed method so that this method improves the target signal to the background noise and clutter and increases the contrast between them and also detects the small target in IR images with low false alarm rates and high reliability.

This paper is a cryptanalysis of a recent proposed image encryption algorithm based on chaotic functions. The cryptosystem is composed of two-stage permutation and one-stage substitution for encryption of the gray scale plain-image. However, by applying chosen plaintext attack which is described in this paper, we show that all the secret parameters can be revealed. In addition, some other security defects of the cryptosystem are also highlighted. Both mathematical analysis and experimental results confirm the feasibility of this attack. As a result, the cryptosystem in this structure cannot be recommended when we need a higher level of security.

In this paper, an efficient implementation of high throughput Digital Video Broadcasting (DVB) system based on the Orthogonal Frequency Division Multiplexing (OFDM) modulation for terrestrial links is proposed. The proposed architecture uses an improved optimization methods to obtain high speed system. To verify the efficiency of this system a DVB-T simulator in MATLAB matched with European Telecommunications Standards Institute (ETSI) is used to investigate the hardware design performance. The joint simulation of Xilinx ISE and MATLAB was performed including information framing, channel coding, and modulation. Also, a systematic design procedure based on FPGA for the proposed DVB-T system is presented and the results are reported. Hardware implementation results demonstrate the effectiveness of the proposed system and show that there is a good match between fixed-point implementations and floating-point simulations, while the high-throughput architecture is achieved in hardware implementation using the speed optimization methods in the design.

In the realm of VLSI circuits, addition and multiplication are the most pivotal operators in arithmetic units. In this regard, this work aims to propose an energy efficient 4:2 precise compressor utilizing 10 nm wrap gate CNTFET technology. The proposed compressor is constructed from 2 hybrids 14-transistors full adders. The proposed Gate All Around (GAA) CNTFET based full adder employs a hybrid XOR/XNOR logic structure to lower the transistor count and power consumption. After performing rigorous simulations, we have demonstrated that the proposed GAA CNTFET based full adder and 4:2 compressor depict 175.3 nW and 308.5 nW power consumption respectively along with superior propagation delay response (4.4 ps and 10.57 ps respectively) at a 0.5 V nominal supply voltage. Moreover, the proposed designs occupy a lower layout area (0.195 μm2 and 0.43 μm2 for the proposed full adder and 4:2 compressor respectively) compared to the other counterparts. Our results accentuate the application of the proposed GAA CNTFET based 4:2 precise compressor for ultra miniature microprocessing systems.

This work provides a comparison of the changes in performance of a gate-all-around GAA carbon based tunnel field effect transistor p-i-n TFET and metal-oxide-semiconductor field effect transistor n-i-n MOSFET with respect to insulator thickness $\pmb{t_{ox}}$ values. The performance variations are prominent in the p-i-n TFET than n-i-n MOSFET structure; $\pmb{g_{d}}$ and $\pmb{g_{m}}$ are significantly degraded with $\pmb{t_{ox}}$ . The results are considered based on current spectrum on energy band diagram of the device in detail. Due to 1D quantum transport characteristics of CNTs the results could be applicable to any device with the same structure including 1D nanowire FET.

Physical unclonable functions (PUFs) are powerful security primitives that provide cheap and secure solutions for security-related applications. Strong PUFs provide a large set of challenge-response pairs (CRPs) and are suitable for device authentication. Weak PUFs produce a small number of CRPs and can be used for key extraction. In this paper, we propose a novel method to enhance the CRP set of traditional ring oscillator-based PUFs (RO-PUFs). RO-PUFs are one of the most reliable types of PUFs and the best fit to implement on the field-programmable gate arrays. To the best of our knowledge, our method provides the maximum number of CRPs compared with the state of the art. In addition, the number of response bits that can be extracted by our method for each challenge is $n-1$ times more than the state of the art, where $n$ is the number of ROs. The large number of response bits results in the authentication of more devices and generation of more keys. Evaluation of the PUF responses produced by applying our method shows a significant improvement in unpredictability and randomness compared with the related works. Moreover, we show that the responses are unique and reliable.

For a carbon nanotube field effect transistor (CNTFET) the ballistic I-V characteristics have been investigated theoretically with respect to ambient temperature for both the p-i-n tunnel FET (TFET) and n-i-n metal-oxide-semiconductor FET (MOSFET). The performance stability of a TFET at higher temperatures, especially in subthreshold regime in which the n-i-n device exhibits a devastating characteristic, is appreciable. Alongside very low subthreshold swing even at a temperature beyond 300 K, a p-i-n tunnel FET could be a more reliable choice for operating in a wide range of temperatures. The subthreshold swing, transconductance, output conductance, saturation mechanism and on/off current ratio are also considered with respect to CNT diameter as well. A lower diameter lessens some negative effects of operating at a high temperature. All the results can be realized based on the energy band diagram of the device and the Fermi functions of source and drain. This trend gives a valuable insight into exploring the changes in

Design of analog modular neuron based on memristor is proposed here. Since neural networks are built by repetition of basic blocks that are called neurons, using modular neurons is essential for the neural network hardware. In this work modularity of the neuron is achieved through distributed neurons structure. Some major challenges in implementation of synaptic operation are weight programmability, weight multiplication by input signal and nonvolatile weight storage. Introduction of memristor bridge synapse addresses all of these challenges. The proposed neuron is a modular neuron based on distributed neuron structure which it uses the benefits of the memristor bridge synapse for synaptic operations. In order to test appropriate operation of the proposed neuron, it is used in a real-world application of neural network. Off-chip method is used to train the neural network. The results show 86.7 % correct classification and about 0.0695 mean square error for 4-5-3 neural network based on proposed modular neuron.

In this paper a novel smart control and data handling system based on Atmega128 microcontroller is presented. The proposed system has extensive capabilities in remote controlling and smart quota allocation, such as exclusive RFID card detection and quota allocation system, SAM card, GPS/GPRS/GSM communication system and smart data logger, which can be used in agricultural industries and household consumption. The proposed system can synchronized with various liquid flow meters through network, RS485, RS232 and M-BUS in a secure and encrypted way. Furthermore, implementation results show high efficiency and accuracy in controlling data with high resistance against the data hacking.

Full adder cells play a vital role in numerous VLSI circuits. Therefore, design of an energy-efficient full adder which operates reliably in submicron technologies has become a great concern in recent years. Some previously designed cells suffer from non-full swing outputs, high-power consumption and low-speed issues. In this paper, two high-speed, low-power and full-swing full adder circuits are designed in 90-nm CMOS technology. According to simulation results, the proposed circuits have rail to rail output signals. Also, an improvement of 12%–52%, 7%–48% and 28%–68% has been achieved in delay, power consumption and power-delay product (PDP), respectively.

Many existing XOR-XNOR cells suffer from nonfull-swing outputs, high power consumption and low speed issues. In this paper, a new fast, full-swing and low-power XOR-XNOR cell, is presented. Simulation results in 90-nm CMOS technology show that the proposed circuit has rail to rail outputs Also, we have gained 11%–51%, 2%–19% and 18%–52% improvement in delay, power consumption and power-delay product (PDP), respectively. In order to do a comparison between the previously reported XOR-XNOR cells and our proposed circuit, they are embedded in a 4-2 compressor circuit and simulation results prove energy efficiency of ours in more complicated structures.

In this paper a novel human tracking FPGA design based on particle filter algorithm is proposed. The proposed tracking system uses Particle filter as a real time and iterative tracking algorithm in order to achieve the ability of tracking high dynamic objects. The proposed algorithm is simulated by ise14.2 using FPGA core family virtex6 (xc6vcx75T). The optimality of the proposed algorithm was verified using Matlab. This algorithm has free input size which can be extended conveniently up to the FPGA constraints. In order to have a high precession tracking system, the proposed algorithm generates 300 particles which are evaluated and updated according to their suitability. The proposed tracking algorithm consists of 11 units and shows high optimality in important tracking system parameters such as: speed, maximum frequency and latency compared to the previous works.

In this paper a novel image encryption algorithm based on discrete wavelet transform (DWT) is proposed which uses two-dimensional logistic map as Private-Key. The algorithm uses Haar wavelet transform in order to generate image sub-bands which are used in encryption and decryption process and then two-dimensional logistic map is applied to the encrypted image in order to generate chaotic matrix which causes the encrypted image to be more secure. This chaotic matrix can also be used as a private-key in decryption process. The reversible proposed algorithm is evaluated with standard images and statistical techniques. The results show proposed algorithm possesses higher security and performance compared to the previous works.