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This research proposes a hybrid Full Adder (FA) cell using a combination of Gate Diffusion Input (GDI) technique, Transmission Gate (TG) and conventional Static CMOS (C-CMOS) logic. To test performance parameters, simulation has been conducted using Cadence Virtuoso in 65 nm technology. Moreover, a comparative analysis of the proposed design with 13 existing state of art FAs has been presented in this research to observe the performance improvements obtained by the proposed FA. In addition, the proposed and existing FAs have been cascaded to implement 4-bit, 8-bit, 16-bit and 32-bit adder to test their performance and feasibility in large structures. The proposed design exhibited remarkable performance both as single cell and cascaded mode. Besides, the proposed technique for FA design removes the defect of voltage degradation in GDI technique and low drivability of TG based design by utilizing C-CMOS logic in the output terminals.

Binary magnitude comparator is considered as an elementary apparatus in Arithmetic Logic Unit. Due to increased use of portable devices nowadays, energy efficient designs having less delay have become essential. This research introduces a new two-bit binary magnitude comparator consisting 46 transistors. To analyze performance, simulation of the proposed design has been conducted using Cadence Computer Aided Design apparatus in 90 nm Technology. To analyze design feasibility, the proposed design has been compared with the existing two-bit binary magnitude comparator design. According to simulation result, the proposed design displayed 9.865 $\mu$ W average power consumption, 0.193 ns delay and 1.904 fJ Power Delay Product which was significantly less than the existing two-bit magnitude comparator designs.

A 4-bit Carry Look-Ahead (CLA) architecture for carry-generation process is proposed. CLA architecture proposed in this work uses complex CLA circuits for carry-generation rather than using carry-generate and carry-propagate functions which are used in the conventional process of 4-bit CLA architecture. Performance of the proposed CLA architecture is validated by performing simulation utilizing Cadence tools in standard 45 ​nm CMOS process. In order to prove effectiveness, performance of the proposed 4-bit CLA design is compared with existing 4-bit CLA designs. Moreover, as a possible application of the proposed design and to inspect performance in wide word length adder structure, the 4-bit CLA architectures (proposed and existing) are extended to 16-bits using Carry-Select Adder (CSA) architecture. Both as 4-bit cell and extended 16-bit structure, the proposed 4-bit CLA shows remarkable improvement in speed while maintaining quite acceptable level of power consumption. As a result, the proposed 4-bit CLA can be utilized as a highly suitable substitution of the existing 4-bit CLA architectures in high-speed microprocessor design.