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The use of capacitive sensors in the automotive context opens new possibilities in the development of new interfaces for machine interaction with the vehicle occupants. Large smart surfaces with gesture recognition will possibly be part of such new interfaces. However, the data processing cost of such new sensors should be maintained at a minimum while increasing the complexity of their gesture recognition accuracy by using modern deep-learning approaches. In this paper, we introduce the use of Bayesian optimization with execution platform constraints to implement accurate gesture recognition sensors based on 1D capacitive sensor arrays. Various RNN-based designs are implemented and optimized for their execution on embedded automotive microcontrollers. We show that LSTM and GRU-based designs are especially adequate achieving an average recall of the gesture classes over 95% in less than 100 optimization steps.

The advent of machine learning (ML) methods for the industry has opened new possibilities in the automotive domain, especially for Advanced Driver Assistance Systems (ADAS). These methods mainly focus on specific problems ranging from traffic sign and light recognition to pedestrian detection. In most cases, the computational resources and power budget found in ADAS systems are constrained while most machine learning methods are computationally intensive. The usual solution consists in adapting the ML models to comply with the memory and real-time (RT) requirements for inference. Some models are easily adapted to resource-constrained hardware, such as Support Vector Machines, while others, like Neural Networks, need more complex processes to fit into the desired hardware. The ADAS hardware (HW platforms) are diverse, from complex MPSoC CPUs down to classical MCUs, DPSs and application-specific FPGAs and ASICs or specific GPU platforms (such as the NVIDIA families Tegra or Jetson). Therefore, there is a tradeoff between the complexity of the ML model implemented and the selected platform that impacts the performance metrics: function results, energy consumption and speed (latency and throughput). In this paper, a survey in the form of systematic review is conducted to analyze the scope of the published research works that embed ML models into resource-constrained implementations for ADAS applications and what are the achievements regarding the ML performance, energy and speed trade-off.

Ajudes: National Key Research and Development Program of "Strategic Advanced Electronic Materials" under Grant 2016YFB0401100 and in part by the NSFC of China under Grant 61274083 and Grant 61334008. Attributed to its advantages of super mechanical flexibility, very low-temperature processing, and compatibility with low cost and high throughput manufacturing, organic thin-film transistor (OTFT) technology is able to bring electrical, mechanical, and industrial benefits to a wide range of new applications by activating nonflat surfaces with flexible displays, sensors, and other electronic functions. Despite both strong application demand and these significant technological advances, there is still a gap to be filled for OTFT technology to be widely commercially adopted. This paper providesa comprehensive reviewof the current status of OTFT technologies ranging from material, device, process, and integration, to design and system applications, and clarifies the real challenges behind to be addressed.

Neural Architecture Search (NAS), which allows for automatically developing neural networks, has been mostly devoted to performance on a single metric, usually accuracy. New approaches have added more objectives, such as model size, in order to find networks suitable for resource-constrained platforms. SpArSe [1] is a multi-objective Bayesian optimization framework for automatically developing image classification convolutional neural networks (CNNs) for micro-controller units (MCUs). In this work, we first implement SpArSe and modify it to reduce search time, obtaining similar results regarding accuracy, model size, and maximum working memory but in less optimization time. Moreover, we extend the search space to include recurrent neural networks (RNNs) and add an inference latency objective for time-constrained tasks. Finally, we test our implementation in a gesture recognition task obtaining better results than previous manually tuned approaches for size and performance metrics, which validates the approach and its utility.

In this paper we present a novel method to print paper and cardboard without ink. The method is based on the carbonization of paper by a combination of lasers working on different wavelengths. A prove of concept system is created based on combining existing commercial systems to demonstrate the viability of the method. The results show that no debris is generated and the quality of the mark is superior in terms of contrast and resolution with previously known methods.

Organic electronics is one of the most promising technologies for creating flexible electronic devices using low temperature plastic compatible processes. However, contact resistances of organic transistors remain one of the most significant hurdles to achieving high performance circuits in this technology. Short channel devices (

Implementation of organic digital circuits (or printed electronic circuits) has been under an extensive investigation, facing some critical challenges such as process variability, device performance, cell design styles and circuit yield. Failure in any single Organic Thin Film Transistor (OTFT) often causes the whole circuit to fail since integration density is still low. For the same reason, the application of fault tolerant techniques is not that popular in these circuits. In this paper, we propose an approach for the direct mapping of digital functions on top of new prefabricated structures: Inkjet-Configurable Gate Arrays (IGA). This alternative has two main advantages. First, it helps to obtain high yield circuits out of mid-yield foils, and second, it allows implementing individual circuit personalization at a very low cost by using additive mask-less printing techniques thus avoiding the need for OTPROM-like (or E2PROM) devices. All along the design process of IGA cells and structures we used the scalability and technology-independent strategies provided by parameterizable cells (PCell) what helps dealing with current fast technology evolution.

In the last years there has been a growing interest in the realization of low-cost, flexible and large area electronic systems such as item-level RFID tags, flexible displays or smart labels, among others. Specifically, inkjet printing technology has been increasingly applied as advanced deposition technology in the field of printed electronics due to the high flexibility in terms of patterns (mask-less) and materials, and its low cost approach as only a small amount of materials is required in comparison to other solution-based deposition techniques. Our work focuses on the development of Organic Thin Film Transistors (OTFTs) by using organic, inorganic inks and low-cost all-inkjet purely printing process, thus centring the effort in the design, manufacturing and characterization point of view in order to fabricate all-inkjet printed organic integrated circuits. Electrical and morphological characterizations were performed in order to obtain device statistics to investigate the origins of the failures responsible for the low yields. Most of research works are based on laboratory inkjet equipment for manufacturing using single nozzle systems to fabricate small numbers of devices. The variability and mismatch of the printed devices are underrepresented in literature and are key factors towards commercialization of printed electronics.

This paper presents two main contributions toward efficient VLSI circuits mapped with simple cells: (1) a complete synthesis flow to provide good-quality circuits mapped only with simple cells; and (2) an area-oriented, level-aware buffering algorithm based on inverter trees to fix cell fanout violations. We show that efficient implementations in terms of inverter count, transistor count, area, power and delay can be generated from circuits with a reduced number of both simple cells and inverters, combined with XOR/XNOR-based optimizations. The proposed buffering algorithm can handle all unfeasible fanout occurrences, while (i) optimizing the number of added inverters; and (ii) assigning cells to the inverter tree based on their level criticality. When comparing with academic and commercial approaches, we are able to simultaneously reduce the average number of inverters, transistors, area, power dissipation and delay up to 48%, 4%, 8%, 14%, and 16%, respectively.

This paper discusses the modeling of patent claims in ontology based representation of patent information. Our contributions relate to the internal structure of the claims and the use of the all-element rule for patent coverage. Starting from the general template for the structure of the claim, we present contributions to (1) visualization of claims, (2) storing claim information in a web semantics framework, and (3) evaluating claim coverage using Description Logic.

Pedestrian detection is a vital function of the emerging autonomous vehicle industry. HOG is widely used as the feature extractor for pedestrian detection thanks to its high accuracy despite the fact that it is computationally expensive. Hardware accelerators using GPUs or FPGAs are used in several proposals to address its real-time execution. There is always a trade-off between real-time processing, energy efficiency and accuracy in the existing solutions. In this paper, we present a pipelined implementation of HOG feature extraction on a low-cost Cyclone V SoC FPGA platform. The design is provides a latency of 4ms for every 640×480 input frame, which corresponds to 250fps. The whole detection system reduces the power consumption by 53.3% and 96% compared with state of the art FPGA and GPU alternatives.

Reconfigurable parallel computing is required to provide high-performance embedded computing, hide hardware complexity, boost software development, and manage multiple workloads when multiple applications are running simultaneously on the emerging network-on-chip (NoC)-based multiprocessor systems-on-chip (MPSoCs) platforms. In these type of systems, the overall system performance may be affected due to congestion, and therefore parallel programming stacks must be assisted by quality-of-service (QoS) support to meet application requirements and to deal with application dynamism. In this paper, we present a hardware-software QoS-driven reconfigurable parallel computing framework, i.e., the NoC services, the runtime QoS middleware API and our ocMPI library and its tracing support which has been tailored for a distributed-shared memory ARM clustered NoC-based MPSoC platform. The experimental results show the efficiency of our software stack under a broad range of parallel kernels and benchmarks, in terms of low-latency interprocess communication, good application scalability, and most important, they demonstrate the ability to enable runtime reconfiguration to manage workloads in message-passing parallel applications.

The benefits of stereoscopic vision in medical applications were appreciated and have been thoroughly studied for more than a century. The usage of the stereoscopic displays has a proven positive impact on performance in various medical tasks. At the same time the market of 3D-enabled technologies is blooming. New high resolution stereo cameras, TVs, projectors, monitors, and head mounted displays become available. This equipment, completed with a corresponding application program interface (API), could be relatively easy implemented in a system. Such complexes could open new possibilities for medical applications exploiting the stereoscopic depth. This work proposes a tool for production of interactive stereoscopic graphical user interfaces, which could represent a software layer for web-based medical systems facilitating the stereoscopic effect. Further the tool's operation mode and the results of the conducted subjective and objective performance tests will be exposed.

Wearable electronics are gaining widespread use as enabling technologies, monitoring human physical activity and behavior as part of connected health infrastructures. Attention to human factors and comfort of these devices can greatly positively influence user experience, with a subsequently higher likelihood of user acceptance and lower levels of device rejection. Here, we employ a human factors and comfort assessment methodology grounded in the principles of human-centered design to influence and enhance the design of an instrumented insole. A use case was developed and interrogated by stakeholders, experts, and end users, capturing the context of use and user characteristics for the instrumented insole. This use case informed all stages of the design process through two full design cycles, leading to the development of an initial version 1 and a later version 2 prototype. Each version of the prototype was subjected to an expert human factors inspection and controlled comfort assessment using human volunteers. Structured feedback from the first cycle of testing was the driver of design changes implemented in the version 2 prototype. This prototype was found to have significantly improved human factors and comfort characteristics over the first version of the prototype. Expert inspection found that many of the original problems in the first prototype had been resolved in the second prototype. Furthermore, a comfort assessment of this prototype with a group of young healthy adults showed it to be indistinguishable from their normal footwear. This study demonstrates the power and effectiveness of human factors and comfort assessment methodologies in influencing and improving the design of wearable devices. This work was part funded by the EU FP7 project WIISEL (Wireless Insole for Independent and Safe Elderly Living). Project number FP7-ICT-2011-288878. peer-reviewed

This paper presents a global proposal and methodology for developing digital printed electronics (PE) prototypes, circuits and application specific printed electronics circuits (ASPECs). We start from a circuit specification using standard Hardware Description Languages (HDL) and executing its functional simulation. Then we perform logic synthesis that includes logic gate minimization by applying state-of-the-art algorithms embedded in our proposed electronic design automation (EDA) tools to minimize the number of transistors required to implement the circuit. Later technology mapping is applied, taking into account the available technology, (i.e., PMOS only technologies) and the cell design style (either Standard Cells or Inkjet Gate Array). These layout strategies are equivalent to those available in application specific integrated circuits (ASICs) flows but adapting them to Printed Electronics, which vary greatly depending on the targeted technology. Then Place & Route tools perform floorplan, placement and wiring of cells, which will be checked by the corresponding layout versus schematic (LVS). Afterwards we execute an electrical simulation including parasitic capacitances and relevant parameters. Finally, we obtain the prototypes which will be characterized and tested. The most important aspect of the proposed methodology is that it is portable to different PE processes, so that considerations and variations between different fabrication processes do not affect the validity of our approach. As final results, we present fabricated prototypes that are currently being characterized and tested.

Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as "Bridging Platform". This transfer to "Bridging Platform" from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.

All inkjet printed rectifying diodes based on a metal-insulator-semiconductor (MIS) layer stack are presented. The rectifying properties were optimized by careful selection of the insulator interlayer thickness and the layout structure. The different diode architectures based on the following materials are investigated: (1) silver/ poly (methylmethacrylate-methacrylic acid)/ polytriarylamine/ silver, (2) silver/ polytriarylamine/ poly (methylmethacrylate-methacrylic acid)/ silver, and (3) silver/ poly (methylmethacrylate-methacrylic acid)/ poly-triarylamine/ poly(3,4-ethylenedioxythiophene) poly (styrenesulfonate). The MIS diodes show an averaged rectification ratio of 200 and reasonable forward current density reaching 40 mA cm -2. They are suitable for a number of applications in flexible printed organic electronics. EU [287682]

International audience; This paper deals with the implementation of control algorithms for alternative current (ac) motors using co-design methodology for hard or mixed hardware/software solutions. The authors focus on the design flow and experiments using FPGA / DSP platform. A full FPGA implementation of the well-known field oriented control strategy is presented. In a next step a mixed FPGA / DSP platform is presented associated with preliminary results concerning a mixed implementation of the scalar control algorithm.

Printed electronics technologies add new fabrication concepts to the classical set of microelectronic processes. Among these, the use of digital printing techniques such as inkjet permits the deposition of materials on top of preexisting substrates without any mask. This allows individual personalization of electronic circuits. Different proposals have been made to make use of such a property: (1) wiring new metallic layers on top of circuits to build programmable logic array-like circuits, (2) programming OTP ROM like memories, and (3) building inkjet-configurable gate arrays. The capability of building an individual circuit with technological steps simpler than photolithographic ones opens a concept similar to the successful field programmable gate array. Although nowadays the process resolution is still low, it can quickly evolve to higher wiring densities and therefore permit a greater level of transistor integration. In this paper, we propose a new structure to realize the connections only by deposition of conductive dots oriented to optimize the area needed to implement the drop-on-demand (DoD) wiring at circuit level. One important feature of this structure is that it minimizes the amount of printed material required for the connection thereby reducing failures often seen with DoD printing techniques for conductive lines. These structures have been validated by two different DoD technologies: inkjet and superfine jet, and have been compared to mask-based photolithography technology with promising results. acceptedVersion

The present work explores the effect of introducing stereoscopic depth to two specific examples of applications. The utilized depth has both an aesthetic and utilitarian function. One case explores a 3D garment catalog, and gives the user the task to rate garments. The second use case is a ‘Pairs’ game in which completing the game itself is the task. In total, effectiveness, efficiency, usability, desirability and gaze patterns were compared between monoscopic and stereoscopic versions of both applications. Time to complete the relevant task did vary, but efficiency, usability, and visual perception did not change. Desirability and eye patterns did differ. This behavior is important to acknowledge in order to better design experiences that utilize stereoscopic images.

Application specific printed electronic circuits (ASPECs) are the corresponding term with application-specified ICs for printed electronics. The same as any new technology, printed electronics is suffering from some restrictions in design and process technology aspects. An important stage in the ASPEC design is the final wiring of the organic thin-film transistor arrays or gate arrays to customize it to implement any specific target application that fits in their structure. In this paper, we evaluate two additive manufacturing technologies: aerosol jet using Optomec M3D and electrohydrodynamic printer using superfine inkjet. Both techniques are based on direct-writing of the pattern corresponding to any individual circuit being fabricated (digital printing) enabled by the mask-free noncontact deposition of materials. Finally, these structures will be compared with the corresponding photolithography mask technology. Some parameterized test vehicles, with different instantiations for the variation of line widths and separations, have been designed to be wired using the target technologies. These test vehicles have been fabricated at the Centre for Process Innovation by a five masks lithography and subtractive patterning technology. Results show that both direct printing technologies are feasible for the fabrication of the gate-array customization, thus allowing individual personalization of every circuit what can produce added value functionalities at low cost such as the equivalent effect of having an ROM memory which final contents could be customized at home by using low-cost digital printing technologies. Further interactions between transistor bulk and wiring technologies can improve the obtained performance in order to end up in an industrialized process.

This paper presents two main contributions toward efficient very large scale integration circuits mapped with simple cells: 1) a complete synthesis flow to provide good-quality circuits mapped only with simple cells; and 2) an area-oriented, level-aware buffering algorithm based on inverter trees to fix cell fanout violations. An effective pattern-based algorithm to identify XORs/XNORs on and-inverter graphs is also presented. We show that efficient implementations in terms of inverter count, transistor count, area, power, and delay can be generated from circuits with a reduced number of both simple cells and inverters, combined with XOR/XNOR-based optimizations. The proposed buffering algorithm can handle all unfeasible fanout occurrences, while: 1) optimizing the number of added inverters and 2) assigning cells to the inverter tree based on their level criticality. When comparing with academic and commercial approaches, we are able to simultaneously reduce the average number of inverters, transistors, area, power dissipation, and delay up to 48%, 4%, 8%, 14%, and 16%, respectively.