Search

Leadless Cardiac Pacemakers (LCP) have the potential to revolutionize Cardiac Rhythm Management (CRM). Current LCPs can only pace a single location of the heart limiting their use to patients requiring single-chamber stimulation. A Multi-node system of synchronized LCPs could be used in a significantly larger patient population. Synchronization using standard communication techniques involves high power consumption decreasing the longevity of the device. In this work, we investigate Galvanic Intra Body Communication (IBC) as a method to synchronize multi-node LCP systems. First, an accurate computational torso model was used for quasi-static simulations to estimate channel pathloss in the frequency range [40 kHz-20 MHz]. The model was then verified with in-vivo measurements using a novel experimental setup, where two LCP devices were placed in the right atrium, right ventricle and left ventricle. All channels involved in a potential multi-node LCP system were characterized. The orientation of the transducers relative to each other had a great impact on the results, with the attenuation level ranging between 55 dB and 70 dB between the best and worst orientations. The best results were achieved in the MHz range. Coupled with the fact that it does not require additional electrodes, this study suggests Galvanic IBC be superior to conventional communication methods for LCP devices. This analysis defines a methodology for galvanic IBC channel characterization for LCP systems, which is an important step for the design of efficient transceivers for IBC applications. More experiments with larger datasets are needed to bring this method to practice.

In this work, a novel approach to reduce the complexity of memory polynomial model is presented. The proposed technique, named the coefficient decomposition (CD) technique, is based on reducing the search space for the memory polynomial coefficients based on memory effects generation mechanism. In this paper, the technique is demonstrated for power amplifier of classes A and AB. In this case, the physical analysis shows that the conventional two-dimensional coefficient architecture of the memory polynomial could be simplified into a one dimensional architecture while keeping almost the same accuracy. The performance of the proposed approach is demonstrated and compared with other models using a 30 dBm commercial power amplifier with 20 MHz and 60 MHz LTE signals. The measurements and simulations showed that, the presented model achieves −34.2 dB of NMSE while needing only 13 coefficients compared with 25 needed for a memory polynomial model. Also, the DPD performance of the proposed model is the same as memory polynomial model and comparable with high complexity models like the PLUME and GMP.

The Direct RF-to-Digital $\Delta\Sigma$ receiver has emerged as an attractive solution for multi-band multi-standard wireless applications. This architecture is a direct RF to baseband digitizer with RF feedback from baseband to RF stages. The presence of the RF blocks such as the low noise amplifier and down-conversion mixer inside the loop filter significantly relaxes their linearity requirements and also improves the noise transfer function of the loop filter. However, the RF feedback poses several challenges, especially making the design methodology more complex. In contrast to classical receiver architectures, the blocks of the Direct RF-to-Digital $\Delta\Sigma$ receiver cannot be designed, analyzed, and simulated independently. Besides, conventional design methodologies for $\Delta\Sigma$ Modulators cannot be applied for this kind of receiver due to the presence of the RF blocks and the RF feedback inside the loop. This paper presents a new design methodology suited for this family of receivers. The proposed methodology covers simulation approaches, system design, and non-ideality impacts on the receiver. A design example of a multi-band multi-standard receiver for GSM/WCDMA/LTE is considered throughout the paper to demonstrate this design methodology.

In this study, a new behavioural model named memory aware physically enhanced polynomial model is proposed. This modelling approach is based on using a physical analysis of the power amplifier (PA) operation and takes into account the electro-thermal and electrical memory effects as main sources of long-term memory. The physical analysis-based approach allows to select the most relevant coefficients for the model and discards the less significant ones in order to minimise the complexity. In this study, the proposed methodology is demonstrated on a single-stage class-AB PA. Nevertheless, it is applicable for multi-stage PAs. The model accuracy and complexity are evaluated using measurement results from two commercial PAs. Compared to the conventional memory polynomial (MP) model, for, respectively, 20 and 80 MHz long-term evolution signals, the proposed model shows 3 and 5 dB improvement in the normalised mean square error with fewer coefficients 18 instead of 20 for a memory depth of 3. Also, with same accuracy the proposed model has considerably fewer coefficients compared with the PLUME and generalised MP (GMP) models. Applying digital predistortion (DPD), the proposed model outperforms the MP model in terms of performance and the PLUME and GMP models in terms of complexity.

This paper presents a new digital predistortion (DPD) technique for wide band applications. Digital predistortion is the most useful linearization technique to reduce power amplifier (PA) nonlinearity effects due to its high flexibility and low complexity. However, this technique requires high performances ADC to digitize the feedback signal whose bandwidth is equal to several times the original bandwidth due to spectral regrowth generated by the PA nonlinearity. This point represents one of the main bottlenecks for the deployment of the wideband LTE-A standard. The method proposed in this paper calculates the DPD coefficients iteratively using an ADC with a fixed bandwidth equal to the original bandwidth. The proposed method has been simulated and compared with other methods using Matlab. Simulation results show that the proposed method has almost the same performance as the other methods with an ACPR of − 60 dB. Moreover, it reduces considerably the constraints on the ADC and the power calculation resources.

In this paper, we present a low-power high-performance digital predistorter (DPD) for the linearization of wideband RF power amplifiers (PAs). It is based on the novel FIR memory polynomial (FIR-MP) predistorter model, which significantly augments the performance of the conventional memory polynomial predistorter with the use of complex baseband digital FIR filter prior to the memory polynomial. The adjacent channel leakage ratio (ACLR) performance comparison between the conventional MP and the proposed FIR-MP is done based on simulations with multi-carrier modulated signals of 20 and 80 MHz bandwidths. The PA models used for the simulations are extracted from the measurements of a commercial $$1\,\hbox {W}$$ GaAs HBT PA. At the ideal system-level simulations, the improvements in ACLR over the conventional MP are 7.2 and 15.6 dB, respectively, for 20 and 80 MHz signals. The choice of selection of various parameters of the predistorter along with the subsequent digital-to-analog converter (DAC) is presented. The impact of fixed-point representation is assessed using ACLR metrics, which shows that a wordlength of 14 bits is sufficient to obtain ACLR beyond $$45\,\hbox {dBc}$$ with a margin of $$10\,\hbox {dB}$$ . The proposed predistorter is synthesized in $$28\,\hbox {nm}$$ fully-depleted silicon-on-insulator (FDSOI) CMOS process. It is shown that with a fraction of the power and die area of that of the MP a huge improvement in ACLR is attained. With an overall power consumption of 8.2 and 88.8 mW, respectively, for 20 and 80 MHz signals, the FIR-MP DPD proves to be a suitable candidate for small-cell base station PA linearization.

Parallel subband digital predistortion (DPD) has emerged as a promising approach for linearizing power amplifiers (PA) in wireless communication systems. This solution has the advantage of relaxing the bandwidth constraints on the feedback path analog to digital converter (ADC) which digitizes the PA distorted output which may spread over several hundreds MHz in the latest generations of mobile communications. However, the subband approach still has some limitations such as signal reconstruction and subband aliasing which limits its implementation on a wide scale. In this paper, an FFT-Based DPD technique that enables to compute the predistorter without interpolating signals is presented. Thanks to the frequency domain approach, the subband signals can be combined easily to compute the fullband predistorter directly. Moreover, the proposed technique offers the possibility of selecting specific frequency bins for the computation. In particular, the subband edges can be ignored which will result in relaxed bandwidth constraints and selectivity for the subband ADCs. Simulations show that the proposed FFT based subband DPD performs as good as the conventional time domain least-square approach even while excluding up to 13% of the FFT bins at the band edges.

International audience; This brief proposes a new all-digital calibration technique suppressing the timing mismatch effect in time-interleaved analog-to-digital converters (TIADCs) for input at any Nyquist band (NB) using the equivalent polyphase structure of the TIADC. The correction technique is simple and does not require the adaptive digital synthesis filters. The timing mismatch is estimated based on an adaptive stochastic gradient descent technique, which is a promising solution for TIADCs operating at a very fast sampling rate. The digital circuit of the proposed calibration algorithm is designed and synthesized using a 28-nm fully depleted Silicon on insulator (FD-SOI) CMOS technology for the 11-b 60-dB SNR TIADC clocked at 2.7 GHz with the input in the first four NBs. The designed circuit occupies the area of 0.05 mm2 and dissipates the total power of 41 mW.

Leadless Cardiac Pacemaker (LCP) devices are the cutting edge technology for cardiac rhythm management. An LCP requires to communicate with an external programmer and with different LCP nodes placed in different heart chambers. Human Body Communication (HBC) is an ultra-low-power telemetry that exploits body conduction properties to propagate signals. There is a lack of studies in the literature about intracardiac HBC channel characterization. Channel modeling is fundamental to prototype transceivers able to link different LCP devices. Quasi-Static Simulations based on Finite Element Method (FEM) have been used to characterize all HBC channels involved in LCP telemetry. A very accurate 3D model of a Human Torso has been designed and used to characterize HBC attenuation levels in a frequency range between 40 kHz and 20 MHz. This kind of approach will help to minimize animal trials for a more durable and optimized development.

This paper focuses on wideband power amplifier predistortion for current and future communications standards such as LTE and 5G. As a matter of fact, the large bandwidth and the large dynamic range of exchanged signals in these standards make the predistortion task very challenging. To overcome these challenges, innovations and improvements are needed in the three main blocks of the predistortion system, i.e., modeling and estimation algorithms, the transmission path and the observation path. In this work, for each of these three blocks, the state of the art is briefly presented and solutions are proposed to contribute in achieving a low power wideband predistortion compatible with the 5G low power transmission cells.

International audience; Digital post-distortion is becoming an increasingly attractive solution to compensate for the non-linearities of RF receivers implemented in deep submicron CMOS technologies. A very promising technique which provides flexibility and robustness is the frequency spreading based digital post-distortion. This paper focuses on the analysis of this approach for wideband receivers and its main limitations, such as the anti-alias filter (AAF) impact. As a matter of fact, distortions filtered by the AAF can degrade the correction performance. To overcome this problem, a novel solution based on mimicking the AAF frequency response in the digital domain is proposed. Aspects regarding the estimation and the algorithm convergence are also studied: the noise effect and the choice of the free frequency band. Furthermore, two other techniques are developed to improve the modeling and the correction of the memory effect using, respectively, a bank of filters and two-step architecture. The proposed techniques are demonstrated by simulations and measurements on a multi-channel receiver suited for DVB-T applications. The receiver is based on a 1-GHz bandwidth RF front-end followed by a 2.7-GHz 13-bit analog-to-digital converter.

A memory polynomial (MP) based digital baseband predistorter for wideband base station RF power amplifiers is presented. The conventional memory polynomial based predistorter's inability to sufficiently improve the adjacent channel leakage ratio (ACLR) for high bandwidth signals is mitigated by using a linear FIR filter. The FIR filter compensates for the linear memory distortions and is employed prior to the memory polynomial predistorter (FIR-MP). The proposed technique is validated in simulations for 20 MHz and 80 MHz signals centered at 2 GHz. The PA models for the simulation are extracted from measurements carried out on a commercial 1W GaAs HBT PA. With considerably less number of coefficients, an ACLR improvement of at least 5.2 dB and 11.1 dB over the conventional MP DPD is obtained for 20 MHz and 80 MHz signals, respectively, and hence showing suitability for the adoption into small-cell base stations.

This paper presents a low-power fully digital clock skew feedforward background calibration technique in sub-sampling Time-Interleaved Analog-to-Digital Converters (TIADCs). Both estimation and correction algorithms share the common derivative filter, which makes them possible to reduce the chip area. Furthermore, these algorithms use the polyphase filtering technique and do not use adaptive digital synthesis filters. Thus, the proposed calibration can be implemented on a moderate hardware cost with low power dissipation. The adopted feedforward technology eliminates the stability issues encountered with the adaptive technique. The Hardware Description Language (HDL) design of the proposed calibration is synthesized using a 28nm FD-SOI process for a 60dB SNR TIADC clocked at 2.7GHz. The calibration is designed for both baseband and sub-sampling TIADC applications. For sub-sampling TIADCs with the input at the first four Nyquist bands, the synthesized calibration system occupies $0.04\rm {mm}^{2}$ of area and dissipates a total power of 33.2mW. For the baseband TIADC applications, it occupies $0.02\rm {mm}^{2}$ and consumes 15.5mW.

This paper presents a 3rd-order continuous-time direct RF-to-digital ΔΣ receiver architecture for flexible receivers. Adopted passive mixer with inherited high-Q bandpass filtering and passive integrator enables a low complexity and low power consumption implementation. Moreover, high flexibility can be achieved thanks to a flexible frequency plan of the architecture. In order to verify the features of this proposed architecture, a design example with 10 MHz useful baseband bandwidth and 0.4–4.0 GHz frequency range is conducted.

This paper presents a 120 dB Stacked analog to digital (A/D) converter dedicated for radio astronomy. The design of the chain of cascaded amplifiers preceding the A/D converters was performed in a 1.2 V 65 nm CMOS process. Simulation results showed that the designed chain of three cascaded amplifiers has an overall gain of 90 dB (30 dB each) over 100 MHz of bandwidth. The paper proposes also a calibration technique that copes with the phase and gain mismatches between channels allowing thereby to reach the minimum required SNR of 30 dB over all the input range.

Time interleaving (TI) is one of the best approaches to relax the speed-power trade-off of analog-to-digital converters (ADC). However, channel mismatches especially timing can limit the resolution of TIADC if they are not addressed properly. To achieve an efficient calibration for these errors, the most difficult task is the error estimation in the digital domain. The correction is less problematic and can be done either in digital domain or in the analog domain. Two big families of estimation techniques are commonly employed: the free-band estimation and the cross-correlation estimation. This paper reviews and analyses these estimation techniques and highlights their limitations. It also presents solutions to overcome these limitations.

The Internet of Thing (IoT) is experiencing explosive growth in the number of devices and applications. However, the existing cloud-centric architecture of IoT poses serious challenges regarding network latency, privacy, and energy-efficiency. We have presented COGNICOM+ concept, a brain-inspired software-hardware paradigm, to support IoT's future growth and developed 4 research directions — flexible radio, convolutional neural network accelerator, compressed deep learning, and game theory for reasoning and collaboration — within COGNICOM+. The key idea is to bring computing closer to the end-user while focusing on optimal uses of local smart application gateway and cloud computing. COGNICOM+ consists of two key components: Cognitive Engine (CE) and Smart Connectivity (SC). The cognitive engine is powered by deep-learning algorithms integrated with game-theoretic decision analytics, implemented on a low-power application-specific integrated circuit. It provides cognitive functions to smart objects. The smart connectivity integrates neural network inspired designs of cognitive radio, transceivers, and baseband processors. The SC provides flexible and reliable connections to IoT objects and optimally distributes communication resources.

With the increasing bandwidth of communication signals, the challenges on the feedback path used for digital predistortion (DPD) of power amplifiers are getting significantly stringent. A subband approach has been recently proposed by the authors in order to relax the design constraints on the feedback path ADC. This paper presents a new step toward a practical implementation of the concept with LTE signals. A continuous-time multi-channel modulator is proposed to address wider bandwidths and sizing choices are discussed with simulation results. Some nonlinear effects of the feedback path such as I/Q imbalance, pure nonlinearity and quantization are simulated to define high level design parameters. Results show that for a distorted signal with 30 dB ACPR, 60 dB SNR is sufficient for the principal subband and 22 dB SNR is required for the adjacent subbands to perform as good as an ideal fullband DPD. Continuous-time simulation using a 2-4-4 configuration of the zero IF MSNBC with 4-bit quantizers achieves the required subband SNRs.

This paper presents a reconfigurable 2nd/3rd-order discrete-time direct RF-to-digital ΔΣ receiver architecture for wide frequency range flexible receivers. Using 25% duty-cycle current-driven passive mixer along with RF feedback enables high-Q bandpass filtering and relaxes the linearity requirement on LNTA. Moreover, the passive/active implementation of the loop filter gives a good trade-off between power consumption, linearity and dynamic range. A design example with 10 MHz useful bandwidth and 0.4–4.0 GHz frequency range is conducted to demonstrate the feasibility and the characteristics of this proposed architecture.

In this paper, high-pass (HP) $$\Updelta\Upsigma$$ modulators are compared against the traditional low-pass (LP) $$\Updelta\Upsigma$$ modulators. The objective of this comparison is to point out the advantages and drawbacks of the two modulators thereby allowing choosing the most suited for a given application. The metrics of comparison are the noise floor, power consumption, area and the effect of the non-idealities of all the basic blocks (i.e., operational transconductance amplifier, quantizer, switches and clocks). The comparative analysis shows that HP modulators are more suited for narrow band applications because of their immunity against DC-offset and flicker noise. For medium and wide band applications, LP modulators are preferred because of their higher robustness against switch imperfections and clock jitter.

This paper presents a practical implementation of all digital calibration algorithm for the gain and timing mismatches in undersampling Time-Interleaved Analog-to-Digital Converter (TI-ADC). A new Least Mean Square (LMS) based detection scheme is proposed to increase convergence speed as well as to enhance the estimate accuracy. Monte Carlo simulations for a four-channel undersampling 60 dB SNR TI-ADC clocked at 2.7 GHz show that SFDR can achieve approximately 90 dB SFDR within the stable point of the channel mismatch coefficients over the first three Nyquist Bands. The proposed architecture is implemented and validated on the Altera FPGA DE4 board. The synthesized design consumes a few percentages of the hardware resources of the FPGA chip and work properly on a Hardware-In-the-Loop emulation framework.

International audience; This paper studies a post-distortion correction technique applied to a nonlinear receiver. The employed technique relies on the assumption that the input signal is bandlimited and uses the signal spreading in the free energy band in order to perform the estimation. The study focuses on three points: the input distortion level impact, filter complexity and quantization. A good sizing of these key parameters is mandatory in order to have an optimized CMOS implementation.

International audience; Abstract—This paper proposes a fully digital calibration oftiming mismatch for undersampling Time Interleaved Analog-to-Digital Converter (TI-ADC) employed in Software Defined Radio (SDR) receivers. The proposed calibration scheme employs an ideal differentiator filter, a Hilbert transform filter and a scaling factor to compute the derivative of the input in any Nyquist Band (NB). The efficiency of the proposed technique is shown using a four-channel undersampling 60 dB SNR TI-ADC clocked at 2.7 GHz. Monte Carlo simulations show SNDR and SFDR improvements ofrespectively,18 dB and 21 dB over the first three NBs.

International audience; This paper presents the design of a low power RC time constant tuning circuit for high linearity 5th order continuous time Delta Sigma modulator used in LTE-Aapplication with 40MHz bandwidth. This auto-tuning system contains an analog integrator, a voltage comparator, and a digital tuning engine performed by a clock generator, a register and a counter which generate a control word that sets a programmable capacitors bank to obtain an RC time constant accuracy better than ±2%. It resolves process variations issues which could result in up to ±30% of RC time constant uncertainty and degrade the Delta Sigma modulators SNDR. The system has been designed in a 65nm CMOS technology with 1.2 V supply voltage and power consumption is less than 200μW.