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The strain impact on integrated circuit performance is investigated by applying a novel indentation technique. The approach aims to investigate stress caused by CPI, particularly highly localized stress/strain with respect to the actual device geometry. Non-destructive elastic indentation is used to induce homogenous stress fields in the vicinity of the test structure by applying a contact with a spherical tip. Strain-sensitive ring oscillator structures manufactured in the 22 nm FDSOI CMOS technology node are designed to monitor the device and simultaneously the NMOS and PMOS strain behavior separately. Complementary FE-simulations provide a deeper insight into the obtained experimental results by transferring them from contact force into the stress/strain space and validating the indentation approach. Relevant layout and indentation dependent parameters are investigated and evaluated. The simulation of the strain induced mobility shift and the comparison with the established correlation verifies the accuracy of the approach. The results provide an insight into package-related stress and resulting transistor degradation, aiming at establishing a versatile tool to estimate the effect of specific real-usage conditions.

The stress related shifts of transistors are measured by precise stress application with a newly designed in-situ four-point bending (4PB) system. A test board including a flip chip packaged test vehicle is loaded with uniaxial stress. The test vehicle contains dedicated ring oscillator circuits fabricated in the 22 nm FDSOI technology node, used to evaluate the effects of thermo-mechanical stress on the characteristics of CMOS devices. Finite element simulation provides insight into the originated stress values in the board, package, and active devices during mechanical loading. Considering the bending caused stress in the devices and the specific layout of the circuits, the directional frequency shifts of the circuits under stress are derived. These shifts are compared with a previous indentation study, which has been developed to induce very localized loads. The comparison aims for verification of the indentation approach to study directional stress related effects as well as very localized effects in chip stacks.

The stress-related change in the characteristics of transistors manufactured in the 22 nm fully depleted silicon on insulator (FDSOI) CMOS technology node is studied with advanced experimental indentation setups. Precisely, NAND and NOR ring oscillator circuits are used to monitor the strain-caused mobility deviations in the silicon transistor channels. Piezoresistive coefficients for strained silicon are calculated from the experimental indentations data using spherical and cylindrical tip geometries. In contrast to spherical tips, the cylindrical indentation tips enable to induce the stress more selectively into a desired direction. To set up the experimental details appropriately, finite element (FE) simulations have been used. Additionally, FE method (FEM) studies are conducted to compute the quantitative strain values in the silicon transistor channels as a function of contact load as well as chip and tip geometries. Using the signal deviations of the RO circuits subjected to strain from spherical and cylindrical indentation, a set of equations using the linearized piezoresistive model are created to determine the directional piezoresistive coefficients.

With decreasing solder volumes and joint sizes, new aspects in electronics packaging occur. Previous publications report porous structures in Cu/Sn microbump interconnects after flux-assisted bonding and storage. The origin and mechanisms of pore formation are still discussed among researchers. In this study, the influence of no-clean flux during isothermal storage is investigated on soldered Cu/SnAg3.5 microbumps with intermetallic compounds. Soldering was carried out on single dies in air atmosphere without cleaning agent at 240 °C for 15 min. Subsequent isothermal storage was performed in air and N2 atmosphere at 240 °C for 1 min, 10 min and 20 min. The microbumps were exposed to flux and flux fumes during isothermal storage. Reference samples were stored separately without any flux contact. The results show pores in samples with flux contact of any kind. Inert atmosphere seems to diminish pore formation. The study reveals different residue appearances on and around the microbumps according to different storage conditions. Reasons for pore formation are also discussed in this study.

Solid-liquid interdiffusion (SLID) interconnectsbased on Cu and Sn-solder are excellent candidates forstacking of Si chips in 3D integration. If the high-temperaturestable intermetallic compound (IMC) Cu3Sn is desired, themanufacturing of the interconnect can be very time consuming(long annealing time for growth of Cu3Sn). In this paper wepropose a method for the accelerated formation of Cu-Cu3Sn-Cu interconnects by selective dissolution of Sn from Cu6Sn5. This leads to a porous network of Cu3Sn. The influence oftemperature, flux and atmosphere onto the pore formation willbe addressed in detail.