Search

The high peak mobility of 509 cm2/ $\text {V}\cdot \text {s}$ of the chemical vapor deposition -grown GeSn pMOSFETs is obtained using 1-nm Ge cap. The Ge cap on GeSn can reduce the scattering of oxide/interface charges and surface roughness for the holes in the GeSn quantum wells. However, the thick cap induces holes in the Ge cap itself, leading lower mobility than GeSn channels. The on current is enhanced by external stress due to the effective mass reduction. The normalized noise power density of the GeSn devices decreases with increasing Ge cap thickness, indicating the carrier number fluctuation and correlated mobility fluctuation are suppressed when the holes are away from interface.

The electron mobility in junctionless (JL) Ge nanowire nFETs with the $\langle 110\rangle $ channel direction is calculated and compared with experimental data. The calculation of the electron mobility is based on the Kubo–Greenwood formula. The wave functions are obtained by solving the self-consistent Poisson–Schrodinger equation. Phonon scattering, surface roughness scattering, and Coulomb scattering (CS) by interface charges and channel charges are considered. Carrier screening on Coulomb charges is calculated using Lindhard’s screening theory. At low electron densities, the JL channels have lower electron mobility than inversion-mode (IM) channels due to CS from channel charges. At high electron densities, CS in JL channels is effectively reduced by screening, resulting in mobility comparable with the IM channels. The L4 electrons have higher mobility than $\text{L}4^\prime $ electrons. Applying uniaxial tensile strain along the channel can lower the energy of L4 valleys to enhance the channel mobility.

The channel cross section geometry and size dependence of the electron mobility in Ge nanowire nFETs is studied by theoretical calculations for devices beyond the 7nm node. circular channels have the highest mobility for wide channels (width>7nm) operating at high overdrive voltage (>0.5V). While diamond-shaped channels have the highest mobility for wide channels operating at low overdrive voltage (

It is the first time that CVD-grown GeSn channels with low thermal budget of 400°C significantly outperforms the Ge channel processed at high thermal budget of 550°C. Low thermal budget is necessary to prevent the Sn loss during the process. Note that only MBE-grown GeSn had large mobility reportedly in the past. Even with high Sn content (9%), the strong photoluminescence is observed from GeSn layers on Ge buffer on 300mm Si (001), indicating the high crystalline quality by CVD epitaxy. Ge cap with significant Δ Ev at Ge/GeSn interface can ensure the gate stack quality, and reduce the scattering of holes in the GeSn quantum wells by oxide/interface charges and surface roughness. However, the mobility is degraded by thick cap due to low hole population in the GeSn wells. The ∼7% mobility enhancement on channel direction is observed using external transverse uniaxial tensile strain of ∼0.11% due to the reduction of effective mass. The mobility of GeSn QW p-MOSFETs increases with decreasing temperature at both high and low inversion carrier density, indicating that the mobility is dominated by phonon scattering. On the contrary, Ge channels are dominated by Coulomb scattering at low inversion carrier density, which has decreasing mobility with decreasing temperature. The normalized noise power density of GeSn p-MOSFETs decreases with increasing Ge cap thickness, reportedly for the first time, indicating that the carrier number fluctuation and correlated mobility fluctuation can be reduced when the carriers are away from interface.

The low channel doping concentrations of 1.2×1019 cm−3 to deplete the channel and the high S/D doping of 1.2×1020 cm−3 to reduce the S/D resistance are achieved simultaneously by selective laser annealing on the same CVD P-doped epi-Ge on SOI without ion implantation. The device with Wfin down to 7 nm, EOT = 2.2 nm, and Lch = 60 nm has Ion = 1146 μA/pm, Ion/Ioff = 2×106, and SS = 95 mV/dec. The Ion can be further boost to 1235 μA/μm with external uniaxial tensile strain of 0.16%. The self-heating effect is responsible in part for such high Ion, because the high device temperature can reduce the dominant impurity scattering in the channel. The increasing mobility with increasing temperature indicates the impurity scattering is dominant. The lower low frequency noise is observed with junctionless (JL) gate-all-around (GAA) FETs than planar inversion mode (INV) devices due to the bulk conduction nature of JL FETs.

Pseudomorphic Ge 0.91 Sn 0.09 on Ge on Si with strong photoluminescence and low defect density is used for p-MOSFET channels. The mobility of Ge 0.91 Sn 0.09 Quantum Well p-MOSFETs are higher than control Ge p-MOSFETs due to hole population in the GeSn wells. The 7.5% mobility enhancement on channel direction is observed using external transverse uniaxial tensile strain (∼0.11%). The highest [Sn] of 9% in the channels grown by CVD, Pt SB S/D, high I on /I off ratio, and strain-enhanced mobility are obtained in this work.

Impact of via-last through-silicon via (TSV) on 28nm node devices is investigated. The stress field of TSV is affected by the back-end-of-line (BEOL) dielectrics. The absolute value of radial stress (|σr|) is different from that of tangential stress (|σθ|) on silicon, which leads to the asymmetric keep-out zone (KOZ). The physics behind the asymmetry is also described. A modified KOZ model considering the asymmetric stress field is proposed and verified by experiment data.

A Ge/GeSn/Ge single quantum well with 5% Sn content was grown by chemical vapor deposition on a Si substrate using Ge2H6 and SnCl4 precursors. External biaxial tensile strain was mechanically applied to the Ge/Ge0.95Sn0.05/Ge quantum well for the photoluminescence measurement. Note that the Ge0.95Sn0.05 layer is still under compressive strain due to the large internal compressive strain of the GeSn, although the external bending produces the tensile strain. The direct emission of tensily strained Ge buffer shifts toward lower energy, while the direct emission of pseudomorphic Ge0.95Sn0.05 quantum well does not have significant shift. The strain-induced energy changes of heavy holes and light holes in the Γ valley are extracted by fitting the photoluminescence spectra. Based on the nonlocal empirical pseudopotential method and the model-solid theory, a type-I band alignment is used for the fitting of photoluminescence spectra. The experimentally extracted band edge shifts from the photoluminescence measurement have good agreement with theoretical calculation.

Type-I, type-II, reverse type-I, and reverse type-II band alignments are found theoretically in strained Ge1−x Sn x (0 ≤ x ≤ 0.3) grown on relaxed Ge1−y Sn y substrates (0 ≤ y ≤ 0.3) using the model-solid theory. The prerequisite bandgaps, and energy difference between the top valence band edge and the average valence band position of GeSn are obtained by the nonlocal empirical pseudopotential method. For the indirect-gap (L valleys) Ge1−x Sn x on relaxed Ge1−y Sn y , the band alignments are type-I and reverse type-I under biaxial compressive strain (x > y) and biaxial tensile strain (x < y), respectively. For the direct-gap (Γ valley) Ge1−x Sn x on relaxed Ge1−y Sn y , the biaxial compressive strain yields type-I and type-II alignment, while the biaxial tensile strain yields reverse type-I and reverse type-II alignments.