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Achieving high latch-up immunity is critical for power-rail electrostatic discharge (ESD) clamp circuits in high-voltage (HV) integrated circuit products. To investigate how shunt resistance affects the transmission line pulsing current–voltage characteristics of resistance-triggered stacked silicon controlled rectifiers (SCRs), a lateral SCR (LSCR) and a modified LSCR were combined in several SCR stacked structures with various shunt resistances. Compared with in tradition stacked ESD cells, the snapback margin of the SCRs does not expand and can even be reduced. A high holding voltage of 33.4 V is achieved using the resistance-triggered stacked SCR technique in a $0.11~\mu \text{m}$ 32-V HV process. A trigger voltage of approximately 51 V and a failure current of 3.3 A is achieved in this experiment. According to theorem analysis based on a voltage decoupling equation, the minimum trigger voltage can probably be further reduced to 46 V by using the resistance-triggered stacked SCR technique. This paper can offer a simple guideline for designing ESD protection circuit using the resistor-triggered SCRs stacking structure.

In this study, we demonstrated a p -type and n -type SnO TFTs on flexible polyimide substrate. The fabricated p -type SnO TFT showed a high $I_{\rm on}/ I_{\rm off}$ of $ \text{5.7}\, \times \,\text{10}^{5}$ and a high $\mu _{{\rm{FE}}}$ of ${\text{10.7 cm}}^{2}\,{\text{V}}^{-1}\,{\text{s}}^{-1}$ . Through optimizing the oxygen plasma condition, the n -type channel TFT transfered from prime p -type channel exhibits excellent characteristics, including a high on/off current ratio of $\rm{6.6}\,\times\,10^{3}$ , a low threshold voltage of −0.13 V, and a very high field-effect mobility of ${\text{28 cm}}^{2}\,{\text{V}}^{-1}\,{\text{s}}^{-1}$ . This proposed low-temperature oxygen plasma treatment shows the potential in simplification of TFT process that can achieve n -type and p -type TFTs under the same device process.

In this brief, we reported a ferroelectric versatile memory with strained-gate engineering. The versatile memory with high-strain-gate showed a >40% improvement on ferroelectric hysteresis window, compared to low-strain case. The high compressive stress induced from high nitrogen-content TaN enhances monoclinic-to-orthorhombic phase transition to reach stronger ferrolectric polarization and lower depolarization field. The versatile memory featuring ferroelectric negative capacitance exhibited excellent transfer characteristics of the sub-60-mVdec subthreshold swing, ultralow off-state leakage of $\mu \text{m}$ and $> 10^{\mathsf {8}}$ on/off current ratio. Furthermore, the ferroelectric versatile memory can be switched by ±5 V under 20-ns speed for a long endurance cycling (~1012 cycles). The low-power operation can be ascribed to the amplification of the surface potential to reach the strong inversion and fast domain polarization at the correspondingly low program/erase voltages.

This paper describes a high-performance p -type tin-oxide (SnO) thin film transistor (TFT) using fluorine plasma treatment on the SnO active channel layer. The influence of fluorine plasma treatment for this p -type SnO TFT device was also investigated. Through tuning the fluorine plasma power treated on the SnO active channel layer at low temperature, the optimal p -type SnO TFT device exhibits a very high on/off current ratio of 9.6 × 10 6 , a field-effect mobility of 2.13 cm 2 V −1 s −1 , a very low subthreshold swing of 106 mV/dec and an extremely low off-state current of 1 pA at a low driven voltage of p -type SnO channel that reduced crystallized channel roughness and passivated oxygen vacancies and interface traps. This high-performance p -type SnO TFT device using fluorine plasma treatment on the active channel shows great promise for future high-resolution and high-speed display applications.

We reported the characteristics of p-type tin-oxide (SnO) thin film transistors (TFTs) upon illumination with visible light. Our p-type TFT device using the SnO film as the active channel layer exhibits high sensitivity toward the blue-light with a high light/dark read current ratio (Ilight/Idark) of 8.2 × 103 at a very low driven voltage of

In this paper, we investigated the bipolar conduction mechanism in thin-film transistors (TFTs) with oxygen plasma treatment on tin-oxide channel. The optimized p-type thin-oxide TFTs showed an on/off ratio of ${>}{\hbox{10}}^{4}$ , a threshold voltage of $-$ 1.05 V, and a field-effect mobility of ${\hbox{2.14}}\ {\hbox{cm}}^{2}{\cdot}{\hbox{V}}^{-1}{\cdot}{\hbox{s}}^{-1}$ . By increasing the exposure time of oxygen plasma, excess oxygen was incorporated to thin-oxide channel and converted thin monoxide to oxygen-rich n-type thin dioxide, which in turn led to n-type operation. It indicated that oxygen plasma was the critical factor to determine oxygen concentration, oxygen vacancies, metal ions and channel polarity. This proposed oxygen-content tuning through plasma treatment approach shows great promise in simplification of TFT process that can achieve n-type and p-type TFTs under the same device process.

This paper reported the IGZO and IZO thin-film transistor (TFT) with titanium-oxide semiconductor as channel capping layer. After the ${\hbox{TiO}}_{x}$ Gettering process, the oxygen vacancies in IGZO channel were successfully modified to maximize the carrier concentration and device mobility. The superior transfer characteristics included a low sub-threshold swing of 79 mV/decade, a very high mobility of ${\hbox{68}}~{\hbox{cm}}^{2}/{\hbox{V}}{\cdot}{\hbox{s}}$ , and good on/off-current ratio of ${\hbox{5.61}}\times {\hbox{10}}^{6}$ . However, the IZO channel with nano-crystallized grains and without Ga atom doping showed unfavorable transistor characteristics. In addition to apparently degraded transfer properties, the spontaneously oxidized ${\hbox{TiO}}_{x}$ capping layer also lead to an increase of channel parasitic resistance that limits the output driving current. Therefore, we believe that the existence of Ga–O bonds among IGZO channel would be helpful to stabilize oxygen diffusion behavior and electric structure during Gettering process.

This letter reports on a tin oxide (SnO) thin-film transistor (TFT) with p-type conduction that uses aluminum (Al) doping in the SnO active channel layer. Performance enhancements were further achieved by applying fluorine plasma treatment on the p-type Al-doped SnO channel layer. The effects of the fluorine plasma treatment were also investigated.By tuning the power of the fluorine plasma treatment on the p-type Al-doped SnO channel layer, the optimal TFT device showed a very high on/off current ratio of 2.58×10 6 and a low threshold swing of 174 mV/decade, which could be attributed to the passivation effect of the plasma fluorination on the dominant donor-like traps at the SnO/HfO 2 interface, as reflected by the suppression of the hysteresis phenomenon, the low density of interface traps, and the small subthreshold swing. The results indicate that the p-type Al-doped SnO TFT device with fluorine plasma treatment has considerable potential for application in future high-performance displays.

In this work, we investigated the photocapacitive effect of the metal-ferroelectric-insulator-semiconductor capacitors under illumination. The photocapacitive effect is mainly caused by light photon excitation, contributed from the variation of depletion charge. We suggested that the ferroelectric domains are affected by defect dipole charges formed by the interface trapped charges to lead to the variation of depletion capacitance.

In this work, we demonstrate a new concept for realizing high threshold voltage (V th ) E-mode GaN power devices with high maximum drain current (I D, max ). A gate stack ferroelectric blocking film with charge trap layer, achieved a large positive shift of V th . The E-mode GaN MIS-HEMTs with high V th of 6 V shows I D, max 720 mA/mm. The breakdown voltage is above 1100 V.

The electrical instability behaviors of amorphous indium-gallium-zinc oxide thin-film transistors with and without titanium sub-oxide passivation layer were investigated under light illumination in this study. For the unpassivated IGZO TFT device, in contrast with the dark case, a noticeable increase of the sub-threshold swing was observed when under the illumination environment, which can be attributed to the generation of ionized oxygen vacancies within the α-IGZO active layer by high energy photons. For the passivated TFT device, the much smaller SS of ~70 mV/dec and high device mobility of >100 cm2/Vs at a drive voltage of 3 V with negligible degradation under light illumination are achieved due to the passivation effect of n-type titanium sub-oxide semiconductor, which may create potential application for high-performance display.

In this work, we proposal a ferroelectric domain to enhance program/erase/read efficiency of conventional charge-trapping nonvolatile memory. The ferroelectric-domain-dominated HfZrO/HfON memory shows the better subthreshold characteristics than control charge-trapping structure (HfO 2 /HfON). Additionally, the memory speed with ferroelectric polarization (∼800ns) is more than three orders of magnitude faster than that of control trapping type.

In this work, we report a ferroelectric versatile memory (FE-VM) with strained-gate engineering. The memory window of high strain case was improved by ∼47% at the same ferroelectric thickness, which agrees with the increase of orthorhombic crystallinity. Based on a reliable first principle calculation (FPC), we clarify that the gate strain accelerates the phase transformation from metastable monoclinic to orthorhombic and thus largely enhances the ferroelectric polarization without increasing dielectric thickness. On the other hand, the orthorhombic FE-AFE phase transition plays a key role in realizing negative capacitance (NC) effect at high gate electric field. This 1T strained-gate FE-VM with ferroelectric NC achieves a sub-60-mVdec subthreshold swing (SS) over ∼4 decade of I D to provide a 1∼10 fA/µm I off and >108 I on /I off ratio, which allows for a fast 20-ns P/E switching during 1012 cycling endurance.

Incorporating a charge-trapped ZrSiO with ferroelectric HfZrO dielectrics, we demonstrated a gate-injection versatile memory with sub-60mV/dec subthreshold swing (SS) and large threshold voltage window (Δ Vt) of >2V under a fast 20-ns speed. Moreover, it is revealed that the local defects at ZrSiO/HfZrO interface affect the ferroelectric negative capacitance tuning and thus increases the variability of Vt and SS during 1012 cycling endurance.

In this work, we investigated the negative capacitance behavior of novel ferroelectric versatile memory with low-voltage-driven and fast ferroelectric switching. The combined storage mechanism strengthened the stability of ferroelectric polarization by interface aligned dipoles. The simulation results of first principle calculation indicated that the monoclinic-like orthorhombic phase of ferroelectric hafnium oxide facilitated the occurrence of S-shaped negative capacitance behavior. Furthermore, the control of phase transition may affect ferroelectric property and negative capacitance effect during program and erase states.

In this work, we report a ferroelectric memory with strained-gate engineering. The memory window of the high strain case was improved by ∼71% at the same ferroelectric thickness. The orthorhombic phase transition (from ferroelectric to anti-ferroelectric transition) plays a key role in realizing negative capacitance effect at high gate electric field. Based on a reliable first principles calculation, we clarify that the gate strain accelerates the phase transformation from metastable monoclinic to orthorhombic and thus largely enhances the ferroelectric polarization without increasing dielectric thickness. This ferroelectric strain technology shows the potential for emerging device application.

High electrostatic discharge (ESD) protection robustness and good transient-induced latchup immunity are two important issues for high voltage integrate circuit application. In this study, we report a high-voltage-n-type-field (HVNF) implantation to act as the body ties blocking layer in segmented topology silicon-controlled-rectifier (SCR) structure in 0.11 µm 32 V high voltage process. This body ties blocking layer eliminate the elevated triggered voltage in segmented technique. Using a large resistance as shunt resistor in resistor assisted triggered SCRs stacking structure, the double snapback phenomenon is eliminate. The series SCR could be decoupled a sufficient voltage drop to turned-on when a very low current flow through the shunt resistor. The holding voltage and the failure current of 22 V and 3.4 A are achieved in the best condition of segmented topology SCR stacking structure, respectively. It improves the latchup immunity at high voltage ICs application. On the other hand, the triggered voltage almost keep the same value which is identical to SCR single cell without using segmented topology.