Author: "Cyril Buttay" / Topic: 0103 physical sciences - Searchworks@Jio Institute Digital Library Search Results

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48 results on '"Cyril Buttay"'

1. Threshold voltage instability in SiC MOSFETs as a consequence of current conduction in their body diode

Author: Oriol Aviño Salvado, Stéphane Lefebvre, Denis Labrousse, Hervé Morel, Cyril Buttay, Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), and Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)
Subjects: Materials science, 02 engineering and technology, 01 natural sciences, law.invention, law, Current conduction, 0103 physical sciences, MOSFET, 0202 electrical engineering, electronic engineering, information engineering, Electrical and Electronic Engineering, Power MOSFET, Safety, Risk, Reliability and Quality, Diode, 010302 applied physics, business.industry, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 020208 electrical & electronic engineering, PIN diode, Schottky diode, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Threshold voltage, Optoelectronics, business, Antiparallel (electronics)
Abstract: International audience; An antiparallel PiN diode is present in the structure of the SiC Power MOSFET. For simplicity, increased module current ratings, and cost reasons, it sometimes may be preferable to use this diode rather than to add an external Schottky diode to the MOSFET. However, SiC PiN diodes are sensitive to defects in the SiC crystal, and their performance can degrade rapidly. In this paper, we assess the effect of several stresses on the characteristics of a SiC MOSFET, focusing on the stresses which involve the body diode. We demonstrate that using the body diode does not degrade its performances. However, it may produce a noticeable shift in the threshold voltage of the MOSFET. While this behaviour is observed for MOSFETs from one manufacturer, it is not exhibited for others, which indicates that it may be a consequence of some particular design or manufacturing parameters.
Published: 2018
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2. SiC MOSFETs robustness for diode-less applications

Author: Denis Labrousse, Hervé Morel, Stéphane Lefebvre, Marwan Ali, C. Cheng, Oriol Avino-Salvado, Cyril Buttay, Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS), and Safran Tech
Subjects: Silicon, Computer science, intrinsic diode, chemistry.chemical_element, robustness, 02 engineering and technology, 01 natural sciences, Silicon Carbide (SiC), MOSFET, Robustness (computer science), Power electronics, 0103 physical sciences, Electronic engineering, Electrical and Electronic Engineering, threshold voltage, Diode, 010302 applied physics, reliability, oxide traps, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 021001 nanoscience & nanotechnology, Threshold voltage, diode-less, chemistry, 0210 nano-technology
Abstract: International audience; Silicon-Carbide (SiC) technology presents several advantages over silicon for power electronics applications, such as lower losses. However, SiC technology is not totally mature, and some reliability problems remain. This paper studies the robustness of SiC MOSFETs in the case of diode-less applications and the associated phenomena, such as gate oxide degradation. Several devices were stressed under conditions of inductive switching and inverse current conduction. These devices were periodically characterised. As a result, a threshold voltage shift was observed in the MOSFET, with a dependence on the duty cycle of the transistor. On the contrary, no significant degradation of the internal P-N junction of the transistor was observed.
Published: 2018
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3. An investigation of current distribution over four GaN HEMTs in parallel configurations

Author: Jean-François Mogniotte, Stephane Azzopardi, Bruno Allard, Charles Joubert, Hervé Morel, Cyril Buttay, Thilini Wickramasinghe, Pascal Bevilacqua, Thanh-Long Le, Christian Martin, Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), and Safran Tech
Subjects: Materials science, Spice, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, High-electron-mobility transistor, 01 natural sciences, parallel, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Parasitic extraction, 010302 applied physics, business.industry, GaN HEMT, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 020208 electrical & electronic engineering, high frequency, Dissipation, Threshold voltage, CVR, Optoelectronics, Coaxial, business, Index Terms-current balancing, Shunt (electrical), Voltage
Abstract: International audience; GaN HEMTs are desirable for parallel configurations due to (i) relatively steady threshold voltage over a wide temperature range and (ii) the positive temperature coefficient of their on-resistances. However, their operations are sensitive to the circuit parasitics and dissimilarities between devices. This paper investigates the current distribution among four parallel GaN HEMTs, considering two symmetrical circuit layouts of a power cell. For switching experiments, 25 V input voltage and a maximum load current of 7 A are considered. Current through each GaN HEMT is measured using stud-type, high bandwidth, coaxial shunt current sensors (CSs). The same circuit is further investigated by removing the current sensors. A second circuit is built by eliminating the CSs as to achieve high current. The circuit is tested up to 27 A/ 80 V. Here, only the voltage measurements and thermal images are obtained. Thermal images are used to evaluate the power dissipation between the four HEMTs and to correlate them with the current measurements. Further, the current waveforms are simulated using a SPICE model. The parasitic elements of the layout are calculated by ANSYS Q3D.
Published: 2019
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4. Sintered-Silver Bonding of High-Temperature Piezoelectric Ceramic Sensors

Author: Remi Robutel, Jianfeng Li, Stanislas Hascoet, Justine Billore, Cyril Buttay, SuperGrid Institute SAS, Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Faculty of Engineering [Nottingham], and University of Nottingham, UK (UON)
Subjects: 010302 applied physics, Materials science, Piezoelectric sensor, 020208 electrical & electronic engineering, Sintering, 02 engineering and technology, Nanoindentation, 01 natural sciences, Focused ion beam, Piezoelectricity, Industrial and Manufacturing Engineering, Electronic, Optical and Magnetic Materials, [SPI]Engineering Sciences [physics], visual_art, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, visual_art.visual_art_medium, Shear strength, Ceramic, Electrical and Electronic Engineering, Composite material, Porosity
Abstract: International audience; Silver sintering is used to bond five components together, in order to form a piezoelectric sensor. A description is provided of the preparation of these components, and of the manufacturing steps, which are carried out at a low temperature (280 °C). The resulting sensor assemblies are then characterized: cross-sectional views show that the silver layer has a very dense structure , with less than 1 % porosity, although further focused-ion beam investigations show that this porosity is closer to 15 %. The shear strength is approximately 30 MPa. The Young's modulus of the silver bondline is measured using nanoindentation, and is found to be comparable with that of bulk silver (56.6 GPa). Finally, a silver-sintered sensor is compared with a sensor bonded using conventional techniques, showing that an improvement in sensitivity by a factor of more than 3 is achieved.
Published: 2017
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5. Surge current capability of ultra-wide-bandgap Ga2O3 Schottky diodes

Author: Ming Xiao, Christina DiMarino, Hiu Yung Wong, Boyan Wang, Yuhao Zhang, Cyril Buttay, Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), San Jose State University [San José] (SJSU), and Virginia Polytechnic Institute and State University [Blacksburg]
Subjects: 010302 applied physics, Materials science, Band gap, business.industry, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 020208 electrical & electronic engineering, Spice, Schottky diode, 02 engineering and technology, Condensed Matter Physics, Chip, 01 natural sciences, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Thermal conductivity, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, Wafer, Transient (oscillation), Electrical and Electronic Engineering, Current (fluid), Safety, Risk, Reliability and Quality, business
Abstract: International audience; β-Ga 2 O 3 is an emerging ultra-wide-bandgap semiconductor material offering superior power material limits over Si, SiC, and GaN as well as the availability of large-diameter wafers growing from its own melt. However, β-Ga 2 O 3 devices performance may be limited by the relatively poor thermal conductivity of the material. In this paper, we investigate the behavior of β-Ga 2 O 3 Schottky diodes in the condition of forward current surge to explore their electro-thermal ruggedness and the related thermal management. An analytical electro-thermal device model is calibrated with experimental devices and TCAD simulations. Then this device model is incorporated into a SPICE electro-thermal network model, which is used to simulate the device temperature rise during the surge transient, considering various device and packaging configurations (i.e. various chip thicknesses and chip orientations). It is found that provided heat is removed from the junction side, a β-Ga 2 O 3 Schottky diode offers a robustness to surge current exceeding that of a SiC Schottky diode. The low thermal conductivity of β-Ga 2 O 3 is found to be overcome by the enhanced heat extraction from junction-side cooling, as well as by the intrinsically small temperature dependence of the on-resistance (and conduction loss) of β-Ga 2 O 3 devices.
Published: 2020
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6. Application of the PCB-Embedding Technology in Power Electronics – State of the Art and Proposed Development

Author: Florent Morel, Stefan Mollov, Nicolas Degrenne, Roberto Mrad, Remy Caillaud, Cyril Buttay, Christian Martin, Johan Le Lesle, Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Mitsubishi Electric R&D Centre Europe [France] (MERCE-France), and Mitsubishi Electric [France]
Subjects: 010302 applied physics, business.industry, Computer science, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 02 engineering and technology, Converters, 01 natural sciences, 7. Clean energy, Automation, Design for manufacturability, Printed circuit board, Power electronics, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Microelectronics, Parasitic extraction, business, Engineering design process
Abstract: International audience; The embedding of components in Printed Circuit Board (PCB) material is an attractive solution to improve the performance of power converters in the 1 W–100 kW range by increasing the power density (exploitation of unused volume in the PCB), reducing circuit parasitics (strip-line approach to current distribution, shorter interconnects), and improving manufacturability (rationalization of the manufacturing process, automation). This paper presents a review of the embedding technologies, with a special focus on power components (passive, active) and thermal management. The second part of the article is dedicated to the design process, and proposes a new design approach, inspired from microelectronics. The ambition is to simplify the design process by using " design toolkits ". These toolkits would provide the designer with elements such as design rules, libraries or models. The objective is to enable automatic design validation, and to ensure the design can be produced directly.
Published: 2018
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7. Design, manufacturing and characterization of printed circuit board embedded inductors for power applications

Author: Florent Morel, Christian Martin, Roberto Mrad, Johan Le Lesle, Cyril Buttay, Nicolas Degrenne, Stefan Mollov, Remy Caillaud, Mitsubishi Electric R&D Centre Europe [France] (MERCE-France), Mitsubishi Electric [France], Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), and Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)
Subjects: 010302 applied physics, Computer science, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Hardware_PERFORMANCEANDRELIABILITY, Converters, Inductor, 01 natural sciences, Manufacturing cost, Inductance, Printed circuit board, Magnetic core, Electromagnetic coil, 0103 physical sciences, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Host (network)
Abstract: International audience; The Printed-Circuit-Board (PCB) technology is attractive for power electronic systems as it offers a low manufacturing cost for mass production. Power inductors are large and complex to manufacture, because they usually are custom components which must be wound individually. Inductors based on PCB technology can reduce the complexity and cost while using a wasted space (the thickness of said PCB). In this paper, a procedure to design such inductors is summarized , with a focus on inductors intended to be implemented in converters in the 100-1000 W range. The main contribution of this paper is the description of the manufacturing process : the inductors use PCB to host their magnetic core while their winding is made by patterning the PCB copper layers and using copper vias. In addition, new experimental results are presented : the prototypes are electrically characterized, and the results are discussed to present the advantages and drawbacks of this technology, as well as the remaining open questions.
Published: 2018
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8. Protruding Ceramic Substrates for High Voltage Packaging Of Wide Bandgap Semiconductors

Author: Hugo Reynes, Hervé Morel, Cyril Buttay, SuperGrid Institute SAS, Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), and Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)
Subjects: 010302 applied physics, Permittivity, Materials science, business.industry, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Wide-bandgap semiconductor, High voltage, 02 engineering and technology, 01 natural sciences, Substrate (building), visual_art, 0103 physical sciences, Partial discharge, 0202 electrical engineering, electronic engineering, information engineering, visual_art.visual_art_medium, Optoelectronics, Ceramic, business, Layer (electronics), Voltage
Abstract: International audience; —Wide bandgap semiconductors enable high voltage (10 kV and more) switches. As a consequence, new packaging solutions are required to prepare the ground for such devices. The metallized ceramic substrate is a well-known and established technology for voltages up to 3.3kV, but it exhibits some weaknesses at higher voltages: due to its manufacturing process, the profile of the metallization is sharp and induces a reinforcement of the electric field at the " triple point " area (where the ceramic, the conductor and the encapsulating material meet), which can lead to Partial Discharges (PD), eventually causing a failure of the module. In this paper, we present a new substrate structure, where the triple point is moved away to an area where the electric field is lower. In this structure, the ceramic is machined to form protrusions, and round-edge metallizations are brazed on top. The design of the substrate, based on finite-elements is described, and calculations show that a 1 mm-thick AlN layer should be sufficient to withstand 10 kV. The manufacturing process of this substrate is presented. The test results demonstrate the superiority of this new solution, with a partial discharge inception voltage increased by 38 %.
Published: 2017
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9. Robustness of SiC MOSFET under avalanche conditions

Author: Hervé Morel, Ilyas Dchar, Marion Zolkos, Cyril Buttay, SuperGrid Institute SAS, Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), and ITE Supergrid Institute (financement investissement d'avenir)
Subjects: Materials science, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Series and parallel circuits, 01 natural sciences, Hardware_GENERAL, 0103 physical sciences, MOSFET, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Failure mechanism, SiC MOSFET, 010302 applied physics, Avalanche diode, business.industry, 020208 electrical & electronic engineering, Bipolar junction transistor, Electrical engineering, Semiconductor device, Reliability, Avalanche breakdown, [SPI.TRON]Engineering Sciences [physics]/Electronics, High-voltage direct current, Parasitic BJT, business, Critical energy, Voltage
Abstract: International audience; In high voltage direct current (HVDC) converters, a series connection of semiconductor devices is often used to achieve the desired blocking voltage. In such configuration, an unequal voltage sharing may drive one or more devices into avalanche breakdown, eventually causing the failure of the entire group of devices. This paper presents the experimental evaluation of SiC MOSFETs from different manufacturers operated in avalanche. A setup was developed to test the devices under such condition. The reliability of SiC MOSFETs have been compared. To correlate the experimental results with the failure mechanism, the MOSFETs were decapsulated to identify the failure sites on the SiC dies. Examination results show that for some tested devices, the failure occurs at the metallization source of the die, and results in a short circuit between all three terminals of the MOSFETs. Furthermore, it has been found that the parasitic BJT latch up and the intrinsic temperature limit are the main failure mechanisms for these devices.
Published: 2017
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10. Fabrication and characterization of a planar interleaved micro-transformer with magnetic core

Author: A. Siblini, K. Youssouf, S. Capraro, M.H. Bechir, Cyril Buttay, J.P. Chatelon, Faouzi Kahlouche, Jean Jacques Rousseau, Laboratoire Telecom Claude Chappe (LT2C), Université Jean Monnet [Saint-Étienne] (UJM)-Ecole d'ingenieurs Telecom Saint Etienne, Laboratoire Hubert Curien [Saint Etienne] (LHC), Institut d'Optique Graduate School (IOGS)-Université Jean Monnet [Saint-Étienne] (UJM)-Centre National de la Recherche Scientifique (CNRS), Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), and Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)
Subjects: 010302 applied physics, Fabrication, Materials science, HFSS, business.industry, General Engineering, Electrical engineering, Yttrium iron garnet, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, [SPI.TRON]Engineering Sciences [physics]/Electronics, law.invention, Surface micromachining, chemistry.chemical_compound, Magnetic core, chemistry, Electromagnetic coil, law, Magnet, 0103 physical sciences, Optoelectronics, 0210 nano-technology, business, Transformer
Abstract: International audience; This paper presents the design, the fabrication and the characterization of a planar interleaved micro-transformer with an Yttrium Iron Garnet (YIG) core. The design of this micro-transformer and the manufacturing steps are presented. HFSS software is used for the conception and the simulation of the interleaved magnetic micro-transformer. It is composed of two identical windings. A bottom magnetic core is used to improve the integrated transformer performances. To form the windings, we have used a surface micromachining process. We have also used a negative photoresist (SU-8) as an insulating layer and as support for the fabrication of a bridge to connect the central end of the coils to the ground shield. The micro-transformer have been characterized with impedance meter up to 100 MHz, and completed to 1 GHz using vector network analyzer.
Published: 2014
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11. Thermal Stability of Silicon Carbide Power JFETs

Author: Dominique Bergogne, Hervé Morel, Florent Morel, Remy Ouaida, Cyril Buttay, Christophe Raynaud, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), and Project THOR, funded by Euripides and Catrene
Subjects: JFET, silicon carbide (SiC), Materials science, Thermal runaway, thermal runaway, Thermal resistance, 02 engineering and technology, 01 natural sciences, chemistry.chemical_compound, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Silicon carbide, Thermal stability, Electrical and Electronic Engineering, 010302 applied physics, business.industry, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 020208 electrical & electronic engineering, Electrical engineering, Thermal conduction, Electronic, Optical and Magnetic Materials, Power (physics), chemistry, Optoelectronics, business, AND gate
Abstract: 9 pages; International audience; Silicon carbide (SiC) JFETs are attractive devices, but they might suffer from thermal instability. An analysis shows that two mechanisms could lead to their failure: the loss of gate control, which can easily be avoided, and a thermal runaway caused by the conduction losses. Destructive experimental tests performed on a dedicated system show that the latter mechanism is more severe than initially expected. A low thermal resistance and gate driver equipped with protections systems are thus required to ensure safe operation of the SiC JFETs.
Published: 2013
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12. Migration issues in sintered-silver die attaches operating at high temperature

Author: Pascal Bevilacqua, Cyril Buttay, Bruno Allard, Raphaël Riva, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Ampère, Département Energie Electrique (EE), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Euripides-Catrene, and European Project
Subjects: Materials science, power electronics packaging, silver sintering, Sintering, Nanotechnology, 02 engineering and technology, migration, 01 natural sciences, Die (integrated circuit), high temperature, chemistry.chemical_compound, Parylene, Electric field, 0103 physical sciences, Thermal, Electrical and Electronic Engineering, Composite material, Safety, Risk, Reliability and Quality, 010302 applied physics, Moisture, parylene, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, chemistry, Melting point, 0210 nano-technology, Short circuit
Abstract: International audience; Silver sintering is a promising alternative to high melting point (HMP) solders which contain lead. Indeed, it offers better thermal and electrical properties, and can operate at higher temperature. However, silver tends to migrate in presence of electric field, oxygen (or moisture) and high temperature, causing short circuits. In this paper, we assess the extend of this issue, and we evaluate the protective effect of a thin layer of parylene. It is shown that silver migration occurs rapidly (tens to hundred of hours at 300°C), but that parylene offers a good mitigation of this issue.
Published: 2013
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13. Die attach using silver sintering. Practical implementation and analysis

Author: Wissam Sabbah, Cyril Buttay, Régis Meuret, Hervé Morel, Dominique Planson, Amandine Masson, Raphaël Riva, Stephane Azzopardi, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Laboratoire de l'intégration, du matériau au système (IMS), Centre National de la Recherche Scientifique (CNRS)-Institut Polytechnique de Bordeaux-Université Sciences et Technologies - Bordeaux 1, SAFRAN, Grp Hispano Suiza, SAFRAN Group, FRAE projet EPAHT, and Université Sciences et Technologies - Bordeaux 1-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS)
Subjects: 010302 applied physics, Materials science, power electronics packaging, silver sintering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 020208 electrical & electronic engineering, Metallurgy, dBc, Sintering, 02 engineering and technology, Substrate (printing), 01 natural sciences, Silver nanoparticle, Die (integrated circuit), high temperature, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Melting point, Electrical and Electronic Engineering, Silver particles
Abstract: National audience; Silver sintering is a promising alternative to high melting point (HMP) solders which contain lead. Indeed, it offers better thermal and electrical properties, and can operate at higher temperature. Currently, several implementations of this technique are available, based on various silver particles sizes and sintering additives. This paper presents a review of the different implementations, and gives practical details about one of them, based on silver nanoparticles. One specific aspect is highlighted: the metal finish of the DBC substrate. It has a major impact on the quality of the sintered joint: with some finishes, the adhesion is excellent (more than 50 MPa), while it is poor with some others (lower than 10 MPa).
Published: 2013
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14. Lifetime of power electronics interconnections in accelerated test conditions: High temperature storage and thermal cycling

Author: Cyril Buttay, Wissam Sabbah, Hervé Morel, L. Theolier, Oriol Avino-Salvado, F. Arabi, Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Fiabilité / Puissance, Laboratoire de l'intégration, du matériau au système (IMS), Université Sciences et Technologies - Bordeaux 1-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS)-Université Sciences et Technologies - Bordeaux 1-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS), PIA GENOME PREMICES, and Centre National de la Recherche Scientifique (CNRS)-Institut Polytechnique de Bordeaux-Université Sciences et Technologies - Bordeaux 1-Centre National de la Recherche Scientifique (CNRS)-Institut Polytechnique de Bordeaux-Université Sciences et Technologies - Bordeaux 1
Subjects: Thermal shock, Materials science, chemistry.chemical_element, 02 engineering and technology, Temperature cycling, 01 natural sciences, Die (integrated circuit), [SPI]Engineering Sciences [physics], Aluminium, Power electronics, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electrical and Electronic Engineering, Composite material, Safety, Risk, Reliability and Quality, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, Electrical engineering, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Shock (mechanics), chemistry, Power module, business, High temperature storage
Abstract: International audience; We investigate the effect of three testing conditions (thermal shock, Rapid Temperature Changes – RTC – and high temperature storage) on the interconnects of a power electronic module. In particular, the mechanical strength of thick aluminium wirebonds is investigated and shows that while it is not affected by storage at 230 °C, it is much more sensitive to thermal cycling. Shock tests are found to be especially severe, despite having a smaller temperature swing than RTC. Regarding the die attach, no noticeable reduction in mechanical strength is found, regardless of the ageing conditions, and despite clear micro-structural evolutions.
Published: 2017
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15. Characterization of materials and their interfaces in a direct bonded copper substrate for power electronics applications

Author: O. Dezellus, Laurent Gremillard, A. Ben Kabaar, Cyril Buttay, Anthony Gravouil, Rafael Estevez, Science et Ingénierie des Matériaux et Procédés (SIMaP ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Laboratoire des Multimatériaux et Interfaces (LMI), Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS), Laboratoire de Mécanique des Contacts et des Structures [Villeurbanne] (LaMCoS), Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS), Matériaux, ingénierie et science [Villeurbanne] (MATEIS), Université de Lyon-Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS), and Institut Carnot Lyon I@L, projet SuMeCe
Subjects: Digital image correlation, Materials science, Mechanical characterization, Ceramic substrates, chemistry.chemical_element, 02 engineering and technology, Temperature cycling, 01 natural sciences, [SPI]Engineering Sciences [physics], Power electronics, 0103 physical sciences, Electronic engineering, Ceramic, Electrical and Electronic Engineering, Composite material, Safety, Risk, Reliability and Quality, 010302 applied physics, dBc, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Copper, Atomic and Molecular Physics, and Optics, Finite element method, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Characterization (materials science), chemistry, visual_art, visual_art.visual_art_medium, 0210 nano-technology
Abstract: International audience; Direct Bonded Copper (DBC) are produced by high temperature (>1000 °C) bonding between copper and a ceramic (usually alumina). They are commonly used in power electronics. However, their reliability when exposed to thermal cycling is still an issue, that could be addressed by advanced numerical simulations. This paper describes the identification of the parameters for a numerical model that uses finite elements with cohesive zones. This identification is based on careful mechanical characterization of all components of the DBC (ceramic, copper and interface) using an innovative approach based on image correlation.
Published: 2017
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16. Thermal Runaway Robustness of SiC VJFETs

Author: Cyril Buttay, Dominique Bergogne, Raphaël Riva, Florent Morel, Christophe Raynaud, Remy Ouaida, Hervé Morel, Anh Dung Hoang, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), and Ampère, Publications
Subjects: JFET, Materials science, Thermal runaway, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 7. Clean energy, 01 natural sciences, law.invention, chemistry.chemical_compound, law, Robustness (computer science), Power electronics, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Water cooling, Silicon carbide, General Materials Science, Power Electronics, 010302 applied physics, business.industry, Mechanical Engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 020208 electrical & electronic engineering, Transistor, Electrical engineering, Condensed Matter Physics, Engineering physics, High-Temperature, chemistry, Mechanics of Materials, Thermal Runaway, business, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract: International audience; Silicon Carbide (SiC) Junction-Field Effect Transistors (JFETs) are attractive devices for power electronics. Their high temperature capability should allow them to operate with a reduced cooling system. However, experiments described in this paper conclude to the existence of runaway conditions in which these transistors will reach destructive temperatures.
Published: 2013
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17. Avalanche robustness of SiC Schottky diode

Author: Hervé Morel, Cyril Buttay, Ilyas Dchar, SuperGrid Institute SAS, Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), and Supergrid Institute
Subjects: Engineering, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, [SPI]Engineering Sciences [physics], 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Hardware_INTEGRATEDCIRCUITS, Transient-voltage-suppression diode, Electrical and Electronic Engineering, Safety, Risk, Reliability and Quality, Diode, 010302 applied physics, Avalanche diode, business.industry, 020208 electrical & electronic engineering, Electrical engineering, Schottky diode, High voltage, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Avalanche breakdown, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Single-photon avalanche diode, Voltage spike, Optoelectronics, business
Abstract: International audience; Reliability is one of the key issues for the application of Silicon carbide (SiC) diode in high power conversion systems. For instance, in high voltage direct current (HVDC) converters, the devices can be submitted to high voltage transients which yield to avalanche. This paper presents the experimental evaluation of SiC diodes submitted to avalanche, and shows that the energy dissipation in the device can increase quickly and will not be uniformly distributed across the surface of the device. It has been observed that failure occurs at a fairly low energy level (
Published: 2016
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18. Two Comparison-Alternative High Temperature PCB-Embedded Transformer Designs for a 2 W Gate Driver Power Supply

Author: Dushan Boroyevich, Marwan Ali, Bruno Allard, Nicolas Quentin, Rolando Burgos, Cyril Buttay, Rémi Perrin, Bingyao Sun, Center for Power Electronics Systems - CPES (Blacksburg, USA), Virginia Polytechnic Institute and State University [Blacksburg], Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Sagem - SAFRAN Gr., SAFRAN Group, and IEEE
Subjects: Isolation transformer, Engineering, inter-capacitance, Switched-mode power supply, Flyback transformer, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, Distribution transformer, 01 natural sciences, GaN, high temperature, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Gate driver, Hardware_INTEGRATEDCIRCUITS, Energy efficient transformer, Delta-wye transformer, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Electrical engineering, PCB-embedded transformer, high integration converter, business, Transformer types, Hardware_LOGICDESIGN
Abstract: International audience; With fast power semiconductor devices based on GaN and SiC becoming more common, there is a need for improved driving circuits. Transformers with smaller inter-winding capacitance in the isolated gate drive power supply helps in reducing the conducted EMI emission from the power converter to auxiliary sources. This paper presents a transformer with a small volume, a low power loss and a small inter-capacitance in a gate drive power supply to fast switching devices, such as GaN HEMT and SiC MOSFET. The transformer core is embedded into PCB to increase the integration density. Two different transformer designs, the coplanar-winding PCB embedded transformer and the toroidal PCB embedded transformer, are presented and compared. The former has a 0.8 pF inter-capacitance and the latter has 85% efficiency with 73 W/in 3 power density. Both designs are dedicated to a 2 W gate drive power supply for wide-band-gap device, which can operate at 200 ̊ C ambient temperature.
Published: 2016
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19. Implementation and Switching Behavior of a PCB-DBC IGBT Module Based on the Power Chip-on-Chip 3D Concept

Author: Raphaël Riva, Johan Delaine, Jean-Louis Marchesini, Cyril Buttay, Yvan Avenas, Pierre-Olivier Jeannin, Laboratoire de Génie Electrique de Grenoble (G2ELab), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), IRT Saint Exupéry - Institut de Recherche Technologique, and Institut Carnot 'énergies du futur', Région Rhône-Alpes
Subjects: Engineering, Busbar, 02 engineering and technology, Capacitors, 01 natural sciences, Industrial and Manufacturing Engineering, law.invention, [SPI]Engineering Sciences [physics], law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Electrical and Electronic Engineering, Inductance, 010302 applied physics, Substrates, business.industry, 020208 electrical & electronic engineering, Transistor, Electrical engineering, Logic gates, Insulated-gate bipolar transistor, Converters, Power (physics), Insulated gate bipolar transistors, Capacitor, Control and Systems Engineering, Logic gate, business, Switches, Copper
Abstract: International audience; With the emergence of new power semiconductor devices, the switching speeds in power converters are increasing. The stray inductances of switching cells must therefore be minimized to limit over-voltages on transistors. One relatively new approach, called Power Chip-on-Chip (PCoC), considers the integration of power dies, one on top of the other, directly in the busbar. This allows for the reduction of the stray inductance. This paper first presents the implementation of a PCoC module using classical packaging techniques. Then a description of the different technological steps for the realization is outlined. Finally, experimental characterization results confirm the lower stray inductances offered by the PCoC package compared with the planar one.
Published: 2016
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20. Thermal management and electromagnetic analysis for GaN devices packaging on DBC substrate

Author: Cyril Buttay, Chenjiang Yu, Eric Laboure, Laboratoire Génie électrique et électronique de Paris (GeePs), Université Paris-Sud - Paris 11 (UP11)-Université Pierre et Marie Curie - Paris 6 (UPMC)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), and ANR-12-BS09-0005,ETHAER,Electronique de puissance à Très Hautes performances pour l'AERonautique(2012)
Subjects: Materials science, Thermal resistance, electromagnetic analysis, Gallium nitride, 02 engineering and technology, Substrate (electronics), 7. Clean energy, 01 natural sciences, law.invention, chemistry.chemical_compound, Printed circuit board, [SPI]Engineering Sciences [physics], Thermal conductivity, law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, thermal management, Ceramic, Electrical and Electronic Engineering, simulation FEM, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, Transistor, Power electronic substrate, chemistry, visual_art, visual_art.visual_art_medium, Optoelectronics, GaN power device, business, DBC substrate
Abstract: International audience; Printed Circuit Boards (PCBs) are often used to mount gallium nitride transistors, as they offer good electrical performance. However, their thermal conductivity is not as good as with ceramic substrates. In this paper, we compare (experimentally and by simulation) both the electrical and thermal performances of GaN transistor mounted on PCBs and ceramic substrates, and we show that with a proper layout, the ceramic substrates can offer both a very good thermal management (thermal resistance 4 times lower than with PCB) and suitable electrical performance (parasitic inductances of 1–2 nH).
Published: 2016
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21. Mechanical Study of Copper Bonded at Low Temperature Using Spark Plasma Sintering Process

Author: Damien Fabrègue, Cyril Buttay, Bruno Allard, Bassem Mouawad, Maher Soueidan, Vincent Bley, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), lebanese Atomic Energy Commission, National Council for Scientific Research = Conseil national de la recherche scientifique du Liban [Lebanon] (CNRS-L), Matériaux, ingénierie et science [Villeurbanne] (MATEIS), Centre National de la Recherche Scientifique (CNRS)-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA), Matériaux Diélectriques dans la Conversion d’Energie (LAPLACE-MDCE), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées, and Ampère, Publications
Subjects: 010302 applied physics, Materials science, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Metallurgy, General Engineering, Spark plasma sintering, chemistry.chemical_element, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Copper, Temperature and pressure, chemistry, Bonding strength, 0103 physical sciences, Ultimate tensile strength, Copper bonding, Surface roughness, 0210 nano-technology, Tensile test, [SPI.NRJ] Engineering Sciences [physics]/Electric power, Spark Plasma Sintering, Tensile testing
Abstract: International audience; Bonding of high purity polished copper was investigated using the Spark Plasma Sintering technique (SPS) showing the effect of SPS parameters (surface roughness, time, temperature and pressure) on the bonding strength behaviour. Mechanical characterization of the bonded samples was performed at room temperature using tensile test. Two surfaces roughnesses were studied (un-polished and polished samples). It was found that the bonding strength varied from 50 MPa to 233 MPa for un-polished and polished surfaces respectively The tensile strength of the used bulk copper-rod was found to be 365 MPa, while most results are over 122 MPa (a third of the bulk value).
Published: 2011
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22. Effect of High Temperature Ageing on Active and Passive Power Devices

Author: Remi Robutel, Dominique Bergogne, Cyril Buttay, Thibaut Chailloux, Christophe Raynaud, Christian Martin, Simeon Dampieni, Ampère, Publications, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), and Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)
Subjects: Materials science, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Inductor, 01 natural sciences, 7. Clean energy, law.invention, Hardware_GENERAL, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Pharmacology (medical), Power semiconductor device, Diode, 010302 applied physics, business.industry, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 020208 electrical & electronic engineering, Electrical engineering, Schottky diode, Active devices, Engineering physics, Power (physics), Capacitor, Magnet, business, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract: International audience; The power devices needed to build a high-temperature converter (inductors, capacitors and active devices) have been stored at 200°C for up to 1000 hrs. Their characteristics have been monitored. Capacitors and magnetic materials from various manufacturers and technologies are tested, as well as silicon-carbide diodes. It is shown that by carefully choosing the components, it is possible to build a reliable power converter operating at high temperature.
Published: 2010
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23. Silver sintering for power electronics integration

Author: Cyril Buttay, Bruno Allard, Raphaël Riva, Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), IRT Saint Exupéry - Institut de Recherche Technologique, IMAPS, Centre National de la Recherche Scientifique - CNRS (FRANCE), Institut National des Sciences Appliquées de Lyon - INSA (FRANCE), Université Claude Bernard-Lyon I - UCBL (FRANCE), and IRT Saint Exupéry - Institut de Recherche Technologique (FRANCE)
Subjects: Energie électrique, Materials science, Assembly, chemistry.chemical_element, Sintering, 02 engineering and technology, Capacitors, 01 natural sciences, law.invention, [SPI]Engineering Sciences [physics], law, Power electronics, 0103 physical sciences, Thermal, Electronique, 010302 applied physics, Internet, Substrates, Metallurgy, Process (computing), 021001 nanoscience & nanotechnology, Copper, Capacitor, chemistry, Soldering, visual_art, Electronic component, visual_art.visual_art_medium, Electrical thermal performance Switches, 0210 nano-technology
Abstract: International audience; Silver sintering is an attractive alternative to soldering in power electronics, as it offers higher electrical and thermal performance. Furthermore, sintered attaches can operate at a higher temperature. In this paper, we investigate the use of silver sintering for the bonding of passive components, and for the manufacturing of so-called 3D-modules. It is shown that this technique is well suited, as it makes it possible to operate at very high temperature (up to 310 °C demonstrated), and as it simplifies the assembly process (several identical sintering steps can be performed successively without problem).
Published: 2015
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24. Direct Copper Bonding for Power Interconnects: Design, Manufacturing, and Test

Author: Benoit Schlegel, Maher Soueidan, Benoit Thollin, Vincent Bley, Cyril Buttay, Laurent Dupont, Bassem Mouawad, Jean-Christophe Crebier, Julien Pezard, Damien Fabrègue, Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Laboratoire des Technologies Nouvelles (IFSTTAR/COSYS/LTN), Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR), Matériaux Diélectriques dans la Conversion d’Energie (LAPLACE-MDCE), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées, Matériaux, ingénierie et science [Villeurbanne] (MATEIS), Centre National de la Recherche Scientifique (CNRS)-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA), Laboratoire de Génie Electrique de Grenoble (G2ELab), Centre National de la Recherche Scientifique (CNRS)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut Polytechnique de Grenoble - Grenoble Institute of Technology, and ANR-09-BLAN-0036,ECLIPSE,Contacts électro-thermo-mécaniques innovants pour les systèmes et l'électronique de puissance intégrée à grande échelle(2009)
Subjects: Computer science, Assembly, chemistry.chemical_element, Mechanical engineering, 02 engineering and technology, interconnections, assembly method, direct copper-to-copper bonding, 01 natural sciences, 3-D packaging, Industrial and Manufacturing Engineering, semiconductor device manufacture, Heating, Cu-Cu, power semiconductor devices, planar technology, semiconductor device metallisation, [SPI]Engineering Sciences [physics], Planar, Power electronics, thermal management (packaging), 0103 physical sciences, semiconductor device testing, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Electrical and Electronic Engineering, 010302 applied physics, Bonding, Substrates, Manufacturing process, 020208 electrical & electronic engineering, 3D power module structures, spark plasma sintering (SPS), Copper, Electronic, Optical and Magnetic Materials, Characterization (materials science), Power (physics), bonding processes, power electronics, chemistry, 3D technology, Packaging, Power module, manufacturing process, parasitic inductances, semiconductor device packaging, power interconnects
Abstract: International audience; 3-D power module structures allow for better cooling and lower parasitic inductances compared with the classical planar technology. In this paper, we present a 3-D technology that uses an innovative assembly method (direct copper-to-copper bonding). The concept and manufacturing process of this technology is described in detail. An accurate electrical characterization is then performed to compare its performance with that of the classical planar structures.
Published: 2015
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25. Study of short-circuit robustness of SiC MOSFETs, analysis of the failure modes and comparison with BJTs

Author: Denis Labrousse, Hervé Morel, Cheng Chen, Mickael Petit, Stéphane Lefebvre, Cyril Buttay, Lefebvre, Stéphane, Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE), École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS), Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Electronique de Puissance et Intégration (SATIE-EPI), Composants et Systèmes pour l'Energie Electrique (CSEE), Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)-École normale supérieure - Cachan (ENS Cachan)-Université Paris-Sud - Paris 11 (UP11)-Institut Français des Sciences et Technologies des Transports, de l'Aménagement et des Réseaux (IFSTTAR)-École normale supérieure - Rennes (ENS Rennes)-Université de Cergy Pontoise (UCP), and Université Paris-Seine-Université Paris-Seine-Conservatoire National des Arts et Métiers [CNAM] (CNAM)-Centre National de la Recherche Scientifique (CNRS)-Systèmes et Applications des Technologies de l'Information et de l'Energie (SATIE)
Subjects: SiC, Materials science, [SPI] Engineering Sciences [physics], BJT, Time-dependent gate oxide breakdown, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, law.invention, MOSFET, [SPI]Engineering Sciences [physics], chemistry.chemical_compound, Robustness (computer science), law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Silicon carbide, Hardware_INTEGRATEDCIRCUITS, Electrical and Electronic Engineering, Safety, Risk, Reliability and Quality, 010302 applied physics, business.industry, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 020208 electrical & electronic engineering, Transistor, Bipolar junction transistor, Electrical engineering, short circuit, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, chemistry, Optoelectronics, business, Short circuit, AND gate, Hardware_LOGICDESIGN, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract: International audience; This paper presents experimental robustness tests made on Silicon Carbide (SiC) MOSFETs and SiC Bipolar Junction Transistors (BJTs) submitted to short-circuit operations (SC) or current limitation modes. For SiC MOSFETs, a gate leakage current is detected before failure without being responsible for the immediate failure. Nevertheless this gate leakage current is not without effect on the integrity of the SiC MOSFETs. Based on several robustness tests performed on SiC MOSFETs and on the comparison with experimental results obtained with SiC BJTs, the paper points out two main failure modes for SiC MOSFETs. The first one results in a simultaneously short circuit between drain and gate and drain and source and the second one in a degradation of the insulation between gate and source leading to a short circuit between gate and source. For some tested devices, the failure appears in a very interesting open state mode between drain and source after physical short-circuit between gate and source with a mode of failure very similar to those observed for SiC BJT.
Published: 2015
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26. Measurement and numerical analysis of C-V characteristics for normally-on SiCED-JFET

Author: Hervé Morel, Cyril Buttay, Sami Ghedira, Kamel Besbes, Faculté des Sciences de Monastir (FSM), Université de Monastir - University of Monastir (UM), Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), and Collaboration Ampere-Monastir
Subjects: 010302 applied physics, [SPI.OTHER]Engineering Sciences [physics]/Other, Test bench, Materials science, Numerical analysis, 020208 electrical & electronic engineering, JFET, 02 engineering and technology, Condensed Matter Physics, 01 natural sciences, Capacitance, Measure (mathematics), Electronic, Optical and Magnetic Materials, law.invention, Computational physics, Capacitor, Planar, law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Instrumentation, Mutual influence
Abstract: 7 pages; International audience; In this paper, terminal capacitances of a normally-on SiCED-JFET are measured, analyzed and simulated. All these capacitances are measured using an auto-balanced (guarded) capacitance test-bench that leads to the standard 3-terminal model capacitors CGS, CDS and CGD. This test bench is developed to measure each capacitance individually, without any mutual influence. 2D finite-element simulations are used to show that the capacitance CGD cannot be modeled by a standard planar junction model. This is due to the influence of two dimensional effects around the buried layer P+. A new analytical model of CGD is proposed. A good agreement is obtained between simulations and measurements of the different capacitances.
Published: 2014
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27. Study of die attach technologies for high temperature power electronics: Silver sintering and gold-germanium alloy

Author: Eric Woirgard, Régis Meuret, Stephane Azzopardi, Wissam Sabbah, Cyril Buttay, Laboratoire de l'intégration, du matériau au système (IMS), Université Sciences et Technologies - Bordeaux 1-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), SAFRAN, Grp Hispano Suiza, SAFRAN Group, and Centre National de la Recherche Scientifique (CNRS)-Institut Polytechnique de Bordeaux-Université Sciences et Technologies - Bordeaux 1
Subjects: Materials science, Thermal resistance, Alloy, Sintering, chemistry.chemical_element, Germanium, 02 engineering and technology, Temperature cycling, engineering.material, 01 natural sciences, Die (integrated circuit), Power electronics, 0103 physical sciences, Electrical and Electronic Engineering, Safety, Risk, Reliability and Quality, 010302 applied physics, Metallurgy, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, chemistry, Soldering, engineering, 0210 nano-technology
Abstract: International audience; Silver sintering joints and AuGe soldering are promising technologies for high temperature (>200 °C ambient) power electronics packaging. This paper presents the implementation of two silver-sintering processes with the one hand micrometer-scale silver particles, and on the other hand nano-meter-scale particles. Two substrates technologies have been investigated: A12O3 DBC and Si3N4 AMB. After the process optimization, tests vehicles have been assembled using both sintering processes, as well as a more classical high-temperature die attach technology: AuGe soldering. Multiple analyses have been performed, such as thermal resistance measurement, shear tests and micro-sections to follow the evolution of the joint during thermal cycling and high-temperature storage ageing.
Published: 2013
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28. High Temperature, High Frequency Micro-Inductors for Low Power DC-DC Converters

Author: Dominique Bergogne, Charles Joubert, Elias Haddad, Christian Martin, Bruno Allard, Cyril Buttay, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Ampère, Département Energie Electrique (EE), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), and MICONET2
Subjects: Materials science, passive component integration, high temperature electronics, 02 engineering and technology, Heat sink, Inductor, 01 natural sciences, high temperature, Operating temperature, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Magnetic material, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Electrical engineering, Atmospheric temperature range, Converters, inductor, Magnetic core, Magnet, LCR meter, Optoelectronics, electroplating process, business
Abstract: 9 pages; International audience; The development of micro-inductors is still a challenge to improve the integration level of low power DC-DC converters. The temperature rise due to self-heating or higher ambient temperature represents a risk for system operation. Unfortunately, the use of a heat sink increases the size of the converter and it is more difficult to extract the heat flow dissipated from a smaller area. The increase in the allowable operating temperature offers a solution to achieve a high integration level while ensuring proper heat management. This paper presents the fabrication process of micro-planar inductors with magnetic layers (YIG). The influence of the temperature on the magnetic material and on the inductor performances is studied up to 280 °C. Fabricated micro-inductors are tested using a LCR meter in the 10 kHz to 110 MHz frequency range and over a large temperature range, from 30 °C to 280 °C.
Published: 2013
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29. Thermal stability of SiC JFETs in conduction mode

Author: Florent Morel, Raphaël Riva, Remy Ouaida, Dominique Bergogne, Bruno Allard, Cyril Buttay, Christophe Raynaud, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Ampère, Département Energie Electrique (EE), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), FRAE, and EPAHT
Subjects: JFET, Test bench, Materials science, High temperature electronics, 02 engineering and technology, Silicon carbide, 01 natural sciences, chemistry.chemical_compound, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Power semiconductor device, Silicon bandgap temperature sensor, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Wide-bandgap semiconductor, Atmospheric temperature range, Reliability, chemistry, Thermal design, Optoelectronics, Junction temperature, business
Abstract: 8 pages; International audience; Although they can operate at elevated junction temperature, silicon carbide power devices can in some cases fail, even at low ambient temperature. This destruction mechanism, called the thermal run-away, is described in the paper. Then, the sensitivity of normally-on SiC JFETs (SiCED) to this mechanism is evaluated using a model based on experimental measurements performed over a wide temperature range (from -50°C to 300°C). It is shown that above a certain current level, run-away can occur. An experimental test bench is used to validate the modelling and explore the safe-operating area of these devices. The measurements confirm the sensitivity of the device to thermal run-away. Mitigation techniques are discussed.
Published: 2013
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30. Analysis of the SiC VJFET gate punch-through and its dependence with the temperature

Author: Régis Meuret, Fabien Dubois, Dominique Tournier, Dominique Bergogne, Cyril Buttay, Hervé Morel, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), SAFRAN, Grp Hispano Suiza, and SAFRAN Group
Subjects: JFET, Materials science, High temperature electronics, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, Blocking (statistics), 01 natural sciences, Silicon Carbide (SiC), 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Device modeling, Voltage range, Device characterisation, 010302 applied physics, business.industry, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Electrical engineering, Wide-bandgap semiconductor, Atmospheric temperature range, 021001 nanoscience & nanotechnology, Threshold voltage, ComputerSystemsOrganization_MISCELLANEOUS, Optoelectronics, 0210 nano-technology, business, Voltage
Abstract: 10 pages; International audience; Turning off a SiC VJFET from INFINEON requires to apply a gate-to-source voltage comprised between the JFET gate threshold voltage and the punch-through voltage. Unfortunately, for applications operating over a large temperature range, these two limits vary with the temperature and reduce the useful blocking gate-to-source voltage range as the temperature rises. So, the punch-through temperature dependence is a very important feature for applications operating in a wide temperature range like aeronautic applications. This paper addresses the analysis and modeling of the punch-through phenomenon and its dependence to the temperature. The proposed model gives a good agreement with the experimental data.
Published: 2013
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31. Design and Implementation of Integrated Common Mode Capacitors for SiC JFET Inverters

Author: Remi Robutel, Régis Meuret, Cyril Buttay, Christian Martin, Hervé Morel, Paolo Mattavelli, Dushan Boroyevich, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Center for power electronics system, University of Wisconsin-Madison, Universita degli Studi di Padova, SAFRAN, Grp Hispano Suiza, SAFRAN Group, and DGA
Subjects: Engineering, 02 engineering and technology, 7. Clean energy, 01 natural sciences, Electromagnetic interference, law.invention, law, EMI, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Power semiconductor device, Common-mode signal, Multichip modules, Electrical and Electronic Engineering, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Electrical engineering, Electromagnetic compatibility, Inverters, Capacitor, Power module, Inverter, business
Abstract: 12 pages; International audience; This paper deals with the issue of electromagnetic interference (EMI) in SiC-JFET inverter power modules, and proposes a solution to limit conducted emissions at high frequencies. SiC-JFET inverters can achieve very fast switching, thereby reducing commutation losses, at the cost of a high level of EMI. In order to limit conducted EMI emissions, it is proposed to integrate small-value common mode (CM) capacitors, directly into the power module. High frequency noise, which is usually difficult to filter, is then contained within the module, thus keeping it far from the external network. This approach is in line with the current trend towards the integration of various functions (such as protection, sensors or drivers) around power devices in modern power modules. To demonstrate this concept, the resulting CM noise was investigated, and compared with a standard configuration. Simulations were used to design the integrated capacitors, and measurements were carried out on an experimental SiC-JFET half-bridge structure. A significant reduction was achieved in the experimentally observed CM conducted emissions, with a very minor influence on the switching waveforms, losses and overall size of the system. The benefits and limitations of this design are discussed, for the case of mid-power range inverters for aircraft applications.
Published: 2013
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32. High temperature, Smart Power Module for aircraft actuators

Author: Dominique Planson, Dominique Tournier, Bruno Allard, Luong Viet Phung, Cyril Buttay, Khalil El Falahi, Stanislas Hascoet, Pascal Bevilacqua, Ampère, Publications, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Ampère, Département Energie Electrique (EE), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Euripides-Catrene, and THOR
Subjects: SiC, Engineering, Silicon on insulator, 02 engineering and technology, 01 natural sciences, 7. Clean energy, chemistry.chemical_compound, Smart power, Power electronics, 0103 physical sciences, Gate driver, Silicon carbide, Pharmacology (medical), Electronic circuit, 010302 applied physics, SOI, business.industry, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Electrical engineering, Converters, 021001 nanoscience & nanotechnology, Power module, chemistry, 0210 nano-technology, business, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract: International audience; More electric aircraft require converters that can operate over a wide temperature range (-55 to more than 200°C). Silicon carbide JFETs can satisfy these requirements, but there is a need for suitable peripheral components (gate drivers, passives. . . ). In this paper, we present a "smart power module" based on SiC JFETs and dedicated integrated gate driver circuits. The design is detailed, and some electrical results are given, showing proper operation of the module up to 200°C.
Published: 2013

33. Pressureless Silver Sintering Die-Attach for SiC Power Devices

Author: Dominique Planson, Stanislas Hascoet, Cyril Buttay, Amandine Masson, Rodica Chiriac, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Laboratoire des Multimatériaux et Interfaces (LMI), Université Claude Bernard Lyon 1 (UCBL), and Université de Lyon-Université de Lyon-Institut de Chimie du CNRS (INC)-Centre National de la Recherche Scientifique (CNRS)
Subjects: 010302 applied physics, Materials science, business.product_category, Mechanical Engineering, 020208 electrical & electronic engineering, Metallurgy, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Sintering, 02 engineering and technology, Condensed Matter Physics, 01 natural sciences, Silver Sintering, Reliability (semiconductor), Drying time, Mechanics of Materials, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Die (manufacturing), General Materials Science, Power semiconductor device, Electronics, business, Die Attach
Abstract: International audience; Silicon carbide power devices are extremely attractive for high temperature applications. Many converters, based on SiC power devices, have been demonstrated to operate at ambient temperatures ranging from 200°C to 400°C. However, the power devices themselves are no longer the only limiting factor for the increase in operating temperature. Their packaging has become the main stumbling block for high-temperature, reliable operation. Different degradation phenomenon can be observed: fracture of the package during large thermal cycling (due to mismatch in the Coefficient of Thermal Expansion of the various materials), diffusion of chemical species, phase change...
Published: 2012
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34. Sintered molybdenum for a metallized ceramic substrate packaging for the wide-bandgap devices and high temperature applications

Author: Hervé Morel, Maher Soueidan, Cyril Buttay, Vincent Bley, Bassem Mouawad, Damien Fabrègue, Florian Mercier, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Matériaux Diélectriques dans la Conversion d’Energie (LAPLACE-MDCE), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées, Matériaux, ingénierie et science [Villeurbanne] (MATEIS), Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), and Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)
Subjects: 010302 applied physics, Materials science, Aluminium nitride, Metallurgy, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Wide-bandgap semiconductor, Electronic packaging, Spark plasma sintering, Sintering, 02 engineering and technology, Substrate (electronics), 021001 nanoscience & nanotechnology, 7. Clean energy, 01 natural sciences, Wide-bandgap devices, chemistry.chemical_compound, molybdenum, chemistry, 0103 physical sciences, Silicon carbide, aluminium nitride, Composite material, 0210 nano-technology, Layer (electronics), Spark Plasma Sintering
Abstract: 4 pages; International audience; Silicon Carbide (SiC) is a good candidate for high temperature power electronic applications. To ensure good reliability, packaging materials with a coefficient of thermal expansion (CTE) matching that of SiC are needed. A metallized ceramic substrate based on aluminium nitride (AlN) and molybdenum (Mo) is reported in this paper. This substrate is built using a spark plasma sintering equipment. Results show that a dense Mo layer can be sintered on an AlN plate, with good adhesion, forming a Mo/AlN/Mo structure with well-matched CTEs.
Published: 2012
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35. An Airborne High Temperature SiC Power Converter for Medium Power Smart Electro Mechanical Actuators

Author: Hervé Morel, Sonia Dhokkar, Dominique Bergogne, Fabien Dubois, Bruno Allard, Christian Martin, Luong Viet Phung, Khalil El Falahi, Régis Meuret, Cyril Buttay, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), SAFRAN, Grp Hispano Suiza, SAFRAN Group, Ampère, Département Energie Electrique (EE), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), IMAPS, and Ampère, Publications
Subjects: Test bench, Engineering, Silicon on insulator, 02 engineering and technology, Input EMI filter, Inductor, 01 natural sciences, 7. Clean energy, law.invention, chemistry.chemical_compound, EMI, law, Voltage Feed Inverter, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Silicon carbide, Gate driver, Pharmacology (medical), Transformer, 010302 applied physics, Interconnection, business.industry, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Electrical engineering, Normally-On device, chemistry, business, SiC JFET, [SPI.NRJ] Engineering Sciences [physics]/Electric power, JFET gate driver
Abstract: International audience; Normally-On Silicon Carbide (SiC) JFETs are good candidates for power switches in high temperature applications, in Three-Phase Voltage-Fed Inverters used to drive Electro-Mechanical Actuators (EMA) for the more electrical aircraft where the ambient varies from -55 °C to 200 °C. The power of the EMA is in the 1 to 5 kW range, the DC bus voltage is 540 V. It is also necessary to implement passive subsystems such as Electro-Magnetic-Interference (EMI) flters, power inductors, transformers, packaging and interconnection solution that withstand the wide temperature range. The gate driver for normally-On devices must include a safe solution against short-circuit in the event of a power supply failure. The experimental converter is built using engineering samples such as SiC JFETs, SOI drivers and laboratory made components such as inductive wire wound, nano-crystalline core components, SOI integrated driver, assembled with a high temperature package and technology. Finally, the Smart EMA test bench is presented.
Published: 2012

36. Application of the Spark Plasma Sintering Technique to Low-Temperature Copper Bonding

Author: Maher Soueidan, Bruno Allard, Hervé Morel, Cyril Buttay, Vincent Bley, Bassem Mouawad, Damien Fabrègue, Christian Martin, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Matériaux, ingénierie et science [Villeurbanne] (MATEIS), Centre National de la Recherche Scientifique (CNRS)-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA), Ampère, Département Energie Electrique (EE), Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Matériaux Diélectriques dans la Conversion d’Energie (LAPLACE-MDCE), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), and Université Fédérale Toulouse Midi-Pyrénées
Subjects: [SPI.OTHER]Engineering Sciences [physics]/Other, Wire bonding, Materials science, 020209 energy, Electronic packaging, Spark plasma sintering, 02 engineering and technology, Substrate (electronics), 01 natural sciences, Industrial and Manufacturing Engineering, Die (integrated circuit), 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Ceramic, Electrical and Electronic Engineering, Three-dimensional packaging, Power density, Spark Plasma Sintering, 010302 applied physics, business.industry, Electronic, Optical and Magnetic Materials, [SPI.TRON]Engineering Sciences [physics]/Electronics, power electronics, Anodic bonding, visual_art, visual_art.visual_art_medium, Optoelectronics, business, semiconductor device packaging
Abstract: International audience; Planar structures, in which a power die is soldered on a substrate and wirebonds are used to connect the top of the die with the substrate, are limited in terms of thermal management and power density. Three-dimensional packaging techniques have been proposed to overcome these limits. Here, an innovative copper-to-copper bonding solution is presented, that can be used for 3-D packaging. The bonding process is described and the effect of the bonding parameters is investigated. It is found that this technique is compatible with the requirements of power electronic packaging. A test assembly including a silicon power die and ceramic substrates is presented.
Published: 2012
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37. Thermal stability of silicon-carbide power diodes

Author: Cyril Buttay, Christophe Raynaud, M-L Locatelli, Florent Morel, Gabriel Civrac, Hervé Morel, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Matériaux Diélectriques dans la Conversion d’Energie (LAPLACE-MDCE), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), and Université Fédérale Toulouse Midi-Pyrénées
Subjects: Materials science, Thermal runaway, Silicon, chemistry.chemical_element, Schottky diodes, 02 engineering and technology, Silicon carbide, 01 natural sciences, chemistry.chemical_compound, High temperature techniques, 0103 physical sciences, Power electronics, Power semiconductor device, Electrical and Electronic Engineering, P-i-n diodes, Diode, 010302 applied physics, business.industry, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Wide-bandgap semiconductor, Schottky diode, 021001 nanoscience & nanotechnology, Electronic, Optical and Magnetic Materials, chemistry, Optoelectronics, Junction temperature, 0210 nano-technology, business
Abstract: International audience; Silicon carbide (SiC) power devices can operate at much higher junction temperature than those made of silicon. However, this does not mean that SiC devices can operate without a good cooling system. To demonstrate this, the model of a Merged PiN Schottky (MPS) SiC diode is presented, and its parameters are identified with experimental measurements. This model is then used to study the ruggedness of the diode regarding the thermal run-away phenomenon. Finally, it is shown that where a purely unipolar diode would be unstable, the MPS structure brings increased stability.
Published: 2012
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38. Elaboration of Architectured Materials by Spark Plasma Sintering

Author: Aude Lamontagne, Loic Courtois, Eric Maire, Véronique Massardier-Jourdan, Maher Soueidan, Romain Forte, Damien Fabrègue, Bassem Mouawad, Cyril Buttay, Michel Perez, Caroline Landron, Matériaux, ingénierie et science [Villeurbanne] (MATEIS), Centre National de la Recherche Scientifique (CNRS)-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), and Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)
Subjects: Materials science, Spark Plasma Sintering (SPS), Sintering, Spark plasma sintering, 02 engineering and technology, 01 natural sciences, Porous Material, 0103 physical sciences, Microelectronics, General Materials Science, Ceramic, Composite material, Porosity, 010302 applied physics, Bonding, business.industry, Mechanical Engineering, Metallurgy, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Microstructure, Grain size, Mechanics of Materials, visual_art, Architectured Materials, visual_art.visual_art_medium, 0210 nano-technology, business, Diffusion bonding
Abstract: International audience; Spark plasma sintering has been used for decades in order to consolidate a wide variety of materials and permitting to obtain fully dense specimens. This technique has been mainly applied to ceramics. This paper concentrates on an unusual use of spark plasma sintering system: obtaining innovative materials especially architectured ones. Different applications are presented. Firstly, the SPS technique has been used to elaborate nanometers grain size materials or containing nanoscale microstructure. This is possible since the sintering temperature and the holding time are far lower in the SPS compared to other techniques. Then SPS has been used to realize diffusion bonding. In that case again, bonding can be realized at low temperature and for short time. It permits for example to realize bonding between two copper layers which is of a great importance for microelectronic applications. It is worth noting that this bonding can have the same mechanical strength as pure copper even for diffusion time of a few minutes. Secondly, bonding has been also carried out between a metallic layer and a ceramic one. This could lead to design of new layered materials combining interesting properties in terms of mechanical strength but also in terms of electrical resistance. The SPS machine has also been used to obtain porous materials (cobalt alloys or copper) with an adapted microstructure (porosity, tortuosity,). These structures could open new perspectives for biomedical or for microelectronic applications. All these examples lead to a better understanding of the physical processes which happen during spark plasma sintering.
Published: 2011
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39. Modeling, Fabrication, and Characterization of Planar Inductors on YIG Substrates

Author: Bruno Allard, Mihai Lazar, Charles Joubert, Cyril Buttay, Maher Soueidan, Béatrice Payet-Gervy, Elias Haddad, Christian Martin, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Dispositifs et Instrumentation en Optoélectronique et micro-ondes (DIOM), Université Jean Monnet [Saint-Étienne] (UJM), and Ampère, Publications
Subjects: Planar Inductors, [SPI.OTHER]Engineering Sciences [physics]/Other, Engineering, Fabrication, Switched-mode power supply, 02 engineering and technology, Inductor, Passive Components, 7. Clean energy, 01 natural sciences, EMI, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Magnetic Material, DC-DC Power Conversion, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, General Engineering, Electrical engineering, Converters, Copper Electroplating, [SPI.TRON]Engineering Sciences [physics]/Electronics, Inductance, Magnet, Optoelectronics, business, Microwave, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract: International audience; This paper presents the design, fabrication, and characterization of micro planar inductors on a microwave magnetic material (YIG). Planar spiral inductors were designed for monolithic DC-DC converters in System-In-Package with 100 MHz switching frequency (1 W, Vin=3.6 V, Vout=1 V). System-In-Package applications are facing miniaturization issues due to passive components size. In this frequency range, the size of filter passive components can be reduced dramatically. Thus, the passive area of integration is in the 10 mm2 range. A microwave magnetic substrate (YIG) serves as mechanical support and also presents a double purpose by increasing inductance value and reducing electromagnetic perturbations. This last point seems to be a critical point to improve the good behavior of a switching mode power supply. In order to obtain the optimal design for the inductor, geometrical parameters were studied using Flux2D simulator. A specific Merit factor taking into consideration inductance value at 100MHz, DC resistance and footprint was proposed to compare different inductor structures. An optimized 50 nH spiral inductor with expected 50 mΩ RDC, 3 mm2 surface area was designed. Simulation conditions and results will be described in the full paper. Micro inductors occupying 3mm2 surface area were fabricated by electroplating technique. Fabrication process involves seed layer deposition on YIG, lamination of dry film photoresist and electroplating to mould the resist patterns. Process fabrication will be detailed in the full paper. Figure 1 shows SEM image of the fabricated inductor. Afterwards, samples were tested using a vector network analyzer in the 10 MHz to 100 MHz range. Results were then compared to the predicted response of simulated equivalent model.
Published: 2011
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40. Design of a High Temperature EMI Input Filter for a 2 kW HVDC-Fed Inverter

Author: Rémi Robutel, Christian Martin, Hervé Morel, Cyril Buttay, Nicolas Gazel, Dominique Bergogne, Ampère, Publications, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), SAFRAN, Grp Hispano Suiza, and SAFRAN Group
Subjects: 010302 applied physics, Computer Networks and Communications, Electromagnetic disturbance, [SPI.NRJ]Engineering Sciences [physics]/Electric power, 020208 electrical & electronic engineering, 02 engineering and technology, Silicon carbide, Inductor, High temperature, 7. Clean energy, 01 natural sciences, Electromagnetic interference, Electronic, Optical and Magnetic Materials, Temperature dependence, Junction field effect transistor, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Inverter, Electrical and Electronic Engineering, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract: International audience; In this article, a high temperature EMI input filter for a SiC JFET inverter is designed and tested in operating conditions at 200°C. Inverter EMI issues, design procedure, and characterizations of selected components are presented in detail. The feasibility based on industrially available materials and components is demonstrated with a low temperature dependence of the EMI spectrum.
Published: 2011

41. Design of High Temperature EMI Input Filter for a 2 kW HVDC-Fed Inverter

Author: Nicolas Gazel, Christian Martin, Hervé Morel, Remi Robutel, Dominique Bergogne, Cyril Buttay, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), SAFRAN, Grp Hispano Suiza, SAFRAN Group, and Ampère, Publications
Subjects: 010302 applied physics, Conducted electromagnetic interference, Engineering, business.industry, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Electrical engineering, JFET, 02 engineering and technology, Inductor, 7. Clean energy, 01 natural sciences, Electromagnetic interference, EMI, Filter (video), 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Inverter, Pharmacology (medical), Common-mode signal, business, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract: International audience; In this paper, a high temperature EMI input filter for a SiC JFET inverter is designed and tested in operating conditions at 200°C. Inverter EMI issues, design procedure and characterizations of selected components are presented in details. The feasibility based on industrially available materials and components is demonstrated with a low temperature dependence of EMI Spectrum.
Published: 2010

42. State of the art of High Temperature Power Electronics

Author: Christophe Raynaud, Christian Martin, Bruno Allard, Hervé Morel, Dominique Bergogne, Charles Joubert, Pascal Bevilacqua, Mihai Lazar, Cyril Buttay, Dominique Tournier, Dominique Planson, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), and Ampère, Publications
Subjects: [SPI.OTHER]Engineering Sciences [physics]/Other, Materials science, Silicon, chemistry.chemical_element, 02 engineering and technology, Temperature cycling, High-temperature, Silicon carbide, 7. Clean energy, 01 natural sciences, High-temperature electronics, Carbide, Electric power system, chemistry.chemical_compound, Power electronics, Semiconductor devices, 0103 physical sciences, General Materials Science, 010302 applied physics, business.industry, [SPI.OTHER] Engineering Sciences [physics]/Other, Mechanical Engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Semiconductor device, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Engineering physics, Semiconductor, chemistry, Mechanics of Materials, 0210 nano-technology, business
Abstract: International audience; High temperature power electronics has become possible with the recent availability of silicon carbide devices. This material, as other wide-bandgap semiconductors, can operate at temperatures above 500 °C, whereas silicon is limited to 150-200 °C. Applications such as transportation or a deep oil and gas wells drilling can benefit. A few converters operating above 200 °C have been demonstrated, but work is still ongoing to design and build a power system able to operate in harsh environment (high temperature and deep thermal cycling).
Published: 2009
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43. Experimental Analysis of Punch-Through Conditions in Power P-I-N Diodes

Author: Kamel Besbes, Bruno Allard, Hervé Morel, T.B. Salah, Cyril Buttay, Sami Ghedira, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Laboratoire de Microélectronique et Instrumentations [Monastir], Faculté des Sciences de Monastir (FSM), and Université de Monastir - University of Monastir (UM)-Université de Monastir - University of Monastir (UM)
Subjects: intrinsic, [SPI.OTHER]Engineering Sciences [physics]/Other, Materials science, 02 engineering and technology, 01 natural sciences, Optics, Power electronics, 0103 physical sciences, reverse-recovery, 0202 electrical engineering, electronic engineering, information engineering, Breakdown voltage, Electrical and Electronic Engineering, Diode, Extrinsic semiconductor, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, Doping, p-type, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Semiconductor, avalanche, Optoelectronics, Transient (oscillation), Zener diode, punch-through (PT), n-type (P-I-N) diode, business
Abstract: International audience; Commercial power diodes are optimized to feature punch–through behavior. However, a tradeoff between the width and the doping level of the diode epitaxial layer leads to various levels of optimization. For a given breakdown voltage, a shorter epitaxial layer width leads to better transient performances. Device datasheets do not cover this issue and a simple experimental setup is presented to assess the optimization conditions inside the diode epitaxial layer. Three commercial devices are tested and experimental results are confronted to device simulations. A good agreement is found
Published: 2007
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44. Model Requirements for Simulation of Low-Voltage MOSFET in Automotive Applications

Author: Bruno Allard, Cyril Buttay, P. Lefranc, Olivier Brevet, Hervé Morel, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), and Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)
Subjects: [SPI.OTHER]Engineering Sciences [physics]/Other, Engineering, Characterization, Commutation cell, electrothermal, power metal-oxide semiconductor field-effect transistor (MOSFET), 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, Electronic circuit simulation, law.invention, Computer Science::Hardware Architecture, law, 0103 physical sciences, MOSFET, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Commutation, Electrical and Electronic Engineering, Power MOSFET, Electronic circuit, 010302 applied physics, validation, model, business.industry, 020208 electrical & electronic engineering, Transistor, circuit parasitics, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Condensed Matter::Mesoscopic Systems and Quantum Hall Effect, Automotive electronics, business
Abstract: International audience; This paper focuses on the modeling of low-voltage automotive power electronic circuits to obtain accurate system simulation, including estimation of losses. The aim is to compare several metal-oxide semiconductor field-effect transistor (MOSFET) models to find out which can be used for low-voltage, high-current automotive converter simulations. As these models are intended for system simulation, only analytical models are addressed as they may be implemented into any circuit simulator. The different modes of operation of the switches are described (commutation, synchronous rectification, avalanche ), and several models of the power MOSFET transistor, allowing for simulation in these modes, are presented. Special care is given to the parameter extraction methods and to the interconnection model of the commutation cell. The four test circuits used to identify the low-voltage power MOSFET model parameters are presented. Comparison between simulations and measurements obtained with a calorimeter are then detailed. This measurement method is accurate and offers a simple way to prove the quality of simulation results. It is shown that the parameter identification is of major concern to achieve high accuracy, as classical Spice models can give good results, providing the model parameters are correctly set.
Published: 2006
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45. Paralleling of Low-Voltage MOSFETs Operating in Avalanche Conditions

Author: Dominique Bergogne, Cyril Buttay, Olivier Brevet, Hervé Morel, Bruno Allard, Centre de génie électrique de Lyon (CEGELY), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), and Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)
Subjects: [SPI.OTHER]Engineering Sciences [physics]/Other, Engineering, automotive electronics, Ampere balance, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, law.invention, MOSFET, Reliability (semiconductor), Automotive component, law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Breakdown voltage, 010302 applied physics, Avalanche diode, business.industry, 020208 electrical & electronic engineering, Transistor, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Electrical engineering, Condensed Matter::Mesoscopic Systems and Quantum Hall Effect, thermal design, Avalanche breakdown, device modelling, business, Low voltage
Abstract: International audience; This paper addresses the behavior of low voltage MOSFETs under breakdown avalanche operation. The phenomena leading to avalanche operation of the MOSFET transistors in automotive applications are first presented. Then, after a brief description of the model and of the experimental identification of its parameters, electrothermal simulations are performed. A special focus is given to the current balance between paralleled MOSFETs, because in this case breakdown voltage mismatches are a well-known reliability issue. These simulations demonstrate the influence of the specific avalanche path resistance on current sharing. Calculations performed using the proposed model give results far less pessimistic (lower temperature rise on the most stressed transistor) than classical temperature-dependant-only avalanche models. This avoids expensive specifications narrowing when designing for mass-market applications (where wide manufacturing dispersions occur).
Published: 2005
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46. Avalanche Behavior of Low-Voltage Power MOSFETs

Author: Dominique Bergogne, Cyril Buttay, Bruno Allard, T.B. Salah, Hervé Morel, Jean-Pierre Chante, Centre de génie électrique de Lyon (CEGELY), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), and Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)
Subjects: [SPI.OTHER]Engineering Sciences [physics]/Other, Materials science, low-voltage MOSFET, Physics::Instrumentation and Detectors, Energy Engineering and Power Technology, 02 engineering and technology, 01 natural sciences, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Hardware_INTEGRATEDCIRCUITS, Breakdown voltage, Avalanche, Electrical and Electronic Engineering, Power MOSFET, 010302 applied physics, Avalanche diode, business.industry, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Electrical engineering, Avalanche photodiode, Condensed Matter::Mesoscopic Systems and Quantum Hall Effect, Avalanche breakdown, electrothermal model, Single-photon avalanche diode, avalanche resistance, Zener diode, business, temperature estimation, Low voltage
Abstract: International audience; This letter addresses the behavior of low voltage power MOSFETs under avalanche, with a paralleling point of view. It is shown that during avalanche, up-to-date technology MOSFET transistors exhibit a resistance far in excess of their on-state resistance ( DS ). A novel test setup is proposed to measure “avalanche” resistance. A simple model of breakdown voltage is then proposed. It becomes possible to perform fast simulations using this model to study current balance between paralleled transistors under avalanche operation. It is shown that considering avalanche resistance reduces the influence of breakdown voltage mismatches and allows for better current sharing.
Published: 2004
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47. Packaging with double-side cooling capability for SiC devices, based on silver sintering

Author: Vincent Bley, Marie-Laure Locatelli, Cyril Buttay, Raphel Riva, Bruno Allard, Ampère, Département Energie Electrique (EE), Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)-École Centrale de Lyon (ECL), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), Matériaux Diélectriques dans la Conversion d’Energie (LAPLACE-MDCE), LAboratoire PLasma et Conversion d'Energie (LAPLACE), Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées, IEEE, Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Institut National Polytechnique (Toulouse) (Toulouse INP), and Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3)
Subjects: 010302 applied physics, Materials science, business.industry, 020208 electrical & electronic engineering, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Sintering, 02 engineering and technology, 01 natural sciences, Characterization (materials science), chemistry.chemical_compound, Parylene, chemistry, Etching (microfabrication), Logic gate, visual_art, 0103 physical sciences, Thermal, 0202 electrical engineering, electronic engineering, information engineering, Silicon carbide, visual_art.visual_art_medium, Optoelectronics, Ceramic, business
Abstract: International audience; Although they can operate at high temperature, SiC devices require efficient thermal management. One solution is to use a dual-side cooling packaging, where heat can be extracted through two surfaces. Here, such a package is presented, using only materials which can operate at high temperature (>200°C): ceramic substrates, silver sintering, fluorinated parylene. Due to the small feature size of the SiC dies used, a special care is given on the etching resolution of the substrates. The complete manufacturing process is presented, and some characterization results are given to demonstrate that the package is operational.
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48. Die attach of power devices using silver sintering - Bonding process optimisation and characterization

Author: Jianfeng Li, M. Lazar, Amandine Masson, Christophe Raynaud, Hervé Morel, Mark Johnson, Cyril Buttay, Ampère (AMPERE), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE), University of Nottingham, UK (UON), IMAPS, and Ampère, Publications
Subjects: 010302 applied physics, Bonding process, Materials science, Die attach, silver sintering, Metallurgy, [SPI.NRJ]Engineering Sciences [physics]/Electric power, Sintering, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Die (integrated circuit), Characterization (materials science), high temperature packaging, Operating temperature, Soldering, 0103 physical sciences, Melting point, Shear test, Pharmacology (medical), Power semiconductor device, 0210 nano-technology, [SPI.NRJ] Engineering Sciences [physics]/Electric power
Abstract: Silver sintering is becoming an attractive alternative to soldering, especially for high temperature applications. Indeed, the increase in operating temperature requires new soldering alloys with even higher melting points. Silver sintering, on the contrary, is a solution which only require moderate ( In this paper, we present the implementation of a die attach technique based on sintering of some silver paste, with a special focus on the practical considerations. A good quality bond can be achieved by paying attention to the assembly process.

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