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Your search keyword '"Louise De Conti"' showing total 4 results
Start Over Author "Louise De Conti" Topic 01 natural sciences
4 results on '"Louise De Conti"'

1. GDNMOS and GDBIMOS devices for high voltage ESD protection in thin film advanced FD-SOI technology

Author

Maud Vinet, Philippe Galy, Louise De Conti, Sorin Cristoloveanu, Thomas Bedecarrats, STMicroelectronics, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)

Subjects
Materials science, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 01 natural sciences, [SPI]Engineering Sciences [physics], 0103 physical sciences, MOSFET, Hardware_INTEGRATEDCIRCUITS, Materials Chemistry, Hardware_ARITHMETICANDLOGICSTRUCTURES, Electrical and Electronic Engineering, Metal gate, NMOS logic, 010302 applied physics, business.industry, High voltage, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Electronic, Optical and Magnetic Materials, Anode, CMOS, Optoelectronics, 0210 nano-technology, business, Hardware_LOGICDESIGN, Voltage
Abstract

GDNMOS (Gated Diode merged NMOS) and GDBIMOS (Gated Diode merged BIMOS) were fabricated using the 28 nm node ultra-thin film UTBB FD-SOI high-k metal gate CMOS technology. The anode current and voltage were measured and simulated for a high number of variants with different connectivity conditions on the terminals. The devices are reconfigurable and promising for high voltage ESD protection applications.

Published
2019

2. Thin-Film FD-SOI BIMOS Topologies for ESD Protection

Author

Philippe Galy, Maud Vinet, Sorin Cristoloveanu, and Louise De Conti

Subjects
010302 applied physics, Materials science, business.industry, Silicon on insulator, 02 engineering and technology, 021001 nanoscience & nanotechnology, Network topology, 01 natural sciences, Matrix (mathematics), CMOS, 0103 physical sciences, Optoelectronics, Thin film, 0210 nano-technology, Metal gate, business
Abstract

BIMOS devices - fabricated with the 28 nm thin-film high-k/metal gate FD-SOI CMOS technology - are demonstrated to be promising candidates for ESD protection. This manuscript discloses layouts of various BIMOS topologies in the thin-film. Among them, a 2D matrix of BIMOS is proposed. Those novel topologies were conceived, measured and compared at room temperature. DC, TLP and VF - TLP characterization data are provided and discussed for further optimization.

Published
2019

3. GDNMOS and GDBIMOS devices for ESD protection in 28nm thin film UTBB FD-SOI technology

Author

Sorin Cristoloveanu, Philippe Galy, Louise De Conti, Maud Vinet, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), and STMicroelectronics [Crolles] (ST-CROLLES)

Subjects
Materials science, Silicon on insulator, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, law.invention, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Thin film, Hardware_ARITHMETICANDLOGICSTRUCTURES, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, NMOS logic, GDBIMOS, 010302 applied physics, business.industry, Electrostatic Discharges ESD, GDNMOS, 021001 nanoscience & nanotechnology, Cathode, Anode, CMOS, Logic gate, Optoelectronics, FD-SOI, Resistor, 0210 nano-technology, business, Hardware_LOGICDESIGN
Abstract

session 7: Characterization; International audience; GDNMOS (Gated Diode merged NMOS) and GDBIMOS (Gated Diode merged BIMOS) were fabricated using the 28nm thin film UTBB FD-SOI CMOS technology. Different connectivity conditions were measured and simulated. The devices are reconfigurable and promising for ESD protection applications.

Published
2018

4. Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies

Author

Maud Vinet, Louise De Conti, Sorin Cristoloveanu, Philippe Galy, Thomas Bedecarrats, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), and STMicroelectronics [Crolles] (ST-CROLLES)

Subjects
Materials science, Silicon, chemistry.chemical_element, Soi cmos, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, MOSFET, BIMOS, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Hardware_ARITHMETICANDLOGICSTRUCTURES, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Metal gate, 010302 applied physics, business.industry, Doping, Gated diode, Window (computing), 021001 nanoscience & nanotechnology, Gated Diode, CMOS, chemistry, Electrostatic Discharges, Optoelectronics, FD-SOI, 0210 nano-technology, business, SCR, Hardware_LOGICDESIGN
Abstract

session D: SoC, DFM.TCAD; International audience; This paper presents a new device named the Gated Diode merged BIMOS (GDBIMOS) which is fabricated using the 28nm UTBB FD-SOI high-k metal gate CMOS technology. It is highly reconfigurable and topologically robust for ESD protection. The suitable ESD window is achieved thanks to doping adjustment and to different possible gate connections.

Published
2017

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