Search

The von Neumann architecture is no longer sufficient for handling large-scale data. In-memory computing has emerged as the potent method for breaking through the memory bottleneck. A new 10T SRAM bitcell with row and column control lines called RC-SRAM is proposed in this article. The architecture based on RC-SRAM can achieve bi-directional and operand-controllable logic-in-memory and search operations through different signal configurations, which can comprehensively respond to various occasions and needs. Moreover, we propose threshold-controlled logic gates for sensing, which effectively reduces the circuit area and improves accuracy. We validate the RC-SRAM with a 28 nm CMOS technology, and the results show that the circuits are not only full featured and flexible for customization but also have a significant increase in the working frequency. At VDD = 0.9 V and T = 25 °C, the bi-directional search frequency is up to 775 MHz and 567 MHz, and the speeds for row and column Boolean logic reach 759 MHz and 683 MHz. [ABSTRACT FROM AUTHOR]

The von Neumann architecture is no longer sufficient for handling large-scale data. In-memory computing has emerged as the potent method for breaking through the memory bottleneck. A new 10T SRAM bitcell with row and column control lines called RC-SRAM is proposed in this article. The architecture based on RC-SRAM can achieve bi-directional and operand-controllable logic-in-memory and search operations through different signal configurations, which can comprehensively respond to various occasions and needs. Moreover, we propose threshold-controlled logic gates for sensing, which effectively reduces the circuit area and improves accuracy. We validate the RC-SRAM with a 28 nm CMOS technology, and the results show that the circuits are not only full featured and flexible for customization but also have a significant increase in the working frequency. At VDD = 0.9 V and T = 25 °C, the bi-directional search frequency is up to 775 MHz and 567 MHz, and the speeds for row and column Boolean logic reach 759 MHz and 683 MHz.

Content-addressable memory (CAM) has been part of the memory market for more than five decades. CAM can carry out a single clock cycle lookup based on the content rather than an address. Thanks to this attractive feature, CAM is utilized in memory systems where a high-speed content lookup technique is required. However, typical CAM applications only support exact matching, as opposed to approximate matching, where a certain Hamming distance (several mismatching characters between a query pattern and the dataset stored in CAM) needs to be tolerated. Recent interest in approximate search has led to the development of new CAM-based alternatives, accelerating the processing of large data workloads in the realm of big data, genomics, and other data-intensive applications. In this review, we provide an overview of approximate CAM and describe its current and potential applications that would benefit from approximate search computing.

Content-addressable memory (CAM) has been part of the memory market for more than five decades. CAM can carry out a single clock cycle lookup based on the content rather than an address. Thanks to this attractive feature, CAM is utilized in memory systems where a high-speed content lookup technique is required. However, typical CAM applications only support exact matching, as opposed to approximate matching, where a certain Hamming distance (several mismatching characters between a query pattern and the dataset stored in CAM) needs to be tolerated. Recent interest in approximate search has led to the development of new CAM-based alternatives, accelerating the processing of large data workloads in the realm of big data, genomics, and other data-intensive applications. In this review, we provide an overview of approximate CAM and describe its current and potential applications that would benefit from approximate search computing. [ABSTRACT FROM AUTHOR]

In online education, it is critical for the quality of education to evaluate and grade the assignments or examinations that students upload to the system. However, it is time-consuming to determine how well the circuit drawings prepared for the digital logic course, which is a fundamental course in computer engineering and similar disciplines, are not only correct but also compatible with the truth table. Content-addressable memory (CAM), also known as associative memory, is a data storage and retrieval unit. Typically, it is used instead of the conventional memories in fast-paced and time-sensitive applications such as address lookup in Internet routers, databases, and pattern recognition. CAMs implement the search process by comparing the content itself with a key instead of finding the address like the conventional memories. To see the effect of using binary content-addressable memory-based memory on the time spent scoring hand or digital-drawn logic circuits, it is compared with various data structures commonly used in logic simulation programs. I found a significant relationship (O(1)), indicating that the proposed architecture reduces the time complexity in the search process. This expression is the same as time complexity in hash tables.

The content-addressable memory is an especial memory cell that can search in its entire contents in one clock cycle. The Quantum-dot Cellular Automata (QCA) technology is also the promising nanotechnology for digital circuits implementation. This study presents and evaluates a new architecture for two-input XOR gate in the QCA technology. Then, the unique gate is developed using the developed XOR gate. The novel and efficient content-addressable memory is also developed using the developed unique gate. The QCADesigner tool is utilized to evaluate the functionally of these architectures. The implementation results prove that the developed content-addressable memory has 0.03 µ m 2 area, 0.5 clock cycles, and 37 cells. The developed architectures provide advantages in comparison with other architectures in terms of area, latency, and cell count. [ABSTRACT FROM AUTHOR]

In-memory computing is an attractive solution for reducing power consumption and memory access latency cost by performing certain computations directly in memory without reading operands and sending them to arithmetic logic units. Content-addressable memory (CAM) is an ideal way to smooth out the distinction between storage and processing, since each memory cell is a processing unit. CAM compares the search input with a table of stored data and returns the matched data address. The issues of constructing binary and ternary content-addressable memory (CAM and TCAM) based on ferroelectric devices are considered. A review of ferroelectric materials and devices is carried out, including on ferroelectric transistors (FeFET), ferroelectric tunnel diodes (FTJ), and ferroelectric memristors. [ABSTRACT FROM AUTHOR]

The brain has computational capabilities that surpass those of modern systems, being able to solve complex problems efficiently in a simple way. Neuromorphic engineering aims to mimic biology in order to develop new systems capable of incorporating such capabilities. Bio-inspired learning systems continue to be a challenge that must be solved, and much work needs to be done in this regard. Among all brain regions, the hippocampus stands out as an autoassociative short-term memory with the capacity to learn and recall memories from any fragment of them. These characteristics make the hippocampus an ideal candidate for developing bio-inspired learning systems that, in addition, resemble content-addressable memories. Therefore, in this work we propose a bio-inspired spiking content-addressable memory model based on the CA3 region of the hippocampus with the ability to learn, forget and recall memories, both orthogonal and non-orthogonal, from any fragment of them. The model was implemented on the SpiNNaker hardware platform using Spiking Neural Networks. A set of experiments based on functional, stress and applicability tests were performed to demonstrate its correct functioning. This work presents the first hardware implementation of a fully-functional bio-inspired spiking hippocampal content-addressable memory model, paving the way for the development of future more complex neuromorphic systems. [ABSTRACT FROM AUTHOR]

The binarized neural network (BNN) is one of the most promising candidates for low-cost convolutional neural networks (CNNs). This is because of its significant reduction in memory and computational costs, and reasonable classification accuracy. Content-addressable memory (CAM) can perform binarized convolution operations efficiently since the bitwise comparison in CAM matches well with the binarized multiply operation in a BNN. However, a significant design issue in CAM-based BNN accelerators is that the operational reliability is severely degraded by process variations during match-line (ML) sensing operations. In this paper, we proposed a novel ML sensing scheme to reduce the hardware error probability. Most errors occur when the difference between the number of matches in the evaluation ML and the reference ML is small; thus, the proposed hardware identified cases that are vulnerable to process variations using dual references. The proposed dual-reference sensing structure has >49% less ML sensing errors than that of the conventional design, leading to a >1.0% accuracy improvement for Fashion MNIST image classification. In addition, owing to the parallel convolution operation of the CAM-based BNN accelerator, the proposed hardware achieved >34% processing-time improvement compared with that of the digital logic implementation. [ABSTRACT FROM AUTHOR]

In-memory computing is an emerging computing paradigm that overcomes the limitations of exiting Von-Neumann computing architectures such as the memory-wall bottleneck. In such paradigm, the computations are performed directly on the data stored in the memory, which highly reduces the memory-processor communications during computation. Hence, significant speedup and energy savings could be achieved especially with data-intensive applications. Associative processors (APs) were proposed in the seventies and recently were revived thanks to the high-density memories. In this tutorial brief, we overview the functionalities and recent trends of APs in addition to the implementation of each content-addressable memory with different technologies. The AP operations and runtime complexity are also summarized. We also explain and explore the possible applications that can benefit from APs. Finally, the AP limitations, challenges, and future directions are discussed. [ABSTRACT FROM AUTHOR]

Content-addressable memories (CAMs) allow searching a pattern, processing in parallel all the data stored. Beyond-CMOS technologies can provide new opportunities to improve CAM memories implementations both at the device and architectural level. In this article, we propose a ternary content-addressable memory cell based on skyrmion technology. The proposed memory cell is based on skyrmion racetrack memory. The cell is able to signal if the bit contained in the cell in form of skyrmion corresponds to an electrical input, the target of the search operation. The proposed design, verified by means of micromagnetic simulations, has an area of 0.054 ÎĽ m2 and can perform a search operation in 3.3 ns with an energy of 10.5 fJ. The operation performed is non-destructive and does not require conversion between the magnetic and the electronic domains. For this reason, the designed cell has the potential to be used as a basic block for non-volatile CAM memories. Here, we propose also a layout structure to implement a CAM memory employing the proposed cell. This structure allows to achieve memory density comparable to traditional racetrack memories and execute at the same time CAM operations. [ABSTRACT FROM AUTHOR]

In-memory computing is an attractive solution for reducing power consumption and memory access latency cost by performing certain computations directly in memory without reading operands and sending them to arithmetic logic units. Content-addressable memory (CAM) is an ideal way to smooth out the distinction between storage and processing, since each memory cell is a processing unit. CAM compares the search input with a table of stored data and returns the matched data address. The issues of constructing binary and ternary content-addressable memory (CAM and TCAM) based on ferroelectric devices are considered. A review of ferroelectric materials and devices is carried out, including on ferroelectric transistors (FeFET), ferroelectric tunnel diodes (FTJ), and ferroelectric memristors.

Recently, resistance switch-based content-addressable memory (RCAM) has been proposed as an alternative to the mainstream static random-access memory-based CAM because of its high integration potential and low static energy consumption. However, RCAM has a lower data density due to the use of a pair of resistance switches for a single bit of contents (0.5 bit/switch) than resistive random access memory (1 bit/switch). In this paper, we propose a new type of RCAM referred to as combination-encoding CAM (CECAM). In the N-CECAM, a single unit consists of N high and N low resistance state switches whose combination collectively represents binary contents, yielding a data density of approximately 0.85 bit/switch when N = 10, for instance. The key to the CECAM is the encoding of an n-bit search key as a 2N-digit key and its decoding. To this end, we propose a simple algorithm for encoding and decoding and its implementation in digital circuitry.

Cross-point-array nonvolatile ternary content-addressable memory (CPA nvTCAM) has recently emerged as an alternative to static random-access-memory-type TCAM, based on increased demands for high-capacity and low-power attributes. The CPA structure has various structural weaknesses such as the searchline (SL) combining with the dischargeline and the minimum line pitch of the matchline (ML). This study analyzes these weaknesses in detail for the first time and resolves the issues caused by these weaknesses using the proposed novel ML shield scheduling method with a matching probability-based flexible searching time technique (MLSS + MPFST). The proposed MLSS + MPFST resolves various issues and achieves greater than sixfold smaller cell size (8F2) than the non-CPA nvTCAM with the smallest cell size. To verify the proposed schemes, the Monte Carlo HSPICE simulations were performed using a 22-nm industry-compatible bulk FinFET model parameter in 20-nm resistive memory technology at a circuit level, and the gem5 simulations were performed at a system level. The simulation results indicated that the CPA nvTCAM with the proposed MLSS + MPFST achieved a comparable search operation time of 1 ns and a slight power consumption overhead of 10% but an acceptable system performance overhead of less than 0.6% by resolving the various issues, compared with the non-CPA nvTCAM having the best performance. [ABSTRACT FROM AUTHOR]

This paper presents the design of hardened translation lookaside buffer based on Spaced Transistor Groups (STG) DICE cells in 65-nm bulk CMOS technology. The resistance to impacts of single nuclear particles is achieved by spacing transistors in two groups together with transistors of the output combinational logic. The elements contain two spaced identical groups of transistors. Charge collection from particle tracks by only transistors of just one of the two groups doesn’t lead to the cell upset. The proposed logical element of matching based on the STG DICE cell for a content-addressable memory was simulated using TCAD tool. The results show the resistance to impacts of single nuclear particles with linear energy transfer (LET) values up to 70 MeV×cm2/mg. Short-term noise pulses in combinational logic of the element can be observed in the range of LET values from 20 to 70 MeV×cm2/mg.

Bitmap index is recognized as a promising candidate for online analytics processing systems, because it effectively supports not only parallel processing but also complex and multi-dimensional queries. However, bitmap index creation is a time-consuming task. In this paper, by taking full advantage of massive parallel computing of field-programmable gate array (FPGA), two hardware accelerators of bitmap index creation, namely BIC64K8 and BIC32K16, are originally proposed. Each of the accelerator contains two primary components, namely an enhanced content-addressable memory and a query logic array module, which allow BIC64K8 and BIC32K16 to index 65 536 8-bit words and 32 768 16-bit words in parallel, at every clock cycle. The experimental results on an Intel Arria V 5ASTFD5 FPGA prove that at 100 MHz, BIC64K8 and BIC32K16 achieve the approximate indexing throughput of 1.43 GB/s and 1.46 GB/s, respectively. The throughputs are also proven to be stable, regardless the size of the data sets. More significantly, BIC32K16 only consumes as low as 6.76% and 3.28% of energy compared to the central-processing-unit- and graphic-processing-unit-based designs, respectively.

Comparison elements on base the STG DICE cell and the logical element “Exclusive OR” for a content-addressable memory were designed and simulated. The comparison element contains two identical joint groups of transistors that are spaced on the chip by the distance of four micrometers, so the loss of data in STG DICE cell practically excluded. On the characteristics of the new 65-nm CMOS comparison element, we predict the hardness of these item to single event rate (SER) more to hundred times compared to elements on 6-transistors cells and the standard DICE cell with distances 0.5-0.6 μm between mutually sensitive nodes.

Despite the impressive search rate of one key per clock cycle, the update stage of a random-access-memory-based content-addressable-memory (RAM-based CAM) always suffers high latency. Two primary causes of such latency include: 1) the compulsory erasing stage along with the writing stage and 2) the major difference in data width between the RAM-based CAM (e.g., 8-bit width) and the modern systems (e.g., 256-bit width). This brief, therefore, proposes an efficient input/output (I/O) architecture of RAM-based binary CAM (RCAM) for low-latency update. To achieve this goal, three techniques, namely centralized erase RAM, bit-sliced, and hierarchical-partitioning, are proposed to eliminate the latency of the erasing stage, as well as to allow RCAM to exploit the bandwidth of modern systems effectively. Several RCAMs, whose data width ranges from 8 bits to 64 bits, were integrated into a 256-bit system for the evaluation. The experimental results in an Intel Arria V 5ASTFD5 field-programmable gate array prove that, at 100 MHz, the proposed designs achieve at least 9.6 times higher I/O efficiency as compared to the traditional RCAM. [ABSTRACT FROM AUTHOR]

Highlights • A single set of Memristor crossbar array is extended for bidirectional synaptic weighting operation, which is convenient and cost-effective in hardware implementation of artificial neural networks. • The on-chip learning circuits and related learning algorithm for memristive BAM are considered to train the system to memorize pattern pairs, together with a novel programming strategy to ease the process of tuning memristance. • We have implemented and demonstrated meaningful pattern can be trained and recalled by the proposed memristive BAM system. • BAM neuron activation function is realized by digital circuit element JK flip-flop. • The Verilog-AMS design methodolgy adopted in this study can be a good candidate for system level design of memristor-based large scale ANN circuit when both digital circuit element and analog memristors are employed. Abstract Recently, memristor as an emerging device has been used as the basic synapse realization component for the circuit implementation of artificial neural networks. Following this trend, this paper studies the circuit realization of a memristor-based bidirectional associative memory (BAM) system that extends the memristor crossbar array structure for bidirectional synaptic weighting operation. The neuron cell in BAM is represented by digital circuit element JK flip-flop for hardware cost-saving. Meanwhile a novel memristor programming strategy is also considered and examined to ease the on-chip learning. The design of such memristive BAM circuit system is conducted by hardware description language Verilog-AMS and has been validated in a commercial circuit simulation environment via a case study. Test results show that a set of binary character patterns can be memorized and recalled successfully by the trained memristive BAM system. [ABSTRACT FROM AUTHOR]

We introduce CAMsure, the first realization of secure Content Addressable Memory (CAM) in the context of approximate search using near-neighbor algorithms. CAMsure provides a lightweight solution for practical secure (approximate) search with a minimal drop in the accuracy of the search results. CAM has traditionally been used as a hardware search engine that explores the entire memory in a single clock cycle. However, there has been little attention to the security of the data stored in CAM. Our approach stores distance-preserving hash embeddings within CAM to ensure data privacy. The hashing method provides data confidentiality while preserving similarity in the sense that a high resemblance in the data domain is translated to a small Hamming distance in the hash domain. Consequently, the objective of near-neighbor search is converted to approximate lookup table search which is compatible with the realizations of emerging content addressable memories. Our methodology delivers on average two orders of magnitude faster response time compared to RAM-based solutions that preserve the privacy of data owners. [ABSTRACT FROM AUTHOR]

Recent experiments on voltage-driven magneto-electric (ME) switching of ferromagnets has shown potential for future low-energy, high-speed, nonvolatile spintronic memory. In this letter, we first analyze two different ME devices-an ME magnetic-tunnel-junction (ME-MTJ) device and an ME-xnor device-with respect to writability, readability, and switching speed. The basic operational principle of ME devices is the fact that, by applying appropriate voltage pulses on the ME oxides in contact with their respective ferromagnets, a 180° switching of the magnetization direction can be achieved. Our analysis is based on a coupled stochastic magnetization dynamics and electron transport model. Subsequently, we show that the decoupled read/write path of ME-MTJs can be utilized to construct an energy-efficient dual-port memory, which can be instrumental in improving the memory throughput. Furthermore, we also propose a novel nonvolatile, content-addressable, memory that exploits the compact xnor operation enabled by the ME-xnor device. [ABSTRACT FROM PUBLISHER]

Hopfield networks are a variant of associative memory that recall patterns stored in the couplings of an Ising model. Stored memories are conventionally accessed as fixed points in the network dynamics that correspond to energetic minima of the spin state. We show that memories stored in a Hopfield network may also be recalled by energy minimization using adiabatic quantum optimization (AQO). Numerical simulations of the underlying quantum dynamics allow us to quantify AQO recall accuracy with respect to the number of stored memories and noise in the input key. We investigate AQO performance with respect to how memories are stored in the Ising model according to different learning rules. Our results demonstrate that AQO recall accuracy varies strongly with learning rule, a behavior that is attributed to differences in energy landscapes. Consequently, learning rules offer a family of methods for programming adiabatic quantum optimization that we expect to be useful for characterizing AQO performance.

We conducted two eye-tracking experiments investigating the processing of the Mandarin reflexive ziji in order to tease apart structurally constrained accounts from standard cue-based accounts of memory retrieval. In both experiments, we tested whether structurally inaccessible distractors that fulfill the animacy requirement of ziji influence processing times at the reflexive. In Experiment 1, we manipulated animacy of the antecedent and a structurally inaccessible distractor intervening between the antecedent and the reflexive. In conditions where the accessible antecedent mismatched the animacy cue, we found inhibitory interference whereas in antecedent-match conditions, no effect of the distractor was observed. In Experiment 2, we tested only antecedent-match configurations and manipulated locality of the reflexive-antecedent binding (Mandarin allows non-local binding). Participants were asked to hold three distractors (animate vs. inanimate nouns) in memory while reading the target sentence. We found slower reading times when animate distractors were held in memory (inhibitory interference). Moreover, we replicated the locality effect reported in previous studies. These results are incompatible with structure-based accounts. However, the cue-based ACT-R model of Lewis and Vasishth (2005) cannot explain the observed pattern either. We therefore extend the original ACT-R model and show how this model not only explains the data presented in this article, but is also able to account for previously unexplained patterns in the literature on reflexive processing. [ABSTRACT FROM AUTHOR]

With the context of individualized product design in mass customization, the practice of product configuration is transformed from traditional unidirectional process into bidirectional design interactions. In this interactive configuration manner, maintaining the consistency of configuration assignments, often referred to as consistency restoration, is one of the primary issues which should be addressed. The task of consistency restoration faces two great challenges: the uncertainty and individualized flexibility of customer requirements. The uncertainty turns problem dynamic and deteriorates the computational complexity of existing consistency restoration methods. The individualized flexibility turns the task of consistency restoration ill-structured. Consequently, these two characteristics increase the response time in interactive configuration and make companies face the challenge of ‘customization-responsiveness squeeze’. To leverage this problem, this paper proposes a responsive approach to facilitate the task of consistency restoration. A methodology based on content-addressable memory (CAM) is established, which compiles a CSP-based consistency restoration into a memory recalling process and automatically corrects the incompleteness and inconsistency within the memory. Specific orientation mechanism based on customer preference is proposed to introduce customer flexibility into CAM model. The resulting oriented-CAM method is demonstrated by a case study and the performance and responsiveness are analyzed. [ABSTRACT FROM AUTHOR]

This paper reviews recent progress in nanophotonics, a novel optical technology proposed by one of the authors (M. Ohtsu). Nanophotonics utilizes the local interaction between nanometric particles via optical near fields. The optical near fields are the elementary surface excitations on nanometric particles, that is, dressed photons that carry the material energy. Of the variety of qualitative innovations in optical technology realized by nanophotonics, this paper focuses on devices and systems. The principles of device operation are reviewed considering the excitation energy transfer via the optical near-field interaction and subsequent dissipation. As representative examples, the principles of a nanophotonic and gate, not gate, and optical nanofountain are described. Experimental results for operating devices using CuCl quantum dots (QDs), InAlAs QDs, and nanorod ZnO double quantum wells are described. Using a systems-perspective approach, the principles of content-addressable memory based on nanophotonic device operations and experimental results are reviewed. The hierarchy of optical near-field interactions is discussed, and its application to a multilayer memory retrieval system is demonstrated. [ABSTRACT FROM PUBLISHER]

This paper presents a match-line (ML) sensing scheme that distinguishes a match from a miss by first shunting every ML with a fixed negative resistance; then exciting the MLs with an initial charge, and subsequently observing their voltage developments. It is shown that the voltage on the matched ML will grow. to VDD, as in an unstable system, whereas the voltage on a missed ML will decay to zero, as in a stable system. Since the initial excitation charge on the ML's can be as low as the noise level in the system, this scheme can approach the minimum possible energy consumption level for match-line sensing. We have implemented, in 0.18 µm CMOS, a 144 × 144 ternary CAM array that includes the stability-based sensing scheme along with two previously-reported sensing schemes. The measured results confirm the power savings of the proposed sensing scheme. In addition, the CAM includes a pipelined search-line (SL) architecture that can reduce the SL portion of CAM power by up to 50%. [ABSTRACT FROM AUTHOR]

This paper investigates an information-theoretic design principle, intended to support an evolution of a memory structure fitting a specific selection pressure: associative information transfer through the structure. The proposed criteria measure how much does associativity in memory add to the information transfer in terms of precision, recall and effectiveness. The study also introduces a conjectural analogy between memory retrieval and self-replication, with DNAas a partially-associative memory containing relevant information. DNA decoding by a complicated protein machinery ("cues" or "keys") may correspond to an associative recall: i.e., a replicated offspring is an associatively-recalled prototype. The proposed information-theoretic criteria intend to formalize the notion of information transfer involved in self-replication, and enable bio-inspired design of more effective memory structures. [ABSTRACT FROM AUTHOR]

Ternary content addressable memory (TCAM) is an important component for many applications. For TCAM-based networking systems, the rapidly growing size of routing tables brings with it the challenge to design higher search speeds and lower power consumption. In this work, two techniques are proposed to realize high-performance and low-power TCAM for IP address lookup. One technique is the tree AND-type match-line scheme for high search speed. The other technique is the segmented search-line scheme for low power. The implemented 1.8 V 0.18 μm 256 × 128b TCAM macro achieves a 1.56 ns search time using a 1.42 fJ/bit/search of energy. [ABSTRACT FROM AUTHOR]

Abstract: The growing complexity of Field Programmable Gate Arrays (FPGA’s) is leading to architectures with high input cardinality look-up tables (LUT’s). This paper describes a methodology for area-optimal combinational technology mapping, specifically designed for such FPGA architectures. This methodology, called LURU, leverages the parallel search capabilities of Content-Addressable Memories (CAM’s) to outperform traditional mapping algorithms in both execution time and quality of results. The LURU algorithm is fundamentally different from other techniques for technology mapping in that LURU uses textual representations of circuit topology in order to efficiently store and search for circuit patterns in a CAM. A circuit is mapped to the target LUT technology using exact, inexact, or hybrid matching techniques. Common subcircuit expressions (CSE’s) are also identified and used for architectural optimization—a small set of CSE’s is shown to effectively cover an average of 96% of the test circuits. LURU was tested with the ISCAS ’85 suite of combinational benchmark circuits and compared with the mapping algorithms FlowMap and CutMap. The area requirement of LURU’s mapping is, on average, 20% less than FlowMap or CutMap. The asymptotic runtime complexity of LURU is shown to be better than that of both FlowMap and CutMap. [Copyright &y& Elsevier]

This paper is concerned with content-addressable memory (CAM), which is a kind of functional memory. Flexible multiport content-addressable memory (FMCAM) is proposed, in which flexible retrieval functions and a multiport structure are realized. The implementation and an evaluation are presented. It is known that CAM offers high speed of the matching retrieval function. On the other hand, there are problems in practice concerning the relation between the processing speed and the number of comparators, and also the problem of cost, which have prevented its widespread use. Consequently, we developed the following FMCAM. Multiport CAM is realized by reducing the increase of the number of comparators while retaining high speed matching retrieval functions. Functions for flexible retrieval can be added by implementation in an FPGA. By the categorization process and the use of a ring counter, multiple processing operations can be performed immediately while reducing the number of comparators. This improves the performance of the CAM itself. Another advantage is that FMCAM alone can perform the same processing in situations in which parallel CAM should be applied. After implementing the proposed FMCAM, several tests were performed for comparison. Excellent values were obtained: the AT product was 37.5% lower on average than in conventional CAM, and the increase in hardware complexity was by a factor of 1.57 even if the number of ports was increased by a factor of 4. [ABSTRACT FROM AUTHOR]

A novel, low-energy content addressable memory (CAM) structure is presented which achieves an approximately four-fold improvement in energy per access, compared to a standard parallel CAM, when used as tag storage for caches. It exploits the address patterns commonly found in application programs, where testing the four least significant bits of the tag is sufficient to determine over 90% of the tag mismatches; the proposed CAM checks those bits first and evaluates the remainder of the tag only if they match. Although, the energy savings come at the cost of a 25% increase in search time, the proposed CAM organization also supports a parallel operating mode without a speed loss but with reduced energy savings. [ABSTRACT FROM AUTHOR]

For the purpose of realizing a new intelligent system and its simplified VLSI implementation, we propose a new nonvolatile analog memory called “switched diffusion analog memory with feedback circuit (FBSDAM).” FBSDAM has linear writing and erasing characteristics. Therefore, FBSDAM is useful for memorizing an analog value exactly. We also propose a new analog content-addressable memory (CAM) which has neural-like learning and discriminating functions which discriminate whether an incoming pattern is an unknown pattern or a stored pattern. We design and fabricate the CAM using FBSDAM by means of the 4 μm double-poly single-metal CMOS process and nonvolatile analog memory technology which are developed by us. The chip size is 3.1 mm×3.1 mm. We estimate that the CAM is composed of 50 times fewer transistors and requires 70 times fewer calculation steps than a typical digital computer implemented using similar technology. [ABSTRACT FROM AUTHOR]

A compact rectangular solid representation of three-dimensional (3-D) objects is proposed for motion planning of intelligent robots. A VLSI-oriented algorithm that transforms the discrete point representation of a 3-D object to a rectangular solid representation is considered. A new architecture is proposed to perform matching operations between a rectangular solid and discrete points in parallel. Performance evaluation shows that the VLSI processor that implements the algorithm is 25,000 times faster than a RAM-based architecture. © 1997 Scripta Technica, Inc. Syst Comp Jpn, 28(3): 54–61, 1997 [ABSTRACT FROM AUTHOR]

The primacy of memristors for the realization of the synaptic circuit makes this element a promising component for implementing Artificial Neural Networks (ANN). However, integrating memristors with other ANN components is still an open area of research. Therefore, a circuit-level hybrid CMOS/Memristor architecture for implementing Bidirectional Associative Memory (BAM) is proposed in this paper. A passive bi-directional pre-differentiation crossbar architecture has been utilized and applied for the realization of synaptic weights. A compact, low voltage CMOS neuron that consumes a low amount of power is also designed. The noise tolerance of the proposed hardware is evaluated for typical networks with different sizes and a number of stored patterns. It is demonstrated that the hardware pattern retrieval rate is similar to its software-based counterpart. The influence of memristor non-idealities on BAM is also investigated for the first time, and a practical method has been introduced to deal with this issue. In comparison to the available circuit-level hardware implementation of memristive associative memories, the proposed circuit consumes significantly less power and retrieves the stored patterns notably faster. [ABSTRACT FROM AUTHOR]