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Field effect transistors (FETs) in plasmonic regimes of operation could detect terahertz (THz) radiation and operate as THz interferometers, spectrometers, frequency-to-digital converters and THz modulators and sources. We report on the development of compact models for Si MOS (Metal-Oxide-semiconductor) and heterostructure-based plasmonic FETs (or TeraFETs) suitable for circuit design in the THz range and based on the multi-segment unified charge control model. This model accounts for the electron inertia effect (by incorporating segmented Drude inductances), for the ballistic field effect mobility, which is proportional to the channel length, for parasitic resistances and capacitances and for the leakage current. It is validated by comparison with experimental data and TCAD simulation results. The model can be used for simulation and optimization of sub-THz and THz detectors. Our simulations use up to 200 segments in the device channel. The results are also in good qualitative agreement with the hydrodynamic simulations. Applications of our model could dramatically reduce astronomical design costs of nanoscale VLSI reaching US$1.5 billion for the 3 nm technological node. [ABSTRACT FROM AUTHOR]

We present an update of the Rensselaer Polytechnic Institute (RPI) thin-film transistor (TFT) compact model. The updated model implemented in Simulation Program with Integrated Circuit Emphasis (SPICE) accounts for the gate voltage-dependent channel layer thickness, enables the accurate description of the direct current (DC) characteristics, and uses channel segmentation to allow for terahertz (THz) frequency simulations. The model introduces two subthreshold ideality factors to describe the control of the gate voltage on the channel layer and its effect on the drain-to-source current and the channel capacitance. The calculated field distribution in the channel is used to evaluate the channel segment parameters including the segment impedance, kinetic inductance, and gate-to-segment capacitances. Our approach reproduces the conventional RPI TFT model at low frequencies, fits the measured current–voltage characteristics with sufficient accuracy, and extends the RPI TFT model applications into the THz frequency range. Our calculations show that a single TFT or complementary TFTs could efficiently detect the sub-terahertz and terahertz radiation. [ABSTRACT FROM AUTHOR]

Dry electrodes are a promising solution for prolonged EEG signal acquisition, whereas wet electrodes may lose their signal quality in the same situation and require skin preparation for set-up. Here, we review the impedance and noise of passive and active dry EEG electrodes. In addition, we compare noise and input impedance of the EEG amplifiers. As there are multiple definitions of impedance in each EEG system, they are all first defined. Electrodes must be compatible with amplifiers to accurately record EEG signals. This implies that their impedance plays a significant role in amplifier compatibility and affects total input-referred noise. Therefore, we review the impedance and noise of state-of-the-art amplifiers and electrodes. Furthermore, we compare the various structures and materials used and their final impedance to that of wet electrodes. Finally, we compare state-of-the-art electrodes and amplifiers to the standards of the IFCN and IEC80601-2-26. We investigate bottlenecks and propose a guideline for future work on passive and active dry electrodes, as well as EEG amplifiers. [ABSTRACT FROM AUTHOR]

An approach to merge superconducting Josephson junction (JJ) devices with nanoscale Graphene devices in order to achieve high gain-bandwidth-product on the order of THz is proposed. While JJ-based devices have existed since nearly 1962, interfacing or interacting with them with standard electrical systems has been a challenge for several reasons, including operating temperature, switching speed, and low-signal sensitivity. In this article, we investigated the possibility of utilizing JJ's so-called ac effect in order to generate high frequency signals that can be accommodated by high speed nanoscale devices. Graphene nanoribbon field effect transistors (GNRFET) have been emphasized for their very high frequency operation that is appropriate to accommodate the very high switching speed of the JJ devices. The article is based on the ac JJ effect with generating a sinusoidal current whose frequency directly scales with voltage. For a single-stage GNRFET CS amplifier, a gain of 35.7 dB with a bandwidth of 217 GHz was achieved, while 10.8 dB with a unitary gain of 2.5 THz was also accomplished. This article details the design and interface of the JJ with GNRFET devices, targeting high frequency signal generation on the order of hundreds of GHz to THz, with the purpose of providing a foundation on top of which further developments can be made, especially in the areas of communications, medical devices, instrumentation and measurement devices, high-speed imaging, subinfrared antenna arrays, and computer architecture and hardware, by providing a system, which can respond to speeds on the order of fifty to one hundred times faster than current commercial computer equipment or signal generation/processing. [ABSTRACT FROM AUTHOR]

We propose architectural advances in low voltage, energy-efficient, level shifters. A write assist circuit is introduced, to support the up-conversion of deep subthreshold inputs. We also present an approach to reduce the leakage current in split signal output stages. A prototype was created in a 130 nm bulk CMOS process, and some samples were successfully tested for input voltages as low as 5 mV. For 10 measured samples, the mean functional, minimum, input voltage was 31.1 mV. By applying body bias to selected NMOS transistors to compensate for process and mismatch variation, the measured mean minimum input voltage was lowered to 14.3 mV. The leakage reduction in the split control output driver reduces the driver leakage by a factor of 8. The designed level shifter was found to be energy efficient compared to published structures, it consumed an average of 25.9 fJ per conversion in post-layout simulations and the delay was measured to 21.08 ns at 300 mV input signals. [ABSTRACT FROM AUTHOR]

This brief presents an approach that dynamically exploits content dependencies in asymmetric memory cells. By using a capacitive, logic-value majority circuit and an extra column of memory cells, words are conditionally flipped during write operations to reach the more beneficial state for storage. A 1-kb SRAM block of low-voltage memory cells was implemented and manufactured in a 130-nm CMOS. The memory cells were made writable and read-stable at low supply voltages with a single-ended write and single-ended read structure using six multithreshold transistors that give rise to an asymmetric retention power. At a supply voltage of 350 mV, the content-dependent leakage power in the asymmetric memory cell is 23 times smaller when storing logic “1”s compared with logic “0”s. A derived statistical model suggests that the mean, wordwise, static power savings of the word-flipping scheme become 15.70% for 8-bit words of uniform bit probability. For the implemented SRAM macro, the mean improvement for the retention power is, including flip logic and decoder and driver overheads, found to be 14.69%. In boundary tests, by writing all words full of undesired values, the power saving becomes 80.37%, while writing all words full of desired values causes a power penalty of 6.14%. Measurement results confirm the improvement in retention power with a ten-chip mean improvement of 11.93% for the same data set. [ABSTRACT FROM AUTHOR]

We describe a compact terahertz (THz) SPICE/advanced design system (ADS) model based on the extended Enz-Krummenacher-Vittoz (EKV) MOSFET model with channel segmentation but accounting for the new physics of the electron transport at THz frequencies. The model includes the distributed Drude inductance representing the electron inertia. The channel segmentation allows reproducing the nonuniformity in the electron density excitations and the plasmonic oscillations at THz frequencies. The model was validated by comparing the simulation results with the analytical THz detection theory and experimental data for silicon MOSFETs and FinFETs with gate lengths ranging from 60 to 800 nm. The good agreement between the simulated and analytical results and experimental data revealed the significance of the electron inertia and demonstrated the improved validity of the model at higher frequencies with an increase in the number of segments. The model was used to simulate a novel TeraFET THz spectrometer and the resonant TeraFET THz detector. These results show the model utility for device and circuit simulations at sub-THz and THz frequencies. An important application of the THz spectrometer simulation is in the design of a single field-effect transistor (FET) THz vector detector that could be extremely useful for 5G (and beyond) line-of-sight applications. [ABSTRACT FROM AUTHOR]

A low-power level shifter capable of up-converting sub-50 mV input voltages to 1 V has been implemented in a 28 nm FDSOI technology. Diode connected transistors and a single-NWELL layout strategy have been used along with poly and back-gate biasing techniques to achieve an adequate balance between the drive strength of the pull-up and pull-down networks. Measurements showed that the lowest input voltage levels, which could be upconverted by the 10 chip samples, varied from 39 mV to 52 mV. Half of the samples could upconvert from 39 mV to 1 V. The simulated energy consumption of the level shifter was 5.2 fJ for an up-conversion from 0.2 V to 1 V and 1 MHz operating frequency. [ABSTRACT FROM AUTHOR]

We describe an improved compact SPICE/ADS model validated for the terahertz (THz) frequency range in a large dynamic range. The model validation was done by comparing the simulation results with the analytical THz detection theory and with the measured data for the 130-nm InGaAs/AlGaAs HFETs. This validation revealed the importance of the electron inertia and the crucial role of the gate and drain leakage currents at high intensities of the impinging THz radiation. The modeling results are in good agreement with the analytical THz detection theory and with the measured sub-THz response dependence on the bias, power, and polarization. It also demonstrates the response saturation previously measured at high intensities, and the resonant detection predicted by the detection theory for higher mobility devices. The model has been implemented in AIM-SPICE, ADS, and Cadence and could be used for design, characterization, and parameter extraction of sub-THz and THz devices and integrated circuits. [ABSTRACT FROM AUTHOR]

In this paper, a dual-mode low-power, high dynamic-range receiver circuit is designed for the interface with a capacitive micromachined ultrasonic transducer. The proposed ultrasound receiver chip enables the development of an in-probe digital beamforming imaging system. The flexibility of having two operation modes offers a high dynamic range with minimum power sacrifice. A prototype of the chip containing one receive channel, with one variable transimpedance amplifier (TIA) and one analog to digital converter (ADC) circuit is implemented. Combining variable gain TIA functionality with ADC gain settings achieves an enhanced overall high dynamic range, while low power dissipation is maintained. The chip is designed and fabricated in a 65 nm standard CMOS process technology. The test chip occupies an area of 76\mu \textm\; \times 170 \mu \textm. A total average power range of 60–240 \mu \textW for a sampling frequency of 30 MHz, and a center frequency of 5 MHz is measured. An instantaneous dynamic range of 50.5 dB with an overall dynamic range of 72 dB is obtained from the receiver circuit. [ABSTRACT FROM PUBLISHER]

This paper presents a low-power 9-bit compiled successive-approximation register (SAR) analog-to-digital converter (ADC) for Bluetooth low energy receivers. The ADC is compiled from a SPICE netlist, a technology rule file, and an object definition file into a design rule check and layout versus schematic clean layout and schematic in 28-nm FDSOI. The compiled SAR ADC reduces the design time necessary to port to a new technology, and to demonstrate technology porting the same SAR ADC architecture is compiled in 28-nm FDSOI with Input/Output (IO) transistors. This paper also includes a comparator clock generation loop that uses the bottom plate of the capacitive digital-to-analog converter. The proposed compiled core transistor SAR ADC achieves the state-of-the-art Figure of Merit (FoM) of 2.7 fJ/conv.step at 2 MS/s, and 3.5 fJ/conv.step at 20 MS/s with an area of 0.00312 mm2. [ABSTRACT FROM AUTHOR]

Fully digitized 2D ultrasound transducer arrays require one ADC per channel with a beamforming architecture consuming low power. We give design considerations for per-channel digitization and beamforming, and present the design and measurements of a continuous time delta-sigma modulator (CTDSM) for cardiac ultrasound applications. By integrating a mixer into the modulator frontend, the phase and frequency of the input signal can be shifted, thereby enabling both improved conversion efficiency and narrowband beamforming. To minimize the power consumption, we propose an optimization methodology using a simulated annealing framework combined with a C++ simulator solving linear electrical networks. The 3rd order single-bit feedback type modulator, implemented in a 65 nm CMOS process, achieves an SNR/SNDR of 67.8/67.4 dB across 1 MHz bandwidth consuming 131 \mu\textW of power. The achieved figure of merit of 34.2 fJ/step is comparable with state-of-the-art feedforward type multi-bit designs. We further demonstrate the influence to the dynamic range when performing dynamic receive beamforming on recorded delta-sigma modulated bit-stream sequences. [ABSTRACT FROM PUBLISHER]

This brief presents an inverter-based low-noise single-ended to differential continuous-time variable gain amplifier (VGA) for 2–6-MHz second harmonic cardiac ultrasound imaging probes. The proposed VGA is based on a transimpedance amplifier and composed of resistive arrays and three equal inverters to form the resistive feedback loop. The inverters operate in the class C mode by being biased in the subthreshold region to improve both the power and noise performances of the VGA. The 6-bit thermometer resistive arrays can control the gain range from −1 to 21 dB for a 2-D piezoelectric transducer (PZT) model, and for a 50- \Omega source resistor, the gain range is from 20 to 26 dB. The second harmonic distortion (HD2) is lower than −55 dB in most cases due to the single-ended to differential conversion, and the equivalent input referred noise is 7 \text{nV}/\sqrt{\text{Hz}} at 5 MHz with the maximum gain. The VGA is fabricated in 65-nm CMOS technology and has the power consumption of 54 \mu\text{W}$ at a supply voltage of 0.5 V. The die size of the VGA is 154\ \mu\text{m} \times 102\ \mu\text{m}. [ABSTRACT FROM PUBLISHER]

A low noise, low power, single‐ended to differential switched‐capacitor variable gain amplifier (SC‐VGA) is designed and fabricated in 0.18 µm complementary metal‐oxide‐semiconductor technology for a 2–6 MHz second harmonic cardiac ultrasound imaging system. The SC‐VGA has 10‐bit dB‐linear gain steps from −14 to 32 dB which are distributed into two stages, and each stage has a single‐stage operational trans‐conductance amplifier using floating capacitors to save the power and improve the noise performance. The first stage converts the single‐ended input to differential outputs with the 2‐bit gain control from 0 to 18 dB, and the second stage exploits 8‐bit capacitor arrays to control the gain from −14 to 14 dB. The measured results show that the second harmonic distortion is <−50 dB, the third harmonic distortion is <−50 dB and the integrated noise from 2 to 6 MHz at the output is −64 dBm at the maximum gain and a sampling frequency of 30 MHz. The simulation results match well with the measured results. The SC‐VGA works at a supply voltage of 1.6 V and consumes the current of 900 µA. The die size of the SC‐VGA is 387 µm × 502 µm. [ABSTRACT FROM AUTHOR]

A low-power high-energy-efficiency switched current (SI)-based beamformer is designed and fabricated in a 180-nm complementary metal–oxide–semiconductor technology. The beamformer is implemented using an analog RAM (ARAM) delay and sum approach. A new bias-shared SI architecture is proposed for the low-power ARAM implementation. The highlight of the proposed architecture is that the number of memory cells in the ARAM can be increased without a proportional increase in power consumption. This feature allows the beamformer to have a longer memory depth and higher flexibility for wave shaping during the beam formation. As proof of concept, 16 channels have been implemented for the beamformer, each containing 16 memory cells. The current consumption of a single memory cell is 27 \mu\mathrmA . The maximum input signal frequency is 10 MHz, and the sampling frequency is 25 MHz. The measurement results for the beamformer show a 60-dB signal-to-noise ratio after summation. The total current consumption of the chip, including the beamformer along with the bias generation and a digital controller, is 7 mA, and it occupies an active area of 1.3 mm2. [ABSTRACT FROM AUTHOR]